def main(): dut = ASMIcon(sdram_phy, sdram_geom, sdram_timing) initiator1 = Initiator(my_generator_r(), dut.hub.get_port()) initiator2 = Initiator(my_generator_w(), dut.hub.get_port()) dut.finalize() logger = DFILogger(dut.dfi) def end_simulation(s): s.interrupt = initiator1.done and initiator2.done fragment = dut.get_fragment() + initiator1.get_fragment() + initiator2.get_fragment() + \ logger.get_fragment() + \ Fragment(sim=[end_simulation]) sim = Simulator(fragment, TopLevel("my.vcd")) sim.run(700)
def main(): controller = ASMIcon(sdram_phy, sdram_geom, sdram_timing) bridge = wishbone2asmi.WB2ASMI(l2_size//4, controller.hub.get_port()) controller.finalize() initiator = wishbone.Initiator(my_generator()) conn = wishbone.InterconnectPointToPoint(initiator.bus, bridge.wishbone) logger = DFILogger(controller.dfi) def end_simulation(s): s.interrupt = initiator.done fragment = controller.get_fragment() + \ bridge.get_fragment() + \ initiator.get_fragment() + \ conn.get_fragment() + \ logger.get_fragment() + \ Fragment(sim=[end_simulation]) sim = Simulator(fragment, TopLevel("my.vcd")) sim.run()