def build_drive_system(np): # driver system CPU is always simple, so is the memory # Note this is an assignment of a class, not an instance. DriveCPUClass = AtomicSimpleCPU drive_mem_mode = 'atomic' DriveMemClass = SimpleMemory cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == 'mips': drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == 'sparc': drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == 'x86': drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == 'arm': drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, bm[1], options.dtb_filename, cmdline=cmdline) # Create a top-level voltage domain drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) # Create a source clock for the system and set the clock period drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, voltage_domain = drive_sys.voltage_domain) # Create a CPU voltage domain drive_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, voltage_domain = drive_sys.cpu_voltage_domain) drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, cpu_id=0) drive_sys.cpu.createThreads() drive_sys.cpu.createInterruptController() drive_sys.cpu.connectAllPorts(drive_sys.membus) if options.kernel is not None: drive_sys.workload.object_file = binary(options.kernel) if ObjectList.is_kvm_cpu(DriveCPUClass): drive_sys.kvm_vm = KvmVM() drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges) drive_sys.iobridge.slave = drive_sys.iobus.master drive_sys.iobridge.master = drive_sys.membus.slave # Create the appropriate memory controllers and connect them to the # memory bus drive_sys.mem_ctrls = [DriveMemClass(range = r) for r in drive_sys.mem_ranges] for i in range(len(drive_sys.mem_ctrls)): drive_sys.mem_ctrls[i].port = drive_sys.membus.master drive_sys.init_param = options.init_param return drive_sys
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "riscv": test_sys = makeBareMetalRiscvSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], args.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, args.machine_type, np, bm[0], args.dtb_filename, bare_metal=args.bare_metal, cmdline=cmdline, external_memory=args.external_memory_system, ruby=args.ruby, vio_9p=args.vio_9p, bootloader=args.bootloader, ) if args.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = args.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=args.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=args.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=args.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if buildEnv['TARGET_ISA'] == 'riscv': test_sys.workload.bootloader = args.kernel elif args.kernel is not None: test_sys.workload.object_file = binary(args.kernel) if args.script is not None: test_sys.readfile = args.script test_sys.init_param = args.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np) ] if args.ruby: bootmem = getattr(test_sys, '_bootmem', None) Ruby.create_system(args, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=args.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.mem_side_ports = test_sys.ruby._io_port.in_ports for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() test_sys.ruby._cpu_ports[i].connectCpuPorts(cpu) else: if args.caches or args.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.mem_side_ports test_sys.iocache.mem_side = test_sys.membus.cpu_side_ports elif not args.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.cpu_side_port = test_sys.iobus.mem_side_ports test_sys.iobridge.mem_side_port = test_sys.membus.cpu_side_ports # Sanity check if args.simpoint_profile: if not ObjectList.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in range(np): if args.simpoint_profile: test_sys.cpu[i].addSimPointProbe(args.simpoint_interval) if args.checker: test_sys.cpu[i].addCheckerCpu() if not ObjectList.is_kvm_cpu(TestCPUClass): if args.bp_type: bpClass = ObjectList.bp_list.get(args.bp_type) test_sys.cpu[i].branchPred = bpClass() if args.indirect_bp_type: IndirectBPClass = ObjectList.indirect_bp_list.get( args.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if args.elastic_trace_en and args.checkpoint_restore == None and \ not args.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, args) CacheConfig.config_cache(args, test_sys) MemConfig.config_mem(args, test_sys) if ObjectList.is_kvm_cpu(TestCPUClass) or \ ObjectList.is_kvm_cpu(FutureClass): # Assign KVM CPUs to their own event queues / threads. This # has to be done after creating caches and other child objects # since these mustn't inherit the CPU event queue. for i, cpu in enumerate(test_sys.cpu): # Child objects usually inherit the parent's event # queue. Override that and use the same event queue for # all devices. for obj in cpu.descendants(): obj.eventq_index = 0 cpu.eventq_index = i + 1 test_sys.kvm_vm = KvmVM() return test_sys
drive_sys = build_drive_system(np) root = makeDualRoot(True, test_sys, drive_sys, args.etherdump) elif len(bm) == 1 and args.dist: # This system is part of a dist-gem5 simulation root = makeDistRoot(test_sys, args.dist_rank, args.dist_size, args.dist_server_name, args.dist_server_port, args.dist_sync_repeat, args.dist_sync_start, args.ethernet_linkspeed, args.ethernet_linkdelay, args.etherdump) elif len(bm) == 1: root = Root(full_system=True, system=test_sys) else: print("Error I don't know how to create more than 2 systems.") sys.exit(1) if ObjectList.is_kvm_cpu(TestCPUClass) or \ ObjectList.is_kvm_cpu(FutureClass): # Required for running kvm on multiple host cores. # Uses gem5's parallel event queue feature # Note: The simulator is quite picky about this number! root.sim_quantum = int(1e9) # 1 ms if args.timesync: root.time_sync_enable = True if args.frame_capture: VncServer.frame_capture = True if buildEnv['TARGET_ISA'] == "arm" and not args.bare_metal \ and not args.dtb_filename: if args.machine_type not in [
system.iobridge.cpu_side_port = system.iobus.mem_side_ports system.iobridge.mem_side_port = system.membus.cpu_side_ports # Sanity check if args.simpoint_profile: if not ObjectList.is_noncaching_cpu(CPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal("SimPoint generation not supported with more than one CPUs") for i in range(np): if args.simpoint_profile: system.cpu[i].addSimPointProbe(args.simpoint_interval) if args.checker: system.cpu[i].addCheckerCpu() if not ObjectList.is_kvm_cpu(CPUClass): if args.bp_type: bpClass = ObjectList.bp_list.get(args.bp_type) system.cpu[i].branchPred = bpClass() if args.indirect_bp_type: IndirectBPClass = ObjectList.indirect_bp_list.get( args.indirect_bp_type) system.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() system.cpu[i].createThreads() # ----------------------------- PMA Checker ---------------------------- # uncacheable_range = [ *system.platform._on_chip_ranges(), *system.platform._off_chip_ranges() ]
def build_test_system(np): cmdline = cmd_line_template() if buildEnv['TARGET_ISA'] == "alpha": test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "mips": test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "sparc": test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "x86": test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby, cmdline=cmdline) elif buildEnv['TARGET_ISA'] == "arm": test_sys = makeArmSystem( test_mem_mode, options.machine_type, np, bm[0], options.dtb_filename, bare_metal=options.bare_metal, cmdline=cmdline, external_memory=options.external_memory_system, ruby=options.ruby, security=options.enable_security_extensions, vio_9p=options.vio_9p, ) if options.enable_context_switch_stats_dump: test_sys.enable_context_switch_stats_dump = True else: fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) # Set the cache line size for the entire system test_sys.cache_line_size = options.cacheline_size # Create a top-level voltage domain test_sys.voltage_domain = VoltageDomain(voltage=options.sys_voltage) # Create a source clock for the system and set the clock period test_sys.clk_domain = SrcClockDomain( clock=options.sys_clock, voltage_domain=test_sys.voltage_domain) # Create a CPU voltage domain test_sys.cpu_voltage_domain = VoltageDomain() # Create a source clock for the CPUs and set the clock period test_sys.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=test_sys.cpu_voltage_domain) if options.kernel is not None: test_sys.kernel = binary(options.kernel) if options.script is not None: test_sys.readfile = options.script if options.lpae: test_sys.have_lpae = True if options.virtualisation: test_sys.have_virtualization = True test_sys.init_param = options.init_param # For now, assign all the CPUs to the same clock domain test_sys.cpu = [ TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) for i in range(np) ] if ObjectList.is_kvm_cpu(TestCPUClass) or \ ObjectList.is_kvm_cpu(FutureClass): test_sys.kvm_vm = KvmVM() if options.ruby: bootmem = getattr(test_sys, '_bootmem', None) Ruby.create_system(options, True, test_sys, test_sys.iobus, test_sys._dma_ports, bootmem) # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain( clock=options.ruby_clock, voltage_domain=test_sys.voltage_domain) # Connect the ruby io port to the PIO bus, # assuming that there is just one such port. test_sys.iobus.master = test_sys.ruby._io_port.slave for (i, cpu) in enumerate(test_sys.cpu): # # Tie the cpu ports to the correct ruby system ports # cpu.clk_domain = test_sys.cpu_clk_domain cpu.createThreads() cpu.createInterruptController() cpu.icache_port = test_sys.ruby._cpu_ports[i].slave cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in ("x86", "arm"): cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave if buildEnv['TARGET_ISA'] in "x86": cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[ i].slave cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[ i].master else: if options.caches or options.l2cache: # By default the IOCache runs at the system clock test_sys.iocache = IOCache(addr_ranges=test_sys.mem_ranges) test_sys.iocache.cpu_side = test_sys.iobus.master test_sys.iocache.mem_side = test_sys.membus.slave elif not options.external_memory_system: test_sys.iobridge = Bridge(delay='50ns', ranges=test_sys.mem_ranges) test_sys.iobridge.slave = test_sys.iobus.master test_sys.iobridge.master = test_sys.membus.slave # Sanity check if options.simpoint_profile: if not ObjectList.is_noncaching_cpu(TestCPUClass): fatal("SimPoint generation should be done with atomic cpu") if np > 1: fatal( "SimPoint generation not supported with more than one CPUs" ) for i in range(np): if options.simpoint_profile: test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) if options.checker: test_sys.cpu[i].addCheckerCpu() if not ObjectList.is_kvm_cpu(TestCPUClass): if options.bp_type: bpClass = ObjectList.bp_list.get(options.bp_type) test_sys.cpu[i].branchPred = bpClass() if options.indirect_bp_type: IndirectBPClass = ObjectList.indirect_bp_list.get( options.indirect_bp_type) test_sys.cpu[i].branchPred.indirectBranchPred = \ IndirectBPClass() test_sys.cpu[i].createThreads() # If elastic tracing is enabled when not restoring from checkpoint and # when not fast forwarding using the atomic cpu, then check that the # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check # passes then attach the elastic trace probe. # If restoring from checkpoint or fast forwarding, the code that does this for # FutureCPUClass is in the Simulation module. If the check passes then the # elastic trace probe is attached to the switch CPUs. if options.elastic_trace_en and options.checkpoint_restore == None and \ not options.fast_forward: CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) CacheConfig.config_cache(options, test_sys) MemConfig.config_mem(options, test_sys) return test_sys
# Create a separate clock domain for the CPUs system.cpu_clk_domain = SrcClockDomain( clock=options.cpu_clock, voltage_domain=system.cpu_voltage_domain) # If elastic tracing is enabled, then configure the cpu and attach the elastic # trace probe if options.elastic_trace_en: CpuConfig.config_etrace(CPUClass, system.cpu, options) # All cpus belong to a common cpu_clk_domain, therefore running at a common # frequency. for cpu in system.cpu: cpu.clk_domain = system.cpu_clk_domain if ObjectList.is_kvm_cpu(CPUClass) or ObjectList.is_kvm_cpu(FutureClass): if buildEnv['TARGET_ISA'] == 'x86': system.kvm_vm = KvmVM() for process in multiprocesses: process.useArchPT = True process.kvmInSE = True else: fatal("KvmCPU can only be used in SE mode with x86") # Sanity check if options.simpoint_profile: if not ObjectList.is_noncaching_cpu(CPUClass): fatal("SimPoint/BPProbe should be done with an atomic cpu") if np > 1: fatal("SimPoint generation not supported with more than one CPUs")