def gen_constraints(self):
cons = []
# Pin Constraints
cons.append(PortConstraint('DAC_DATA_OUT', 'DAC_DATA_OUT', port_index=list(range(self.bits)), iogroup_index=list(range(self.bits))))
cons.append(PortConstraint('DAC_IQWRT', 'DAC_IQWRT'))
cons.append(PortConstraint('DAC_IQSEL', 'DAC_IQSEL'))
cons.append(PortConstraint('DAC_IQCLK', 'DAC_IQCLK'))
cons.append(PortConstraint('DAC_IQRESET', 'DAC_IQRESET'))
#To do: add timing constraints
#Clock Group Constraints
cons.append(ClockGroupConstraint('-of_objects [get_pins red_pitaya_infr_inst/dsp_clk_mmcm_inst/CLKOUT0]', '-of_objects [get_pins red_pitaya_infr_inst/adc_clk_mmcm_inst/CLKOUT1]', 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins red_pitaya_infr_inst/adc_clk_mmcm_inst/CLKOUT1]', '-of_objects [get_pins red_pitaya_infr_inst/dsp_clk_mmcm_inst/CLKOUT0]', 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', 'aux_clk_diff_p', 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', 'sync_in_p', 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
#input constraints
# Output Constraints (setting to false path, so initial value made large)
#cons.append(OutputDelayConstraint('adc_clk_125_mmcm', consttype='min', constdelay_ns=0, add_delay_en=True, portname='DAC_DATA_OUT[*]'))
#cons.append(OutputDelayConstraint('adc_clk_125_mmcm', consttype='max', constdelay_ns=100, add_delay_en=True, portname='DAC_DATA_OUT[*]'))
#cons.append(OutputDelayConstraint('dac_clk_250_mmcm', consttype='min', constdelay_ns=0, add_delay_en=True, portname='DAC_IQWRT'))
#cons.append(OutputDelayConstraint('dac_clk_250_mmcm', consttype='max', constdelay_ns=100, add_delay_en=True, portname='DAC_IQWRT'))
#cons.append(OutputDelayConstraint('dac_clk_250_315_mmcm', consttype='min', constdelay_ns=0, add_delay_en=True, portname='DAC_IQCLK'))
#cons.append(OutputDelayConstraint('dac_clk_250_315_mmcm', consttype='max', constdelay_ns=100, add_delay_en=True, portname='DAC_IQCLK'))
#cons.append(OutputDelayConstraint('adc_clk_125_mmcm', consttype='min', constdelay_ns=0, add_delay_en=True, portname='DAC_IQRESET'))
#cons.append(OutputDelayConstraint('adc_clk_125_mmcm', consttype='max', constdelay_ns=100, add_delay_en=True, portname='DAC_IQRESET'))
#cons.append(OutputDelayConstraint('adc_clk_125_mmcm', consttype='min', constdelay_ns=0, add_delay_en=True, portname='DAC_IQSEL'))
#cons.append(OutputDelayConstraint('adc_clk_125_mmcm', consttype='max', constdelay_ns=100, add_delay_en=True, portname='DAC_IQSEL'))
#False Path Constraints
cons.append(FalsePathConstraint(destpath='[get_ports {DAC_DATA_OUT[*]}]'))
cons.append(FalsePathConstraint(destpath='[get_ports {DAC_IQWRT}]'))
cons.append(FalsePathConstraint(destpath='[get_ports {DAC_IQCLK}]'))
cons.append(FalsePathConstraint(destpath='[get_ports {DAC_IQRESET}]'))
cons.append(FalsePathConstraint(destpath='[get_ports {DAC_IQSEL}]'))
#Raw Constraints
return cons
def gen_constraints(self):
cons = []
cons.append(PortConstraint('clk_100_p', 'clk_100_p'))
cons.append(
ClockConstraint('clk_100_p',
'clk_100_p',
period=10.0,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=5.0))
cons.append(
ClockGroupConstraint('clk_pl_0', 'clk_100_p', 'asynchronous'))
cons.append(
ClockGroupConstraint('clk_100_p', 'clk_pl_0', 'asynchronous'))
return cons
def gen_constraints(self):
cons = []
# leaving the aux constraints here so that we can support them at a later stage.
#cons.append(PortConstraint('AUX_CLK_N','AUX_CLK_N'))
#cons.append(PortConstraint('AUX_CLK_P','AUX_CLK_P'))
#cons.append(PortConstraint('AUX_SYNCO_P','AUX_SYNCO_P'))
#cons.append(PortConstraint('AUX_SYNCI_P','AUX_SYNCI_P'))
#cons.append(PortConstraint('AUX_SYNCO_N','AUX_SYNCO_N'))
#cons.append(PortConstraint('AUX_SYNCI_N', 'AUX_SYNCI_N'))
#Need to extract the period and half period for creating the clock
#Port constraints
cons.append(
PortConstraint('MEZ3_' + self.mez3_phy + '_LANE_TX_P',
'MEZ3_' + self.mez3_phy + '_LANE_TX_P',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
ClockConstraint('MEZ3_REFCLK_%s_P' % self.port,
'MEZ3_REFCLK_%s_P' % self.port,
period=6.4,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=3.2))
cons.append(
RawConstraint('create_pblock MEZ3_' + self.mez3_phy + '_QSFP'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins skarab_infr/USER_CLK_MMCM_inst/CLKOUT0]',
'MEZ3_REFCLK_%s_P' % self.port, 'asynchronous'))
cons.append(
InputDelayConstraint(clkname='MEZ3_REFCLK_%s_P' % self.port,
consttype='max',
constdelay_ns=2.0,
add_delay_en=True,
portname='FPGA_RESET_N'))
cons.append(
MultiCycleConstraint(multicycletype='hold',
sourcepath='get_ports FPGA_RESET_N',
destpath='get_clocks MEZ3_REFCLK_%s_P' %
self.port,
multicycledelay=4))
return cons
def gen_constraints(self):
cons = []
cons.append(PortConstraint('FIXED_IO_ddr_vrp', 'FIXED_IO_ddr_vrp'))
cons.append(PortConstraint('FIXED_IO_ddr_vrn', 'FIXED_IO_ddr_vrn'))
cons.append(PortConstraint('DDR_we_n', 'DDR_we_n'))
cons.append(PortConstraint('DDR_RAS_n', 'DDR_RAS_n'))
cons.append(PortConstraint('DDR_ODT', 'DDR_ODT'))
cons.append(PortConstraint('DDR_reset_n', 'DDR_reset_n'))
cons.append(
PortConstraint('DDR_DQS_p',
'DDR_DQS_p',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('DDR_DQS_n',
'DDR_DQS_n',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('DDR_DQ',
'DDR_DQ',
port_index=list(range(32)),
iogroup_index=list(range(32))))
cons.append(
PortConstraint('DDR_DM',
'DDR_DM',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(PortConstraint('DDR_CS_n', 'DDR_CS_n'))
cons.append(PortConstraint('DDR_CKE', 'DDR_CKE'))
cons.append(PortConstraint('DDR_Ck_p', 'DDR_Ck_p'))
cons.append(PortConstraint('DDR_Ck_n', 'DDR_Ck_n'))
cons.append(PortConstraint('DDR_CAS_n', 'DDR_CAS_n'))
cons.append(
PortConstraint('DDR_ba',
'DDR_ba',
port_index=list(range(3)),
iogroup_index=list(range(3))))
cons.append(
PortConstraint('DDR_Addr',
'DDR_Addr',
port_index=list(range(15)),
iogroup_index=list(range(15))))
cons.append(PortConstraint('FIXED_IO_ps_porb', 'FIXED_IO_ps_porb'))
cons.append(PortConstraint('FIXED_IO_ps_srstb', 'FIXED_IO_ps_srstb'))
cons.append(PortConstraint('FIXED_IO_ps_clk', 'FIXED_IO_ps_clk'))
cons.append(PortConstraint('ADC_CLK_IN_P', 'ADC_CLK_IN_P'))
cons.append(
ClockConstraint('ADC_CLK_IN_P',
'ADC_CLK_IN_P',
period=8.0,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=4.0))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins red_pitaya_infr_inst/dsp_clk_mmcm_inst/CLKOUT0]',
'-of_objects [get_pins red_pitaya_inst/processing_system7_0/inst/PS7_i/FCLKCLK[0]]',
'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins red_pitaya_inst/processing_system7_0/inst/PS7_i/FCLKCLK[0]]',
'-of_objects [get_pins red_pitaya_infr_inst/dsp_clk_mmcm_inst/CLKOUT0]',
'asynchronous'))
return cons
def gen_constraints(self):
cons = []
# Pin Constraints
cons.append(
PortConstraint('MEZ%s_REFCLK_0_P' % self.mez,
'MEZ%s_REFCLK_0_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_0_N' % self.mez,
'MEZ%s_REFCLK_0_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_1_P' % self.mez,
'MEZ%s_REFCLK_1_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_1_N' % self.mez,
'MEZ%s_REFCLK_1_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_2_P' % self.mez,
'MEZ%s_REFCLK_2_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_2_N' % self.mez,
'MEZ%s_REFCLK_2_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_3_P' % self.mez,
'MEZ%s_REFCLK_3_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_3_N' % self.mez,
'MEZ%s_REFCLK_3_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_PHY11_LANE_RX_P' % self.mez,
'MEZ%s_PHY11_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY11_LANE_RX_N' % self.mez,
'MEZ%s_PHY11_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY12_LANE_RX_P' % self.mez,
'MEZ%s_PHY12_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY12_LANE_RX_N' % self.mez,
'MEZ%s_PHY12_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY21_LANE_RX_P' % self.mez,
'MEZ%s_PHY21_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY21_LANE_RX_N' % self.mez,
'MEZ%s_PHY21_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY22_LANE_RX_P' % self.mez,
'MEZ%s_PHY22_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY22_LANE_RX_N' % self.mez,
'MEZ%s_PHY22_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZZANINE_%s_RESET' % self.mez,
'MEZZANINE_%s_RESET' % self.mez))
cons.append(
PortConstraint('MEZZANINE_%s_CLK_SEL' % self.mez,
'MEZZANINE_%s_CLK_SEL' % self.mez))
cons.append(PortConstraint(
'aux_clk_diff_p',
'aux_clk_diff_p')) #AUX_CLK_P : in std_logic; AU20
cons.append(PortConstraint(
'aux_clk_diff_n',
'aux_clk_diff_n')) #AUX_CLK_N : in std_logic; AV19
cons.append(PortConstraint(
'sync_in_p', 'sync_in_p')) #AUX_SYNCI_P : in std_logic; AT21
cons.append(PortConstraint(
'sync_in_n', 'sync_in_n')) #AUX_SYNCI_N : in std_logic; AU21
cons.append(PortConstraint(
'sync_out_p', 'sync_out_p')) #AUX_SYNCO_P : out std_logic; AW21
cons.append(PortConstraint(
'sync_out_n', 'sync_out_n')) #AUX_SYNCO_N : out std_logic); AY21
# Output Constraints
#set_output_delay -clock [get_clocks FPGA_REFCLK_BUF0_P] -min -add_delay -3.000 [get_ports AUX_SYNCO_P]
#set_output_delay -clock [get_clocks FPGA_REFCLK_BUF0_P] -max -add_delay -3.000 [get_ports AUX_SYNCO_P]
cons.append(
OutputDelayConstraint(
clkname='-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
consttype='min',
constdelay_ns=-3.0,
add_delay_en=True,
portname='sync_out_p'))
cons.append(
OutputDelayConstraint(
clkname='-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
consttype='max',
constdelay_ns=-3.0,
add_delay_en=True,
portname='sync_out_p'))
cons.append(
MultiCycleConstraint(
multicycletype='setup',
sourcepath=
'get_clocks -of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
destpath='get_ports sync_out_p',
multicycledelay=4))
cons.append(
MultiCycleConstraint(
multicycletype='hold',
sourcepath=
'get_clocks -of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
destpath='get_ports sync_out_p',
multicycledelay=3))
#Clock Constraints
#create_clock -period 100.000 -name AUX_CLK_P -waveform {0.000 50.000} [get_ports AUX_CLK_P]
#create_clock -period 100.000 -name AUX_SYNCI_P -waveform {0.000 50.000} [get_ports AUX_SYNCI_P]
#create_clock -period 3.57 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#create_clock -period 3.57 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#create_clock -period 3.57 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#create_clock -period 3.57 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#create_clock -period 5.714 -waveform {0.000 2.857} [get_ports ADC_MEZ_REFCLK_0_P]
#create_clock -period 5.714 -waveform {0.000 2.857} [get_ports ADC_MEZ_REFCLK_1_P]
#create_clock -period 5.714 -waveform {0.000 2.857} [get_ports ADC_MEZ_REFCLK_2_P]
#create_clock -period 5.714 -waveform {0.000 2.857} [get_ports ADC_MEZ_REFCLK_3_P]
cons.append(
ClockConstraint('aux_clk_diff_p',
'aux_clk_diff_p',
period=100.0,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=50.0))
cons.append(
ClockConstraint('sync_in_p',
'sync_in_p',
period=100.0,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=50.0))
cons.append(
ClockConstraint(
'%s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=3.57,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=1.785))
cons.append(
ClockConstraint(
'%s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=3.57,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=1.785))
cons.append(
ClockConstraint(
'%s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=3.57,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=1.785))
cons.append(
ClockConstraint(
'%s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=3.57,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=1.785))
cons.append(
ClockConstraint('MEZ%s_REFCLK_0_P' % self.mez,
'MEZ%s_REFCLK_0_P' % self.mez,
period=5.714,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.857))
cons.append(
ClockConstraint('MEZ%s_REFCLK_1_P' % self.mez,
'MEZ%s_REFCLK_1_P' % self.mez,
period=5.714,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.857))
cons.append(
ClockConstraint('MEZ%s_REFCLK_2_P' % self.mez,
'MEZ%s_REFCLK_2_P' % self.mez,
period=5.714,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.857))
cons.append(
ClockConstraint('MEZ%s_REFCLK_3_P' % self.mez,
'MEZ%s_REFCLK_3_P' % self.mez,
period=5.714,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.857))
#Clock Group Constraints
#set_clock_groups -asynchronous -group [get_clocks AUX_CLK_P] -group [get_clocks FPGA_REFCLK_BUF0_P]
#set_clock_groups -asynchronous -group [get_clocks AUX_SYNCI_P] -group [get_clocks FPGA_REFCLK_BUF0_P]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'aux_clk_diff_p', 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'sync_in_p', 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
#False Path Constraints
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_0/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_0/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_1/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_1/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_2/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_2/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_3/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_3/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -from [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]] -to [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_false_path -from [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]] -to [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_false_path -from [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]] -to [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_false_path -from [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]] -to [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]
#set_false_path -from [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK] -to [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]
#set_false_path -from [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK] -to [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]
#set_false_path -from [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK] -to [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]
#set_false_path -from [get_clocks test_skarab_adc_byp_skarab_adc4x3g14_byp/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK] -to [get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_0/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_0/reset_RX_SYNC_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_1/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_1/reset_RX_SYNC_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_2/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_2/reset_RX_SYNC_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_3/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_11G2_RX_3/reset_RX_SYNC_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]',
destpath=
'[get_clocks %s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]',
destpath=
'[get_clocks %s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]',
destpath=
'[get_clocks %s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]',
destpath=
'[get_clocks %s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks %s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname,
destpath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]'
))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks %s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname,
destpath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]'
))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks %s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname,
destpath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]'
))
cons.append(
FalsePathConstraint(
sourcepath=
'[get_clocks %s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]'
% self.fullname,
destpath=
'[get_clocks -of_objects [get_pins test_skarab_adc_byp_Subsystem_fgbe/SYS_CLK_MMCM_inst/CLKOUT0]]'
))
#Raw Constraints
#create_pblock ADC32RF45_11G2_RX_0
#add_cells_to_pblock [get_pblocks ADC32RF45_11G2_RX_0] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]
#resize_pblock [get_pblocks ADC32RF45_11G2_RX_0] -add {CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}
#create_pblock ADC32RF45_11G2_RX_1
#add_cells_to_pblock [get_pblocks ADC32RF45_11G2_RX_1] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]
#resize_pblock [get_pblocks ADC32RF45_11G2_RX_1] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#create_pblock ADC32RF45_11G2_RX_2
#add_cells_to_pblock [get_pblocks ADC32RF45_11G2_RX_2] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]
#resize_pblock [get_pblocks ADC32RF45_11G2_RX_2] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
#create_pblock ADC32RF45_11G2_RX_3
#add_cells_to_pblock [get_pblocks ADC32RF45_11G2_RX_3] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]
#resize_pblock [get_pblocks ADC32RF45_11G2_RX_3] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_0' %
self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' %
self.mez + ' -add {CLOCKREGION_X0Y4:CLOCKREGION_X0Y4}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' %
self.mez + ' -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' %
self.mez + ' -add {CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' %
self.mez + ' -add {CLOCKREGION_X1Y7:CLOCKREGION_X1Y7}'))
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_1' %
self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' %
self.mez + ' -add {CLOCKREGION_X0Y5:CLOCKREGION_X0Y5}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' %
self.mez + ' -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' %
self.mez + ' -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' %
self.mez + ' -add {CLOCKREGION_X1Y6:CLOCKREGION_X1Y6}'))
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_2' %
self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' %
self.mez + ' -add {CLOCKREGION_X0Y6:CLOCKREGION_X0Y6}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' %
self.mez + ' -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' %
self.mez + ' -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' %
self.mez + ' -add {CLOCKREGION_X1Y5:CLOCKREGION_X1Y5}'))
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_3' %
self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' %
self.mez + ' -add {CLOCKREGION_X0Y7:CLOCKREGION_X0Y7}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' %
self.mez + ' -add {CLOCKREGION_X0Y3:CLOCKREGION_X0Y3}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' %
self.mez + ' -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' %
self.mez + ' -add {CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}'))
return cons
def gen_constraints(self):
cons = []
# -------------------------------------
# PATHS
# -------------------------------------
# RXOUTCLK: ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK
# BUF: ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i
# -------------------------------------
# PIN CONSTRAINTS
# -------------------------------------
cons.append(PortConstraint('MEZ%s_REFCLK_0_P' % self.mez, 'MEZ%s_REFCLK_0_P' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_0_N' % self.mez, 'MEZ%s_REFCLK_0_N' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_1_P' % self.mez, 'MEZ%s_REFCLK_1_P' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_1_N' % self.mez, 'MEZ%s_REFCLK_1_N' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_2_P' % self.mez, 'MEZ%s_REFCLK_2_P' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_2_N' % self.mez, 'MEZ%s_REFCLK_2_N' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_3_P' % self.mez, 'MEZ%s_REFCLK_3_P' % self.mez))
cons.append(PortConstraint('MEZ%s_REFCLK_3_N' % self.mez, 'MEZ%s_REFCLK_3_N' % self.mez))
cons.append(PortConstraint('MEZ%s_PHY11_LANE_RX_P' % self.mez, 'MEZ%s_PHY11_LANE_RX_P' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY11_LANE_RX_N' % self.mez, 'MEZ%s_PHY11_LANE_RX_N' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY12_LANE_RX_P' % self.mez, 'MEZ%s_PHY12_LANE_RX_P' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY12_LANE_RX_N' % self.mez, 'MEZ%s_PHY12_LANE_RX_N' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY21_LANE_RX_P' % self.mez, 'MEZ%s_PHY21_LANE_RX_P' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY21_LANE_RX_N' % self.mez, 'MEZ%s_PHY21_LANE_RX_N' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY22_LANE_RX_P' % self.mez, 'MEZ%s_PHY22_LANE_RX_P' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZ%s_PHY22_LANE_RX_N' % self.mez, 'MEZ%s_PHY22_LANE_RX_N' % self.mez, port_index=list(range(4)), iogroup_index=list(range(4))))
cons.append(PortConstraint('MEZZANINE_%s_RESET' % self.mez, 'MEZZANINE_%s_RESET' % self.mez))
cons.append(PortConstraint('MEZZANINE_%s_CLK_SEL' % self.mez, 'MEZZANINE_%s_CLK_SEL' % self.mez))
cons.append(PortConstraint('aux_clk_diff_p','aux_clk_diff_p')) #AUX_CLK_P : in std_logic; AU20
cons.append(PortConstraint('aux_clk_diff_n','aux_clk_diff_n')) #AUX_CLK_N : in std_logic; AV19
cons.append(PortConstraint('sync_in_p','sync_in_p')) #AUX_SYNCI_P : in std_logic; AT21
cons.append(PortConstraint('sync_in_n','sync_in_n')) #AUX_SYNCI_N : in std_logic; AU21
cons.append(PortConstraint('sync_out_p','sync_out_p')) #AUX_SYNCO_P : out std_logic; AW21
cons.append(PortConstraint('sync_out_n','sync_out_n')) #AUX_SYNCO_N : out std_logic); AY21
# -------------------------------------
# INPUT/OUTPUT DELAY CONSTRAINTS
# -------------------------------------
cons.append(InputDelayConstraint(clkname='-of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]', consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='sync_in_p'))
cons.append(InputDelayConstraint(clkname='-of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]', consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='sync_in_p'))
cons.append(InputDelayConstraint(clkname='-of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]', consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='aux_clk_diff_p'))
cons.append(InputDelayConstraint(clkname='-of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]', consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='aux_clk_diff_p'))
cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]', consttype='min', constdelay_ns=-3.0, add_delay_en=True, portname='sync_out_p'))
cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]', consttype='max', constdelay_ns=-3.0, add_delay_en=True, portname='sync_out_p'))
cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', consttype='min', constdelay_ns=0.1, add_delay_en=True, portname='MEZZANINE_%s_RESET' % self.mez))
cons.append(OutputDelayConstraint(clkname='-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', consttype='max', constdelay_ns=0.2, add_delay_en=True, portname='MEZZANINE_%s_RESET' % self.mez))
cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_clocks -of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', destpath='get_ports MEZZANINE_%s_RESET' % self.mez, multicycledelay=2))
cons.append(MultiCycleConstraint(multicycletype='hold', sourcepath='get_clocks -of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', destpath='get_ports MEZZANINE_%s_RESET' % self.mez, multicycledelay=1))
# -------------------------------------
# CLOCKS
# -------------------------------------
cons.append(ClockConstraint('%s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname,'%s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK' % self.fullname, period=3.571, port_en=False, virtual_en=False, waveform_min=0.0, waveform_max=1.785))
cons.append(ClockConstraint('%s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname,'%s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK' % self.fullname, period=3.571, port_en=False, virtual_en=False, waveform_min=0.0, waveform_max=1.785))
cons.append(ClockConstraint('%s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname,'%s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK' % self.fullname, period=3.571, port_en=False, virtual_en=False, waveform_min=0.0, waveform_max=1.785))
cons.append(ClockConstraint('%s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname,'%s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK' % self.fullname, period=3.571, port_en=False, virtual_en=False, waveform_min=0.0, waveform_max=1.785))
cons.append(ClockConstraint('MEZ%s_REFCLK_0_P' % self.mez,'MEZ%s_REFCLK_0_P' % self.mez, period=5.714, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=2.857))
cons.append(ClockConstraint('MEZ%s_REFCLK_1_P' % self.mez,'MEZ%s_REFCLK_1_P' % self.mez, period=5.714, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=2.857))
cons.append(ClockConstraint('MEZ%s_REFCLK_2_P' % self.mez,'MEZ%s_REFCLK_2_P' % self.mez, period=5.714, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=2.857))
cons.append(ClockConstraint('MEZ%s_REFCLK_3_P' % self.mez,'MEZ%s_REFCLK_3_P' % self.mez, period=5.714, port_en=True, virtual_en=False, waveform_min=0.0, waveform_max=2.857))
# -------------------------------------
# ASYNCHRONOUS CONSTRAINTS
# -------------------------------------
cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
cons.append(ClockGroupConstraint('-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]', '%s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK'% self.fullname, 'asynchronous'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]', destpath='[get_clocks %s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname))
cons.append(FalsePathConstraint(sourcepath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]', destpath='[get_clocks %s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname))
cons.append(FalsePathConstraint(sourcepath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]', destpath='[get_clocks %s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname))
cons.append(FalsePathConstraint(sourcepath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]', destpath='[get_clocks %s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT0]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT1]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT1]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT1]]'))
cons.append(FalsePathConstraint(sourcepath='[get_clocks %s/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/jesd204b_11200_rx_init_i/U0/jesd204b_11200_rx_i/gt0_jesd204b_11200_rx_i/gthe2_i/RXOUTCLK]' % self.fullname, destpath='[get_clocks -of_objects [get_pins */SYS_CLK_MMCM_inst/CLKOUT1]]'))
if self.sync_ms == "Master":
cons.append(RawConstraint('set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins %s/adc_pll_i/U0/mmcm_adv_inst/CLKOUT0]]' % self.fullname))
# -------------------------------------
# CDC WAIVER
# -------------------------------------
cons.append(RawConstraint('create_waiver -type CDC -id CDC-11 -from [get_pins skarab_infr/user_fpga_rst_reg/C] -to [get_pins %s/ADC32RF45_11G2_RX_0/tff_adcplllocked/reg_z_reg/D] -user Peralex -description {Confirmed CDC-11 can be ignored in this case}' % self.fullname))
cons.append(RawConstraint('create_waiver -type CDC -id CDC-11 -from [get_pins skarab_infr/user_fpga_rst_reg/C] -to [get_pins %s/ADC32RF45_11G2_RX_1/tff_adcplllocked/reg_z_reg/D] -user Peralex -description {Confirmed CDC-11 can be ignored in this case}' % self.fullname))
cons.append(RawConstraint('create_waiver -type CDC -id CDC-11 -from [get_pins skarab_infr/user_fpga_rst_reg/C] -to [get_pins %s/ADC32RF45_11G2_RX_2/tff_adcplllocked/reg_z_reg/D] -user Peralex -description {Confirmed CDC-11 can be ignored in this case}' % self.fullname))
cons.append(RawConstraint('create_waiver -type CDC -id CDC-11 -from [get_pins skarab_infr/user_fpga_rst_reg/C] -to [get_pins %s/ADC32RF45_11G2_RX_3/tff_adcplllocked/reg_z_reg/D] -user Peralex -description {Confirmed CDC-11 can be ignored in this case}' % self.fullname))
# -------------------------------------
# PBLOCKS
# -------------------------------------
cons.append(RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_0' % self.mez))
cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' % self.mez + ' [get_cells -quiet [list '+self.fullname+'/ADC32RF45_11G2_RX_0/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'))
if self.mez == 0:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' % self.mez + ' -add {CLOCKREGION_X0Y4:CLOCKREGION_X0Y4}'))
elif self.mez == 1:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' % self.mez + ' -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}'))
elif self.mez == 2:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' % self.mez + ' -add {CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}'))
elif self.mez == 3:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_0]' % self.mez + ' -add {CLOCKREGION_X1Y7:CLOCKREGION_X1Y7}'))
cons.append(RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_1' % self.mez))
cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' % self.mez + ' [get_cells -quiet [list '+self.fullname+'/ADC32RF45_11G2_RX_1/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'))
if self.mez == 0:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' % self.mez + ' -add {CLOCKREGION_X0Y5:CLOCKREGION_X0Y5}'))
elif self.mez == 1:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' % self.mez + ' -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}'))
elif self.mez == 2:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' % self.mez + ' -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}'))
elif self.mez == 3:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_1]' % self.mez + ' -add {CLOCKREGION_X1Y6:CLOCKREGION_X1Y6}'))
cons.append(RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_2' % self.mez))
cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' % self.mez + ' [get_cells -quiet [list '+self.fullname+'/ADC32RF45_11G2_RX_2/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'))
if self.mez == 0:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' % self.mez + ' -add {CLOCKREGION_X0Y6:CLOCKREGION_X0Y6}'))
elif self.mez == 1:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' % self.mez + ' -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2}'))
elif self.mez == 2:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' % self.mez + ' -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}'))
elif self.mez == 3:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_2]' % self.mez + ' -add {CLOCKREGION_X1Y5:CLOCKREGION_X1Y5}'))
cons.append(RawConstraint('create_pblock MEZ%s_ADC32RF45_11G2_RX_3' % self.mez))
cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' % self.mez + ' [get_cells -quiet [list '+self.fullname+'/ADC32RF45_11G2_RX_3/ADC32RF45_11G2_RX_PHY_i/jesd204b_11200_rx_support_i/gt_usrclk_source/rxoutclk_bufg0_i]]'))
if self.mez == 0:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' % self.mez + ' -add {CLOCKREGION_X0Y7:CLOCKREGION_X0Y7}'))
elif self.mez == 1:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' % self.mez + ' -add {CLOCKREGION_X0Y3:CLOCKREGION_X0Y3}'))
elif self.mez == 2:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' % self.mez + ' -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}'))
elif self.mez == 3:
cons.append(RawConstraint('resize_pblock [get_pblocks MEZ%s_ADC32RF45_11G2_RX_3]' % self.mez + ' -add {CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}'))
return cons
def gen_constraints(self):
cons = []
# leaving the aux constraints here so that we can support them at a later stage.
#cons.append(PortConstraint('AUX_CLK_N','AUX_CLK_N'))
#cons.append(PortConstraint('AUX_CLK_P','AUX_CLK_P'))
#cons.append(PortConstraint('AUX_SYNCO_P','AUX_SYNCO_P'))
#cons.append(PortConstraint('AUX_SYNCI_P','AUX_SYNCI_P'))
#cons.append(PortConstraint('AUX_SYNCO_N','AUX_SYNCO_N'))
#cons.append(PortConstraint('AUX_SYNCI_N', 'AUX_SYNCI_N'))
#Need to extract the period and half period for creating the clock
#Port constraints
cons.append(
PortConstraint('MEZ3_' + self.mez3_phy + '_LANE_TX_P',
'MEZ3_' + self.mez3_phy + '_LANE_TX_P',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ3_' + self.mez3_phy + '_LANE_TX_N',
'MEZ3_' + self.mez3_phy + '_LANE_TX_N',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ3_' + self.mez3_phy + '_LANE_RX_P',
'MEZ3_' + self.mez3_phy + '_LANE_RX_P',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ3_' + self.mez3_phy + '_LANE_RX_N',
'MEZ3_' + self.mez3_phy + '_LANE_RX_N',
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ3_REFCLK_%s_P' % self.port,
'MEZ3_REFCLK_%s_P' % self.port))
cons.append(
PortConstraint('MEZ3_REFCLK_%s_N' % self.port,
'MEZ3_REFCLK_%s_N' % self.port))
cons.append(
ClockConstraint('MEZ3_REFCLK_%s_P' % self.port,
'MEZ3_REFCLK_%s_P' % self.port,
period=6.4,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=3.2))
cons.append(
RawConstraint('create_pblock MEZ3_' + self.mez3_phy + '_QSFP'))
#cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ3_'+self.mez3_phy+'_QSFP] [get_cells -quiet [list '+self.fullname+'/IEEE802_3_XL_PHY_0/PHY_inst/RX_CLK_RCC]]'))
#cons.append(RawConstraint('add_cells_to_pblock [get_pblocks MEZ3_'+self.mez3_phy+'_QSFP] [get_cells -quiet [list '+self.fullname+'/IEEE802_3_XL_PHY_0/PHY_inst/TX_CLK_RCC]]'))
cons.append(
RawConstraint('add_cells_to_pblock [get_pblocks MEZ3_' +
self.mez3_phy + '_QSFP] [get_cells -quiet [list ' +
self.fullname + '/IEEE802_3_XL_PHY_0/PHY_inst]]'))
cons.append(
RawConstraint('resize_pblock [get_pblocks MEZ3_' + self.mez3_phy +
'_QSFP] -add {' + self.clock_region + '}'))
if (self.psize_extend):
cons.append(
RawConstraint('resize_pblock [get_pblocks MEZ3_' +
self.mez3_phy + '_QSFP] -add {' +
self.clock_region2 + '}'))
cons.append(
RawConstraint(
'set_property BEL MMCME2_ADV [get_cells [list ' +
self.fullname +
'/IEEE802_3_XL_lPHY_0/PHY_inst/RX_CLK_RCC/ref_clkB_MMCME2_BASE_inst]]'
))
cons.append(
RawConstraint(
'set_property LOC MMCME2_ADV_X1Y4 [get_cells [list ' +
self.fullname +
'/IEEE802_3_XL_PHY_0/PHY_inst/RX_CLK_RCC/ref_clkB_MMCME2_BASE_inst]]'
))
cons.append(
RawConstraint(
'set_property BEL PLLE2_ADV [get_cells [list ' +
self.fullname +
'/IEEE802_3_XL_PHY_0/PHY_inst/TX_CLK_RCC/PLLE2_BASE_inst]]'
))
cons.append(
RawConstraint(
'set_property LOC PLLE2_ADV_X1Y4 [get_cells [list ' +
self.fullname +
'/IEEE802_3_XL_PHY_0/PHY_inst/TX_CLK_RCC/PLLE2_BASE_inst]]'
))
cons.append(
RawConstraint(
'set_property BEL MMCME2_ADV [get_cells [list skarab_infr/SYS_CLK_MMCM_inst]]'
))
cons.append(
RawConstraint(
'set_property LOC MMCME2_ADV_X1Y3 [get_cells [list skarab_infr/SYS_CLK_MMCM_inst]]'
))
cons.append(
RawConstraint(
'set_property BEL MMCME2_ADV [get_cells [list skarab_infr/USER_CLK_MMCM_inst]]'
))
cons.append(
RawConstraint(
'set_property LOC MMCME2_ADV_X0Y4 [get_cells [list skarab_infr/USER_CLK_MMCM_inst]]'
))
cons.append(
RawConstraint(
'set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets skarab_infr/refclk_0]'
))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-include_generated_clocks FPGA_REFCLK_BUF1_P', 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins skarab_infr/SYS_CLK_MMCM_inst/CLKOUT0]',
'MEZ3_REFCLK_%s_P' % self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-of_objects [get_pins skarab_infr/gmii_to_sgmii_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0]', 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins %s/gmii_to_sgmii_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0]' %self.fullname, 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
cons.append(
ClockGroupConstraint('MEZ3_REFCLK_%s_P' % self.port,
'FPGA_EMCCLK2', 'asynchronous'))
cons.append(
ClockGroupConstraint('FPGA_EMCCLK2',
'MEZ3_REFCLK_%s_P' % self.port,
'asynchronous'))
cons.append(
ClockGroupConstraint(
'MEZ3_REFCLK_%s_P' % self.port,
'-of_objects [get_pins skarab_infr/SYS_CLK_MMCM_inst/CLKOUT0]',
'asynchronous'))
cons.append(
ClockGroupConstraint(
'MEZ3_REFCLK_%s_P' % self.port,
'-of_objects [get_pins skarab_infr/USER_CLK_MMCM_inst/CLKOUT0]',
'asynchronous'))
cons.append(
ClockGroupConstraint(
'MEZ3_REFCLK_%s_P' % self.port,
'-of_objects [get_pins skarab_infr/SYS_CLK_MMCM_inst/CLKOUT1]',
'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins skarab_infr/SYS_CLK_MMCM_inst/CLKOUT1]',
'MEZ3_REFCLK_%s_P' % self.port, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins skarab_infr/USER_CLK_MMCM_inst/CLKOUT0]',
'MEZ3_REFCLK_%s_P' % self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-of_objects [get_pins %s/gmii_to_sgmii_0/U0/core_clocking_i/mmcm_adv_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('VIRTUAL_clkout0', 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('virtual_clock', 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, 'FPGA_EMCCLK2', 'asynchronous'))
#cons.append(ClockGroupConstraint('FPGA_EMCCLK2', 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, 'virtual_clock', 'asynchronous'))
#cons.append(ClockGroupConstraint('VIRTUAL_I', 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, 'VIRTUAL_I','asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins %s/SYS_CLK_MMCM_inst/CLKOUT1]' % self.fullname, 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(ClockGroupConstraint('MEZ3_REFCLK_%s_P'%self.port, '-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'asynchronous'))
#cons.append(ClockGroupConstraint('-of_objects [get_pins %s/USER_CLK_MMCM_inst/CLKOUT0]' % self.fullname, 'MEZ3_REFCLK_%s_P'%self.port, 'asynchronous'))
#cons.append(InputDelayConstraint(clkname='MEZ3_REFCLK_%s_P'%self.port, consttype='min', constdelay_ns=1.0, add_delay_en=True, portname='FPGA_RESET_N'))
#cons.append(InputDelayConstraint(clkname='MEZ3_REFCLK_%s_P'%self.port, consttype='max', constdelay_ns=2.0, add_delay_en=True, portname='FPGA_RESET_N'))
#cons.append(MultiCycleConstraint(multicycletype='setup',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks MEZ3_REFCLK_%s_P'%self.port, multicycledelay=4))
#cons.append(MultiCycleConstraint(multicycletype='hold',sourcepath='get_ports FPGA_RESET_N', destpath='get_clocks MEZ3_REFCLK_%s_P'%self.port, multicycledelay=4))
return cons
def gen_constraints(self):
cons = []
# Pin Constraints
cons.append(
PortConstraint('MEZ%s_REFCLK_0_P' % self.mez,
'MEZ%s_REFCLK_0_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_0_N' % self.mez,
'MEZ%s_REFCLK_0_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_1_P' % self.mez,
'MEZ%s_REFCLK_1_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_1_N' % self.mez,
'MEZ%s_REFCLK_1_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_2_P' % self.mez,
'MEZ%s_REFCLK_2_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_2_N' % self.mez,
'MEZ%s_REFCLK_2_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_3_P' % self.mez,
'MEZ%s_REFCLK_3_P' % self.mez))
cons.append(
PortConstraint('MEZ%s_REFCLK_3_N' % self.mez,
'MEZ%s_REFCLK_3_N' % self.mez))
cons.append(
PortConstraint('MEZ%s_PHY11_LANE_RX_P' % self.mez,
'MEZ%s_PHY11_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY11_LANE_RX_N' % self.mez,
'MEZ%s_PHY11_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY12_LANE_RX_P' % self.mez,
'MEZ%s_PHY12_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY12_LANE_RX_N' % self.mez,
'MEZ%s_PHY12_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY21_LANE_RX_P' % self.mez,
'MEZ%s_PHY21_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY21_LANE_RX_N' % self.mez,
'MEZ%s_PHY21_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY22_LANE_RX_P' % self.mez,
'MEZ%s_PHY22_LANE_RX_P' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZ%s_PHY22_LANE_RX_N' % self.mez,
'MEZ%s_PHY22_LANE_RX_N' % self.mez,
port_index=list(range(4)),
iogroup_index=list(range(4))))
cons.append(
PortConstraint('MEZZANINE_%s_RESET' % self.mez,
'MEZZANINE_%s_RESET' % self.mez))
cons.append(
PortConstraint('MEZZANINE_%s_CLK_SEL' % self.mez,
'MEZZANINE_%s_CLK_SEL' % self.mez))
cons.append(PortConstraint(
'aux_clk_diff_p',
'aux_clk_diff_p')) #AUX_CLK_P : in std_logic; AU20
cons.append(PortConstraint(
'aux_clk_diff_n',
'aux_clk_diff_n')) #AUX_CLK_N : in std_logic; AV19
cons.append(PortConstraint(
'sync_in_p', 'sync_in_p')) #AUX_SYNCI_P : in std_logic; AT21
cons.append(PortConstraint(
'sync_in_n', 'sync_in_n')) #AUX_SYNCI_N : in std_logic; AU21
cons.append(PortConstraint(
'sync_out_p', 'sync_out_p')) #AUX_SYNCO_P : out std_logic; AW21
cons.append(PortConstraint(
'sync_out_n', 'sync_out_n')) #AUX_SYNCO_N : out std_logic); AY21
# Output Constraints
#set_output_delay -clock [get_clocks FPGA_REFCLK_BUF0_P] -min -add_delay -3.000 [get_ports AUX_SYNCO_P]
#set_output_delay -clock [get_clocks FPGA_REFCLK_BUF0_P] -max -add_delay -3.000 [get_ports AUX_SYNCO_P]
cons.append(
OutputDelayConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
consttype='min',
constdelay_ns=-3.0,
add_delay_en=True,
portname='sync_out_p'))
cons.append(
OutputDelayConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
consttype='max',
constdelay_ns=-3.0,
add_delay_en=True,
portname='sync_out_p'))
#Clock Constraints
#create_clock -period 100.000 -name AUX_CLK_P -waveform {0.000 50.000} [get_ports AUX_CLK_P]
#create_clock -period 100.000 -name AUX_SYNCI_P -waveform {0.000 50.000} [get_ports AUX_SYNCI_P]
#create_clock -period 5.333 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#create_clock -period 5.333 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#create_clock -period 5.333 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#create_clock -period 5.333 [get_pins SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#create_clock -period 5.333 -waveform {0.000 2.666} [get_ports ADC_MEZ_REFCLK_0_P]
#create_clock -period 5.333 -waveform {0.000 2.666} [get_ports ADC_MEZ_REFCLK_1_P]
#create_clock -period 5.333 -waveform {0.000 2.666} [get_ports ADC_MEZ_REFCLK_2_P]
#create_clock -period 5.333 -waveform {0.000 2.666} [get_ports ADC_MEZ_REFCLK_3_P]
cons.append(
ClockConstraint('aux_clk_diff_p',
'aux_clk_diff_p',
period=100.0,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=50.0))
cons.append(
ClockConstraint('sync_in_p',
'sync_in_p',
period=100.0,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=50.0))
cons.append(
ClockConstraint(
'%s/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=5.333,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint(
'%s/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=5.333,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint(
'%s/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=5.333,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint(
'%s/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
'%s/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname,
period=5.333,
port_en=False,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint('MEZ%s_REFCLK_0_P' % self.mez,
'MEZ%s_REFCLK_0_P' % self.mez,
period=5.333,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint('MEZ%s_REFCLK_1_P' % self.mez,
'MEZ%s_REFCLK_1_P' % self.mez,
period=5.333,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint('MEZ%s_REFCLK_2_P' % self.mez,
'MEZ%s_REFCLK_2_P' % self.mez,
period=5.333,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
cons.append(
ClockConstraint('MEZ%s_REFCLK_3_P' % self.mez,
'MEZ%s_REFCLK_3_P' % self.mez,
period=5.333,
port_en=True,
virtual_en=False,
waveform_min=0.0,
waveform_max=2.666))
#Clock Group Constraints
#set_clock_groups -asynchronous -group [get_clocks AUX_CLK_P] -group [get_clocks FPGA_REFCLK_BUF0_P]
#set_clock_groups -asynchronous -group [get_clocks AUX_SYNCI_P] -group [get_clocks FPGA_REFCLK_BUF0_P]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
#set_clock_groups -asynchronous -group [get_clocks FPGA_REFCLK_BUF0_P] -group [get_clocks SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK]
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'aux_clk_diff_p', 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'sync_in_p', 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
cons.append(
ClockGroupConstraint(
'-of_objects [get_pins */USER_CLK_MMCM_inst/CLKOUT0]',
'%s/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/JESD204B_4LaneRX_7500MHz_init_i/U0/JESD204B_4LaneRX_7500MHz_i/gt0_JESD204B_4LaneRX_7500MHz_i/gthe2_i/RXOUTCLK'
% self.fullname, 'asynchronous'))
#False Path Constraints
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_0/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_0/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_1/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_1/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_2/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_2/reset_RX_SYNC_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_3/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]
#set_false_path -to [get_pins {SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_3/reset_RX_SYNC_SR_reg[*]/PRE}]
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_0/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_0/reset_RX_SYNC_SR_reg[*]/PRE}]' %
self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_1/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_1/reset_RX_SYNC_SR_reg[*]/PRE}]' %
self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_2/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_2/reset_RX_SYNC_SR_reg[*]/PRE}]' %
self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_3/ADC_RX_PHY_soft_reset_SR_reg[*]/PRE}]'
% self.fullname))
cons.append(
FalsePathConstraint(
destpath=
'[get_pins {%s/ADC32RF45_RX_3/reset_RX_SYNC_SR_reg[*]/PRE}]' %
self.fullname))
#Raw Constraints
#create_pblock ADC32RF45_RX_0
#add_cells_to_pblock [get_pblocks ADC32RF45_RX_0] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]
#resize_pblock [get_pblocks ADC32RF45_RX_0] -add {CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}
#create_pblock ADC32RF45_RX_1
#add_cells_to_pblock [get_pblocks ADC32RF45_RX_1] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]
#resize_pblock [get_pblocks ADC32RF45_RX_1] -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}
#create_pblock ADC32RF45_RX_2
#add_cells_to_pblock [get_pblocks ADC32RF45_RX_2] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]
#resize_pblock [get_pblocks ADC32RF45_RX_2] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
#create_pblock ADC32RF45_RX_3
#add_cells_to_pblock [get_pblocks ADC32RF45_RX_3] [get_cells -quiet [list SKARAB_ADC4x3G_14_inst/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]
#resize_pblock [get_pblocks ADC32RF45_RX_3] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_RX_0' % self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_RX_0]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_RX_0/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_0]' %
self.mez + ' -add {CLOCKREGION_X0Y4:CLOCKREGION_X0Y4}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_0]' %
self.mez + ' -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_0]' %
self.mez + ' -add {CLOCKREGION_X1Y3:CLOCKREGION_X1Y3}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_0]' %
self.mez + ' -add {CLOCKREGION_X1Y7:CLOCKREGION_X1Y7}'))
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_RX_1' % self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_RX_1]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_RX_1/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_1]' %
self.mez + ' -add {CLOCKREGION_X0Y5:CLOCKREGION_X0Y5}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_1]' %
self.mez + ' -add {CLOCKREGION_X0Y1:CLOCKREGION_X0Y1}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_1]' %
self.mez + ' -add {CLOCKREGION_X1Y2:CLOCKREGION_X1Y2}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_1]' %
self.mez + ' -add {CLOCKREGION_X1Y6:CLOCKREGION_X1Y6}'))
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_RX_2' % self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_RX_2]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_RX_2/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_2]' %
self.mez + ' -add {CLOCKREGION_X0Y6:CLOCKREGION_X0Y6}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_2]' %
self.mez + ' -add {CLOCKREGION_X0Y2:CLOCKREGION_X0Y2}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_2]' %
self.mez + ' -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_2]' %
self.mez + ' -add {CLOCKREGION_X1Y5:CLOCKREGION_X1Y5}'))
cons.append(
RawConstraint('create_pblock MEZ%s_ADC32RF45_RX_3' % self.mez))
cons.append(
RawConstraint(
'add_cells_to_pblock [get_pblocks MEZ%s_ADC32RF45_RX_3]' %
self.mez + ' [get_cells -quiet [list ' + self.fullname +
'/ADC32RF45_RX_3/ADC_PHY_inst/ADC_GT_SUPPPORT_inst/GT0_RXOUTCLK_BUFH]]'
))
if self.mez == 0:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_3]' %
self.mez + ' -add {CLOCKREGION_X0Y7:CLOCKREGION_X0Y7}'))
elif self.mez == 1:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_3]' %
self.mez + ' -add {CLOCKREGION_X0Y3:CLOCKREGION_X0Y3}'))
elif self.mez == 2:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_3]' %
self.mez + ' -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0}'))
elif self.mez == 3:
cons.append(
RawConstraint(
'resize_pblock [get_pblocks MEZ%s_ADC32RF45_RX_3]' %
self.mez + ' -add {CLOCKREGION_X1Y4:CLOCKREGION_X1Y4}'))
return cons