def buildProjectSuccess(log_dir):
fpath = os.path.join(log_dir, PROJECT_BUILD_LOG)
if not strInFile(fpath, ["Project created"]):
dbg.print_error("Vivado Project was not created properly!")
dbg.print_error("Check: %s" % fpath)
return False
dbg.print_info("Project was build successfully!")
return True
def implFlowSuccess(log_dir, run_dir):
syn_dir = os.path.join(run_dir, "synth_1")
impl_dir = os.path.join(run_dir, "impl_1")
# check that implementation was started
fpath = os.path.join(log_dir, PROJECT_IMPL_LOG)
if not strInFile(fpath, ["Implementation launched for project"]):
dbg.print_error("Implementation wasn't launched properly!")
dbg.print_error("Check: %s" % fpath)
return False
# check synthesis results
fpath = os.path.join(syn_dir, "runme.log")
if not strInFile(fpath, ["synth_design completed successfully"]):
dbg.print_error("FPGA synthesis failed!")
dbg.print_error("Check: %s" % fpath)
return False
# check implementation results
fpath = os.path.join(impl_dir, "runme.log")
if not strInFile(fpath, ["Bitgen Completed Successfully"]):
dbg.print_error("FPGA implementation failed!")
dbg.print_error("Check: %s" % fpath)
return False
# check timing
fname = [f for f in os.listdir(impl_dir) if f.endswith("timing_summary_routed.rpt")][0]
fpath = os.path.join(impl_dir, fname)
if not strInFile(fpath, ["timing constraints are met"]):
dbg.print_error("Implemented design has timing violations!")
dbg.print_error("Check: %s" % fpath)
return False
dbg.print_info("Design was implemented successfully!")
return True