def test_IFB(cpu):
cpu.reg.a = 0x0001
cpu.ram.set(0x0000, compile_word(0x21, 0x00, 0xf)) # skip next instruction unless a & 1 != 0
cpu.step()
assert cpu.cycle == 2
assert cpu.reg.pc == 1
cpu.ram.set(0x0001, compile_word(0x22, 0x00, 0xf)) # skip next instruction unless a & 2 != 0
cpu.ram.set(0x0002, 0x7803) # sub A, [next_word]
cpu.ram.set(0x0003, 0x1000) # aforementioned next word
cpu.step()
assert cpu.cycle == 5
assert cpu.reg.pc == 4 # must skip BOTH words of next command
def test_XOR(cpu):
cpu.reg.a = 0x0003
cpu.ram.set(0x0000, compile_word(0x21, 0x00, 0xb)) # set reg a to 0b11 ^ 0b01
cpu.step()
assert cpu.reg.a == 0x0002
assert cpu.cycle == 1
assert cpu.reg.pc == 1
def test_BOR(cpu):
cpu.reg.a = 0x0002
cpu.ram.set(0x0000, compile_word(0x21, 0x00, 0xa)) # set reg a to 0b10 | 0b01
cpu.step()
assert cpu.reg.a == 0x0003
assert cpu.cycle == 1
assert cpu.reg.pc == 1
def test_AND(cpu):
cpu.reg.a = 0x0003
cpu.ram.set(0x0000, compile_word(0x21, 0x00, 0x9)) # set reg a to 0b11 & 0b01
cpu.step()
assert cpu.reg.a == 0x0001
assert cpu.cycle == 1
assert cpu.reg.pc == 1
def test_SET(cpu):
assert cpu.reg.b == 0x0000
cpu.ram.set(0x0000, compile_word(0x22, 0x01, 0x1)) # set reg b to literal 2
cpu.step()
assert cpu.reg.b == 0x0002
assert cpu.cycle == 1
assert cpu.reg.pc == 1
def test_SHL_o(cpu):
cpu.reg.a = 0xff00
cpu.ram.set(0x0000, compile_word(0x2c, 0x00, 0x8)) # set reg a to 0xff00 >> 12
cpu.step()
assert cpu.reg.a == 0x000f
assert cpu.cycle == 2
assert cpu.reg.pc == 1
assert cpu.reg.o == 0xf000
def test_SHR(cpu):
cpu.reg.a = 0xff00
cpu.ram.set(0x0000, compile_word(0x24, 0x00, 0x8)) # set reg a to 0xff00 >> 4
cpu.step()
assert cpu.reg.a == 0x0ff0
assert cpu.cycle == 2
assert cpu.reg.pc == 1
assert cpu.reg.o == 0x0000
def test_SHL_o(cpu):
cpu.reg.a = 0xffff
cpu.ram.set(0x0000, compile_word(0x22, 0x00, 0x7)) # set reg a to 0xffff << 2
cpu.step()
assert cpu.reg.a == 0xfffc
assert cpu.cycle == 2
assert cpu.reg.pc == 1
assert cpu.reg.o == 0x0003
def test_MOD_zero(cpu):
cpu.reg.b = 0x0009
cpu.ram.set(0x0000, compile_word(0x20, 0x01, 0x6)) # set reg b to 9 % literal 0
cpu.step()
assert cpu.reg.b == 0x0000
assert cpu.cycle == 3
assert cpu.reg.pc == 1
assert cpu.reg.o == 0x0000
def test_DIV_o(cpu):
cpu.reg.b = 0x0009
cpu.ram.set(0x0000, compile_word(0x22, 0x01, 0x5)) # set reg b to 9 // literal 2
cpu.step()
assert cpu.reg.b == 0x0004
assert cpu.cycle == 3
assert cpu.reg.pc == 1
assert cpu.reg.o == 0x8000
def test_MUL(cpu):
cpu.reg.b = 0x0004
cpu.ram.set(0x0000, compile_word(0x22, 0x01, 0x4)) # set reg b to literal 2 * 4
cpu.step()
assert cpu.reg.b == 0x0008
assert cpu.cycle == 2
assert cpu.reg.pc == 1
assert cpu.reg.o == 0
def test_SUB(cpu):
cpu.reg.b = 0x0005
cpu.ram.set(0x0000, compile_word(0x22, 0x01, 0x3)) # set reg b to 5 - literal 2
cpu.step()
assert cpu.reg.b == 0x0003
assert cpu.cycle == 2
assert cpu.reg.pc == 1
assert cpu.reg.o == 0
def test_SHL(cpu):
cpu.reg.a = 0x0009
cpu.ram.set(0x0000, compile_word(0x22, 0x00, 0x7)) # set reg a to 9 << 2
cpu.step()
assert cpu.reg.a == 0x0024
assert cpu.cycle == 2
assert cpu.reg.pc == 1
assert cpu.reg.o == 0x0000
def test_MUL_o(cpu):
cpu.reg.a = 0x02ff
cpu.reg.b = 0x00ff
cpu.ram.set(0x0000, compile_word(0x01, 0x00, 0x4)) # set reg a to a * b
cpu.step()
assert cpu.reg.a == 0xfc01
assert cpu.cycle == 2
assert cpu.reg.pc == 1
assert cpu.reg.o == 0x0002
def test_SUB_o(cpu):
cpu.reg.a = 0x1000
cpu.reg.b = 0xf000
cpu.ram.set(0x0000, compile_word(0x01, 0x00, 0x3)) # set reg a to a - b
cpu.step()
assert cpu.reg.a == 0x2000
assert cpu.reg.b == 0xf000
assert cpu.cycle == 2
assert cpu.reg.pc == 1
assert cpu.reg.o == 0xffff
def test_JSR(cpu):
cpu.ram.set(0x0000, compile_word(0x25, 0x01, 0x00)) # push address of next instruction to stack and jump to 5
cpu.step()
assert cpu.cycle == 2
assert cpu.reg.pc == 5
assert cpu.ram.get(cpu.reg.sp) == 1
def test_compile_decompile_word():
assert compile_word(0x00, 0x00, 0x0) == 0x0000
assert compile_word(0x03, 0x01, 0x2) == 0b0000110000010010 # ADD register B to register X and put in register B
assert decompile_word(0b0000110000010010) == (0x03, 0x01, 0x2)
