def __init__(self, use_verify_thread):
self.state = None
self.ctlr = Controller(autoflush=0, br=1000000)
self.npulses = 0
self.EST_SPEED = 100000.0
self.bufbuf = ''
if use_verify_thread:
self._verify_queue = Queue.Queue(maxsize=4)
t = threading.Thread(target=self._verify_thread)
t.setDaemon(True)
t.start()
def __init__(self):
self.state = None
self.ctlr = Controller(autoflush=0, br=500000)
self.buf = None
self.npulses = 0
self.est_buf = 0
self.EST_SPEED = 20.0
self.last_est = time.time()
self._verify_queue = Queue.Queue(maxsize=1)
t = threading.Thread(target=self._verify_thread)
t.setDaemon(True)
t.start()
def __init__(self, use_verify_thread):
self.state = None
self.ctlr = Controller(autoflush=0, br=1000000)
self.npulses = 0
self.EST_SPEED = 100000.0
self.bufbuf = ''
if use_verify_thread:
self._verify_queue = Queue.Queue(maxsize=4)
t = threading.Thread(target=self._verify_thread)
t.setDaemon(True)
t.start()
def __init__(self):
self.state = None
self.ctlr = Controller(autoflush=0, br=500000)
self.buf = None
self.npulses = 0
self.est_buf = 0
self.EST_SPEED = 15000.0
self.last_est = time.time()
self._verify_queue = Queue.Queue(maxsize=1)
t = threading.Thread(target=self._verify_thread)
t.setDaemon(True)
t.start()
class JtagController(object):
def __init__(self, use_verify_thread):
self.state = None
self.ctlr = Controller(autoflush=0, br=1000000)
self.npulses = 0
self.EST_SPEED = 100000.0
self.bufbuf = ''
if use_verify_thread:
self._verify_queue = Queue.Queue(maxsize=4)
t = threading.Thread(target=self._verify_thread)
t.setDaemon(True)
t.start()
def _write(self, s):
self.ctlr._write(s)
def sleep_micros(self, micros):
assert self.state in ("drpause", "idle", "irpause"), self.state
# start = time.time()
micros_per_pulse = 1000000.0 / (self.EST_SPEED)
npulses = int((micros + micros_per_pulse + 1) / micros_per_pulse)
npulses = max(npulses, 5)
# print "Doing %d pulses" % npulses
for i in xrange(npulses):
self.pulse(0, 0, get_tdo=False)
# print time.time() - start
def flush(self):
# assert not self.bufbuf
self._write(self.bufbuf)
self.bufbuf = ""
self.ctlr.flush()
# time.sleep(0.001)
def pulse(self, tms, tdi, get_tdo=True):
# with print_lock:
# print tms, tdi, get_tdo
data = (tms << 3) | (tdi << 2) | (get_tdo << 1)
data = chr(data + 16)
self.bufbuf += data
if len(self.bufbuf) >= 1024:
self._write(self.bufbuf)
# time.sleep(0.001)
self.bufbuf = ""
self.npulses += 1
# if self.npulses % 100 == 0:
# time.sleep(0.001)
def queue_verify(self, nbits, tdo, tdo_mask):
return # verifying is broken
try:
self._verify_queue.put((nbits, tdo, tdo_mask), timeout=0)
except Queue.Full:
self.flush()
self._verify_queue.put((nbits, tdo, tdo_mask), timeout=60)
# self.join()
def _verify_thread(self):
while True:
nbits, tdo, mask = self._verify_queue.get()
print "waiting for %d bits" % nbits
hex_digits = [0] * ((nbits + 3) / 4)
for i in xrange(nbits):
if i and i % 10000 == 0:
with print_lock:
print "i =", i, self.ctlr.q.qsize()
# print i, nbits
c = self.ctlr.q.get()
if c != '\0':
hex_digits[i/4] |= (1 << (i%4))
got_tdo_hex = ''.join(reversed([hex(i)[2] for i in hex_digits]))
got_tdo = int(got_tdo_hex, 16)
mismatch = (got_tdo ^ tdo) & mask
if mismatch:
if mask < (1<<1000):
with print_lock:
print "Gotten: ", bin(got_tdo)[2:].rjust(nbits, '0')
print "Expected: ", bin(tdo)[2:].rjust(nbits, '0')
print "Care-mask: ", bin(mask)[2:].rjust(nbits, '0')
else:
with print_lock:
print "Mismatch -- too long to print, but %d/%d bits different" % (bin(mismatch).count('1'), nbits)
# with open("gotten.out", 'w') as f:
# f.write(bin(got_tdo)[2:].rjust(nbits, '0'))
# with open("expected.out", 'w') as f:
# f.write(bin(tdo)[2:].rjust(nbits, '0'))
# with open("mask.out", 'w') as f:
# f.write(bin(mask)[2:].rjust(nbits, '0'))
# print "Written to gotten.out, expected.out, and mask.out"
# raise Exception()
os._exit(-1)
self._verify_queue.task_done()
def join(self):
self.flush()
self._verify_queue.join()
def send(self, nbits, tdi, tdo_mask):
assert self.state in ("irshift", "drshift"), self.state
tdi_hex = hex(tdi)
assert tdi_hex.startswith("0x")
if tdi_hex.endswith("L"):
tdi_hex = tdi_hex[2:-1]
else:
tdi_hex = tdi_hex[2:]
tdi_hex = tdi_hex.rjust((nbits + 3) / 4, '0')
for i in xrange(nbits):
tdi_chr = tdi_hex[-(i/4 + 1)]
tdi_bit = (int(tdi_chr, 16) >> (i % 4)) & 1
get_tdo = 0 if i == nbits-1 else 1
self.pulse(1 if i == nbits-1 else 0, tdi_bit, get_tdo=get_tdo)
if (nbits - i) % 10000 == 0:
print "%d bits left in this command" % (nbits - i,)
if self.state == "irshift":
self.state = "irexit1"
else:
self.state = "drexit1"
def goto(self, new_state):
new_state = new_state.lower()
if self.state is None or new_state == "reset":
for i in xrange(5):
self.pulse(1, 0, get_tdo=False)
self.state = "reset"
assert self.state
while new_state != self.state:
if self.state == "reset":
self.pulse(0, 0, get_tdo=False)
self.state = "idle"
elif self.state == "idle":
self.pulse(1, 0, get_tdo=False)
self.state = "drselect"
elif self.state == "irpause":
self.pulse(1, 0, get_tdo=False)
self.state = "irexit2"
elif self.state == "irexit2":
if new_state in ("irupdate", "idle") or new_state.startswith("dr"):
self.pulse(1, 0, get_tdo=False)
self.state = "irupdate"
elif new_state == "irshift":
self.pulse(0, 0, get_tdo=True)
self.state = "irshift"
else:
raise Exception(new_state)
elif self.state == "irupdate" or self.state == "drupdate":
if new_state == "idle":
self.pulse(0, 0, get_tdo=False)
self.state = "idle"
else:
self.pulse(1, 0, get_tdo=False)
self.state = "drselect"
elif self.state == "drselect":
if new_state.startswith("dr"):
self.pulse(0, 0, get_tdo=False)
self.state = "drcapture"
else:
self.pulse(1, 0, get_tdo=False)
self.state = "irselect"
elif self.state == "irselect":
assert new_state.startswith("ir")
self.pulse(0, 0, get_tdo=False)
self.state = "ircapture"
elif self.state == "drcapture":
if new_state in ("drexit1", "drpause"):
self.pulse(1, 0, get_tdo=False)
self.state = "drexit1"
elif new_state == "drshift":
self.pulse(0, 0, get_tdo=True)
self.state = "drshift"
else:
raise Exception(new_state)
elif self.state == "ircapture":
if new_state in ("irexit1", "irpause"):
self.pulse(1, 0, get_tdo=False)
self.state = "irexit1"
elif new_state == "irshift":
self.pulse(0, 0, get_tdo=True)
self.state = "irshift"
else:
raise Exception(new_state)
elif self.state == "drexit1":
if new_state == "drpause":
self.pulse(0, 0, get_tdo=False)
self.state = "drpause"
elif new_state in ("idle", "drupdate"):
self.pulse(1, 0, get_tdo=False)
self.state = "drupdate"
else:
raise Exception(new_state)
elif self.state == "irexit1":
if new_state == "irpause":
self.pulse(0, 0, get_tdo=False)
self.state = "irpause"
elif new_state == "idle":
self.pulse(1, 0, get_tdo=False)
self.state = "irupdate"
else:
raise Exception(new_state)
elif self.state == "drpause":
self.pulse(1, 0, get_tdo=False)
self.state = "drexit2"
elif self.state == "drexit2":
if new_state in ("drupdate", "idle", "irshift"):
self.pulse(1, 0, get_tdo=False)
self.state = "drupdate"
else:
raise Exception(new_state)
else:
raise Exception((self.state, new_state))
def main():
ctlr = Controller()
ctlr.on_read.append(on_read)
TDO = 5
TCK = 4
TMS = 3
TDI = 2
DBG1 = 6
DBG2 = 7
ctlr.pinMode(TDO, "input")
ctlr.pinMode(TCK, "output")
ctlr.pinMode(TMS, "output")
ctlr.pinMode(TDI, "output")
ctlr.pinMode(DBG1, "output")
ctlr.pinMode(DBG2, "output")
def pulse(tms, tdi):
DELAY = 0.0
ctlr.digitalWrite(TMS, tms)
ctlr.digitalWrite(TDI, tdi)
time.sleep(DELAY)
ctlr.digitalWrite(TCK, 1)
time.sleep(DELAY)
ctlr.digitalWrite(TCK, 0)
time.sleep(DELAY)
ctlr.digitalRead(TDO)
b = ord(q.get())
print "pulse", tms, tdi, b
return b
def idcode1():
# Move to Test-Logic Reset
print "Resetting"
for i in xrange(5):
pulse(1, 0)
# Move to shift-IR:
print "moving to shift-IR"
pulse(0, 0)
pulse(1, 0)
pulse(1, 0)
pulse(0, 0)
pulse(0, 0)
# shift in 0x0001:
print "shifting in IDCODE"
pulse(0, 1)
pulse(0, 0)
pulse(0, 0)
pulse(0, 0)
pulse(0, 0)
pulse(0, 0)
pulse(0, 0)
pulse(1, 0) # move to exit-IR
# Move to shift-DR:
print "moving to shift-DR"
pulse(1, 0)
pulse(1, 0)
pulse(0, 0)
pulse(0, 0)
print "shifting out DR"
ctlr.digitalWrite(DBG1, 1)
for i in xrange(31):
pulse(0, i&1)
pulse(0, 0)
ctlr.digitalWrite(DBG1, 0)
def idcode2():
# Move to Test-Logic Reset
print "Resetting"
for i in xrange(5):
pulse(1, 0)
print "moving to shift-DR"
pulse(0, 0)
pulse(1, 0)
pulse(0, 0)
pulse(0, 0)
print "shifting out DR"
ctlr.digitalWrite(DBG1, 1)
for i in xrange(31):
pulse(0, i&1)
pulse(0, 0)
ctlr.digitalWrite(DBG1, 0)
def reset():
# Move to Test-Logic Reset
print "Resetting"
for i in xrange(5):
pulse(1, 0)
# Move to run-test/idle
pulse(0, 0)
def extest(val):
# Move to shift-IR:
print "moving to shift-IR"
pulse(0, 0)
pulse(1, 0)
pulse(1, 0)
pulse(0, 0)
pulse(0, 0)
# shift in 0x0001:
print "shifting in EXTEST"
pulse(0, 0)
pulse(0, 0)
pulse(0, 0)
pulse(0, 0)
pulse(0, 0)
pulse(0, 0)
pulse(0, 0)
pulse(1, 0) # move to exit-IR
# Move to shift-DR:
print "moving to shift-DR"
pulse(1, 0)
pulse(1, 0)
pulse(0, 0)
b = pulse(0, 0)
print "shifting out DR"
ctlr.digitalWrite(DBG1, 1)
data = [0] * 97
data[25] = 1 # enable pin 2 output
data[26] = val # drive pin 2 high
for i in xrange(97):
print i, "%02x" % b
b = pulse(1 if i == 96 else 0, data[i])
ctlr.digitalWrite(DBG1, 0)
pulse(1, 0) # move to Update-DR
# pulse(1, 0) # move to Run-Test/Idle
idcode1()
class JtagController(object):
def __init__(self):
self.state = None
self.ctlr = Controller(autoflush=0, br=500000)
self.buf = None
self.npulses = 0
self.est_buf = 0
self.EST_SPEED = 15000.0
self.last_est = time.time()
self._verify_queue = Queue.Queue(maxsize=1)
t = threading.Thread(target=self._verify_thread)
t.setDaemon(True)
t.start()
def _write(self, s):
# print bin(ord(s))[2:].rjust(8, '0')
assert len(s) < 10
cost = len(s)
while True:
now = time.time()
new_est = self.est_buf - self.EST_SPEED * (now - self.last_est)
self.est_buf = max(new_est, 0)
self.last_est = now
if self.est_buf + cost < 50:
break
self.ctlr.flush()
self.est_buf += cost
self.ctlr._write(s)
def sleep_micros(self, micros):
assert self.state in ("drpause", "idle", "irpause"), self.state
# The 'correct' value here is 22, but
# overclock it to 50 which seems to work (100 seems stable).
for i in xrange(0, micros, 50):
self.pulse(0, 0, get_tdo=False)
def flush(self):
if self.buf is not None:
self._write(chr(self.buf | (1<<4)))
self.buf = None
self.ctlr.flush()
def pulse(self, tms, tdi, get_tdo=True):
data = (tms << 3) | (tdi << 2) | (get_tdo << 1)
if self.buf is None:
self.buf = data
else:
self._write(chr((self.buf << 4) | data))
self.buf = None
self.npulses += 1
def queue_verify(self, nbits, tdo, tdo_mask):
try:
self._verify_queue.put((nbits, tdo, tdo_mask), timeout=0)
except Queue.Full:
self.flush()
self._verify_queue.put((nbits, tdo, tdo_mask))
def _verify_thread(self):
while True:
nbits, tdo, mask = self._verify_queue.get()
got_tdo = 0
for i in xrange(nbits):
# print i, nbits
d = ord(self.ctlr.q.get())
if d:
got_tdo |= 1 << i
if (got_tdo ^ tdo) & mask:
print bin(got_tdo).rjust(nbits+10)
print bin(tdo).rjust(nbits+10)
print bin(mask).rjust(nbits+10)
os._exit(1)
self._verify_queue.task_done()
def join(self):
self.flush()
self._verify_queue.join()
def send(self, nbits, tdi, tdo_mask):
assert self.state in ("irshift", "drshift"), self.state
for i in xrange(nbits):
bitmask = (1<<i)
get_tdo = 0 if i == nbits-1 else 1
self.pulse(1 if i == nbits-1 else 0, 1 if (tdi & bitmask) else 0, get_tdo=get_tdo)
if self.state == "irshift":
self.state = "irexit1"
else:
self.state = "drexit1"
def goto(self, new_state):
new_state = new_state.lower()
if self.state is None:
assert new_state == "reset"
else:
assert new_state != "reset"
while new_state != self.state:
if self.state is None:
assert new_state == "reset"
for i in xrange(5):
self.pulse(1, 0, get_tdo=False)
self.state = "reset"
elif self.state == "reset":
self.pulse(0, 0, get_tdo=False)
self.state = "idle"
elif self.state == "idle":
self.pulse(1, 0, get_tdo=False)
self.state = "drselect"
elif self.state == "irpause":
self.pulse(1, 0, get_tdo=False)
self.state = "irexit2"
elif self.state == "irexit2":
if new_state in ("irupdate", "idle") or new_state.startswith("dr"):
self.pulse(1, 0, get_tdo=False)
self.state = "irupdate"
else:
raise Exception(new_state)
elif self.state == "irupdate" or self.state == "drupdate":
if new_state == "idle":
self.pulse(0, 0, get_tdo=False)
self.state = "idle"
else:
self.pulse(1, 0, get_tdo=False)
self.state = "drselect"
elif self.state == "drselect":
if new_state.startswith("dr"):
self.pulse(0, 0, get_tdo=False)
self.state = "drcapture"
else:
self.pulse(1, 0, get_tdo=False)
self.state = "irselect"
elif self.state == "irselect":
assert new_state.startswith("ir")
self.pulse(0, 0, get_tdo=False)
self.state = "ircapture"
elif self.state == "drcapture":
if new_state in ("drexit1", "drpause"):
self.pulse(1, 0, get_tdo=False)
self.state = "drexit1"
elif new_state == "drshift":
self.pulse(0, 0, get_tdo=True)
self.state = "drshift"
else:
raise Exception(new_state)
elif self.state == "ircapture":
if new_state in ("irexit1", "irpause"):
self.pulse(1, 0, get_tdo=False)
self.state = "irexit1"
elif new_state == "irshift":
self.pulse(0, 0, get_tdo=True)
self.state = "irshift"
else:
raise Exception(new_state)
elif self.state == "drexit1":
if new_state == "drpause":
self.pulse(0, 0, get_tdo=False)
self.state = "drpause"
elif new_state in ("idle", "drupdate"):
self.pulse(1, 0, get_tdo=False)
self.state = "drupdate"
else:
raise Exception(new_state)
elif self.state == "irexit1":
if new_state == "irpause":
self.pulse(0, 0, get_tdo=False)
self.state = "irpause"
elif new_state == "idle":
self.pulse(1, 0, get_tdo=False)
self.state = "irupdate"
else:
raise Exception(new_state)
elif self.state == "drpause":
self.pulse(1, 0, get_tdo=False)
self.state = "drexit2"
elif self.state == "drexit2":
if new_state in ("drupdate", "idle", "irshift"):
self.pulse(1, 0, get_tdo=False)
self.state = "drupdate"
else:
raise Exception(new_state)
else:
raise Exception((self.state, new_state))
class JtagController(object):
def __init__(self, use_verify_thread):
self.state = None
self.ctlr = Controller(autoflush=0, br=1000000)
self.npulses = 0
self.EST_SPEED = 100000.0
self.bufbuf = ''
if use_verify_thread:
self._verify_queue = Queue.Queue(maxsize=4)
t = threading.Thread(target=self._verify_thread)
t.setDaemon(True)
t.start()
def _write(self, s):
self.ctlr._write(s)
def sleep_micros(self, micros):
if micros > 100000:
with print_lock:
print "Sleeping for %.1fs" % (micros / 1000000.0)
assert self.state in ("drpause", "idle", "irpause"), self.state
# start = time.time()
micros_per_pulse = 1000000.0 / (self.EST_SPEED)
npulses = int((micros + micros_per_pulse + 1) / micros_per_pulse)
npulses = max(npulses, 5)
# print "Doing %d pulses" % npulses
for i in xrange(npulses):
self.pulse(0, 0, get_tdo=False)
# print time.time() - start
def flush(self):
# assert not self.bufbuf
self._write(self.bufbuf)
self.bufbuf = ""
self.ctlr.flush()
# time.sleep(0.001)
def pulse(self, tms, tdi, get_tdo=True):
# with print_lock:
# print "pulse", tms, tdi, get_tdo
data = (tms << 3) | (tdi << 2) | (get_tdo << 1)
data = chr(data + 16)
self.bufbuf += data
if len(self.bufbuf) >= 1024:
self._write(self.bufbuf)
# time.sleep(0.001)
self.bufbuf = ""
self.npulses += 1
# if self.npulses % 100 == 0:
# time.sleep(0.001)
def queue_verify(self, nbits, tdo, tdo_mask):
return # verifying is broken
try:
self._verify_queue.put((nbits, tdo, tdo_mask), timeout=0)
except Queue.Full:
self.flush()
self._verify_queue.put((nbits, tdo, tdo_mask), timeout=60)
# self.join()
def _verify_thread(self):
while True:
nbits, tdo, mask = self._verify_queue.get()
print "waiting for %d bits" % nbits
hex_digits = [0] * ((nbits + 3) / 4)
for i in xrange(nbits):
if i and i % 10000 == 0:
with print_lock:
print "i =", i, self.ctlr.q.qsize()
# print i, nbits
c = self.ctlr.q.get()
if c != '\0':
hex_digits[i / 4] |= (1 << (i % 4))
got_tdo_hex = ''.join(reversed([hex(i)[2] for i in hex_digits]))
got_tdo = int(got_tdo_hex, 16)
mismatch = (got_tdo ^ tdo) & mask
if mismatch:
if mask < (1 << 1000):
with print_lock:
print "Gotten: ", bin(got_tdo)[2:].rjust(
nbits, '0')
print "Expected: ", bin(tdo)[2:].rjust(nbits, '0')
print "Care-mask: ", bin(mask)[2:].rjust(nbits, '0')
else:
with print_lock:
print "Mismatch -- too long to print, but %d/%d bits different" % (
bin(mismatch).count('1'), nbits)
# with open("gotten.out", 'w') as f:
# f.write(bin(got_tdo)[2:].rjust(nbits, '0'))
# with open("expected.out", 'w') as f:
# f.write(bin(tdo)[2:].rjust(nbits, '0'))
# with open("mask.out", 'w') as f:
# f.write(bin(mask)[2:].rjust(nbits, '0'))
# print "Written to gotten.out, expected.out, and mask.out"
# raise Exception()
os._exit(-1)
self._verify_queue.task_done()
def join(self):
self.flush()
self._verify_queue.join()
def send(self, nbits, tdi, tdo_mask):
assert self.state in ("irshift", "drshift"), self.state
tdi_hex = hex(tdi)
assert tdi_hex.startswith("0x")
if tdi_hex.endswith("L"):
tdi_hex = tdi_hex[2:-1]
else:
tdi_hex = tdi_hex[2:]
tdi_hex = tdi_hex.rjust((nbits + 3) / 4, '0')
for i in xrange(nbits):
tdi_chr = tdi_hex[-(i / 4 + 1)]
tdi_bit = (int(tdi_chr, 16) >> (i % 4)) & 1
get_tdo = True
self.pulse(1 if i == nbits - 1 else 0, tdi_bit, get_tdo=get_tdo)
if (nbits - i) % 10000 == 0:
print "%d bits left in this command" % (nbits - i, )
if self.state == "irshift":
self.state = "irexit1"
else:
self.state = "drexit1"
def goto(self, new_state):
new_state = new_state.lower()
if self.state is None or new_state == "reset":
for i in xrange(5):
self.pulse(1, 0, get_tdo=False)
self.state = "reset"
assert self.state
while new_state != self.state:
if self.state == "reset":
self.pulse(0, 0, get_tdo=False)
self.state = "idle"
elif self.state == "idle":
self.pulse(1, 0, get_tdo=False)
self.state = "drselect"
elif self.state == "irpause":
self.pulse(1, 0, get_tdo=False)
self.state = "irexit2"
elif self.state == "irexit2":
if new_state in ("irupdate",
"idle") or new_state.startswith("dr"):
self.pulse(1, 0, get_tdo=False)
self.state = "irupdate"
elif new_state == "irshift":
self.pulse(0, 0, get_tdo=False)
self.state = "irshift"
else:
raise Exception(new_state)
elif self.state == "irupdate" or self.state == "drupdate":
if new_state == "idle":
self.pulse(0, 0, get_tdo=False)
self.state = "idle"
else:
self.pulse(1, 0, get_tdo=False)
self.state = "drselect"
elif self.state == "drselect":
if new_state.startswith("dr"):
self.pulse(0, 0, get_tdo=False)
self.state = "drcapture"
else:
self.pulse(1, 0, get_tdo=False)
self.state = "irselect"
elif self.state == "irselect":
assert new_state.startswith("ir")
self.pulse(0, 0, get_tdo=False)
self.state = "ircapture"
elif self.state == "drcapture":
if new_state in ("drexit1", "drpause"):
self.pulse(1, 0, get_tdo=False)
self.state = "drexit1"
elif new_state == "drshift":
self.pulse(0, 0, get_tdo=False)
self.state = "drshift"
else:
raise Exception(new_state)
elif self.state == "ircapture":
if new_state in ("irexit1", "irpause"):
self.pulse(1, 0, get_tdo=False)
self.state = "irexit1"
elif new_state == "irshift":
self.pulse(0, 0, get_tdo=False)
self.state = "irshift"
else:
raise Exception(new_state)
elif self.state == "drexit1":
if new_state == "drpause":
self.pulse(0, 0, get_tdo=False)
self.state = "drpause"
elif new_state in ("idle", "drupdate"):
self.pulse(1, 0, get_tdo=False)
self.state = "drupdate"
else:
raise Exception(new_state)
elif self.state == "irexit1":
if new_state == "irpause":
self.pulse(0, 0, get_tdo=False)
self.state = "irpause"
elif new_state == "idle":
self.pulse(1, 0, get_tdo=False)
self.state = "irupdate"
else:
raise Exception(new_state)
elif self.state == "drpause":
self.pulse(1, 0, get_tdo=False)
self.state = "drexit2"
elif self.state == "drexit2":
if new_state in ("drupdate", "idle", "irshift"):
self.pulse(1, 0, get_tdo=False)
self.state = "drupdate"
else:
raise Exception(new_state)
else:
raise Exception((self.state, new_state))
class JtagController(object):
def __init__(self):
self.state = None
self.ctlr = Controller(autoflush=0, br=500000)
self.buf = None
self.npulses = 0
self.est_buf = 0
self.EST_SPEED = 20.0
self.last_est = time.time()
self._verify_queue = Queue.Queue(maxsize=1)
t = threading.Thread(target=self._verify_thread)
t.setDaemon(True)
t.start()
def _write(self, s):
# print bin(ord(s))[2:].rjust(8, '0')
assert len(s) < 10
cost = len(s)
while True:
now = time.time()
new_est = self.est_buf - self.EST_SPEED * (now - self.last_est)
self.est_buf = max(new_est, 0)
self.last_est = now
if self.est_buf + cost < 50:
break
self.ctlr.flush()
self.est_buf += cost
self.ctlr._write(s)
def sleep_micros(self, micros):
assert self.state in ("drpause", "idle", "irpause"), self.state
# The 'correct' value here is 22, but
# overclock it to 50 which seems to work (100 seems stable).
for i in xrange(0, micros, 22):
self.pulse(0, 0, get_tdo=False)
def flush(self):
if self.buf is not None:
self._write(chr(self.buf | (1 << 4)))
self.buf = None
self.ctlr.flush()
def pulse(self, tms, tdi, get_tdo=True):
print "pulse", tms, tdi, get_tdo
data = (tms << 3) | (tdi << 2) | (get_tdo << 1)
if self.buf is None:
self.buf = data
else:
self._write(chr((self.buf << 4) | data))
self.buf = None
self.npulses += 1
def queue_verify(self, nbits, tdo, tdo_mask):
try:
self._verify_queue.put((nbits, tdo, tdo_mask), timeout=0)
except Queue.Full:
self.flush()
self._verify_queue.put((nbits, tdo, tdo_mask))
def _verify_thread(self):
while True:
nbits, tdo, mask = self._verify_queue.get()
got_tdo = 0
for i in xrange(nbits):
# print i, nbits
d = ord(self.ctlr.q.get())
if d:
got_tdo |= 1 << i
if (got_tdo ^ tdo) & mask:
with print_lock:
print bin(got_tdo).rjust(nbits + 10)
print bin(tdo).rjust(nbits + 10)
print bin(mask).rjust(nbits + 10)
os._exit(1)
self._verify_queue.task_done()
def join(self):
self.flush()
self._verify_queue.join()
def send(self, nbits, tdi, tdo_mask):
assert self.state in ("irshift", "drshift"), self.state
for i in xrange(nbits):
bitmask = (1 << i)
get_tdo = 0 if i == nbits - 1 else 1
self.pulse(1 if i == nbits - 1 else 0,
1 if (tdi & bitmask) else 0,
get_tdo=get_tdo)
if self.state == "irshift":
self.state = "irexit1"
else:
self.state = "drexit1"
def goto(self, new_state):
new_state = new_state.lower()
if self.state is None:
assert new_state == "reset"
else:
assert new_state != "reset"
while new_state != self.state:
if self.state is None:
assert new_state == "reset"
for i in xrange(5):
self.pulse(1, 0, get_tdo=False)
self.state = "reset"
elif self.state == "reset":
self.pulse(0, 0, get_tdo=False)
self.state = "idle"
elif self.state == "idle":
self.pulse(1, 0, get_tdo=False)
self.state = "drselect"
elif self.state == "irpause":
self.pulse(1, 0, get_tdo=False)
self.state = "irexit2"
elif self.state == "irexit2":
if new_state in ("irupdate",
"idle") or new_state.startswith("dr"):
self.pulse(1, 0, get_tdo=False)
self.state = "irupdate"
else:
raise Exception(new_state)
elif self.state == "irupdate" or self.state == "drupdate":
if new_state == "idle":
self.pulse(0, 0, get_tdo=False)
self.state = "idle"
else:
self.pulse(1, 0, get_tdo=False)
self.state = "drselect"
elif self.state == "drselect":
if new_state.startswith("dr"):
self.pulse(0, 0, get_tdo=False)
self.state = "drcapture"
else:
self.pulse(1, 0, get_tdo=False)
self.state = "irselect"
elif self.state == "irselect":
assert new_state.startswith("ir")
self.pulse(0, 0, get_tdo=False)
self.state = "ircapture"
elif self.state == "drcapture":
if new_state in ("drexit1", "drpause"):
self.pulse(1, 0, get_tdo=False)
self.state = "drexit1"
elif new_state == "drshift":
self.pulse(0, 0, get_tdo=True)
self.state = "drshift"
else:
raise Exception(new_state)
elif self.state == "ircapture":
if new_state in ("irexit1", "irpause"):
self.pulse(1, 0, get_tdo=False)
self.state = "irexit1"
elif new_state == "irshift":
self.pulse(0, 0, get_tdo=True)
self.state = "irshift"
else:
raise Exception(new_state)
elif self.state == "drexit1":
if new_state == "drpause":
self.pulse(0, 0, get_tdo=False)
self.state = "drpause"
elif new_state in ("idle", "drupdate"):
self.pulse(1, 0, get_tdo=False)
self.state = "drupdate"
else:
raise Exception(new_state)
elif self.state == "irexit1":
if new_state == "irpause":
self.pulse(0, 0, get_tdo=False)
self.state = "irpause"
elif new_state == "idle":
self.pulse(1, 0, get_tdo=False)
self.state = "irupdate"
else:
raise Exception(new_state)
elif self.state == "drpause":
self.pulse(1, 0, get_tdo=False)
self.state = "drexit2"
elif self.state == "drexit2":
if new_state in ("drupdate", "idle", "irshift"):
self.pulse(1, 0, get_tdo=False)
self.state = "drupdate"
else:
raise Exception(new_state)
else:
raise Exception((self.state, new_state))
class JtagController(object):
def __init__(self, use_verify_thread):
self.state = None
self.ctlr = Controller(autoflush=0, br=500000)
self.buf = None
self.npulses = 0
self.est_buf = 0
self.EST_SPEED = 15000.0
self.last_est = time.time()
self.pending_bits = 0
if use_verify_thread:
self._verify_queue = Queue.Queue(maxsize=2)
t = threading.Thread(target=self._verify_thread)
t.setDaemon(True)
t.start()
def _write(self, s):
# print bin(ord(s))[2:].rjust(8, '0')
assert len(s) < 10
cost = len(s)
while True:
now = time.time()
new_est = self.est_buf - self.EST_SPEED * (now - self.last_est)
self.est_buf = max(new_est, 0)
self.last_est = now
if self.est_buf + cost < 50:
break
self.ctlr.flush()
self.est_buf += cost
self.ctlr._write(s)
def sleep_micros(self, micros):
assert self.state in ("drpause", "idle", "irpause"), self.state
# start = time.time()
micros_per_pulse = 1000000.0 / (self.EST_SPEED * 2)
npulses = int((micros + micros_per_pulse + 1) / micros_per_pulse)
npulses = max(npulses, 5)
# print "Doing %d pulses" % npulses
for i in xrange(npulses):
self.pulse(0, 0, get_tdo=False)
# print time.time() - start
def flush(self):
if self.buf is not None:
self._write(chr(self.buf | (1 << 4)))
self.buf = None
self.ctlr.flush()
def pulse(self, tms, tdi, get_tdo=True):
# with print_lock:
# print tms, tdi, get_tdo
data = (tms << 3) | (tdi << 2) | (get_tdo << 1)
if self.buf is None:
self.buf = data
else:
self._write(chr((self.buf << 4) | data))
self.buf = None
self.npulses += 1
if get_tdo:
with print_lock:
# assert self.pending_bits >= 0
self.pending_bits += 1
while self.pending_bits >= 512:
# print "Slowing down, %d bits pending" % self.pending_bits
time.sleep(0.01)
# if self.npulses % 1000 == 0:
# time.sleep(0.01)
def queue_verify(self, nbits, tdo, tdo_mask):
try:
self._verify_queue.put((nbits, tdo, tdo_mask), timeout=0)
except Queue.Full:
self.flush()
self._verify_queue.put((nbits, tdo, tdo_mask), timeout=600)
# self.join()
def _verify_thread(self):
nmismatches = 0
while True:
nbits, tdo, mask = self._verify_queue.get()
print "waiting for %d bits" % nbits
hex_digits = [0] * ((nbits + 3) / 4)
for i in xrange(nbits):
# if i and i % 10000 == 0:
# with print_lock:
# print "i =", i, self.ctlr.q.qsize()
# print i, nbits
c = self.ctlr.q.get()
with print_lock:
self.pending_bits -= 1
# assert self.pending_bits >= 0
if c != '\0':
hex_digits[i / 4] |= (1 << (i % 4))
got_tdo_hex = ''.join(reversed([hex(i)[2] for i in hex_digits]))
got_tdo = int(got_tdo_hex, 16)
mismatch = (got_tdo ^ tdo) & mask
if mismatch:
if mask < (1 << 1000):
with print_lock:
print "Gotten: ", bin(got_tdo)[2:].rjust(
nbits, '0')
print "Expected: ", bin(tdo)[2:].rjust(nbits, '0')
print "Care-mask: ", bin(mask)[2:].rjust(nbits, '0')
with print_lock:
print "Mismatch -- too long to print, but %d/%d bits different" % (
bin(mismatch).count('1'), nbits)
with open("gotten%d.out" % nmismatches, 'w') as f:
f.write(bin(got_tdo)[2:].rjust(nbits, '0'))
with open("expected%d.out" % nmismatches, 'w') as f:
f.write(bin(tdo)[2:].rjust(nbits, '0'))
with open("mask%d.out" % nmismatches, 'w') as f:
f.write(bin(mask)[2:].rjust(nbits, '0'))
print "Written to gotten.out, expected.out, and mask.out"
nmismatches += 1
# raise Exception()
# os._exit(-1)
# raise Exception()
self._verify_queue.task_done()
def join(self):
self.flush()
self._verify_queue.join()
def send(self, nbits, tdi, tdo_mask):
assert self.state in ("irshift", "drshift"), self.state
tdi_hex = hex(tdi)
assert tdi_hex.startswith("0x")
if tdi_hex.endswith("L"):
tdi_hex = tdi_hex[2:-1]
else:
tdi_hex = tdi_hex[2:]
tdi_hex = tdi_hex.rjust((nbits + 3) / 4, '0')
for i in xrange(nbits):
tdi_chr = tdi_hex[-(i / 4 + 1)]
tdi_bit = (int(tdi_chr, 16) >> (i % 4)) & 1
get_tdo = 0 if i == nbits - 1 else 1
self.pulse(1 if i == nbits - 1 else 0, tdi_bit, get_tdo=get_tdo)
if (nbits - i) % 10000 == 0:
print "%d bits left in this command" % (nbits - i, )
if self.state == "irshift":
self.state = "irexit1"
else:
self.state = "drexit1"
def goto(self, new_state):
new_state = new_state.lower()
if self.state is None or new_state == "reset":
for i in xrange(5):
self.pulse(1, 0, get_tdo=False)
self.state = "reset"
assert self.state
while new_state != self.state:
if self.state == "reset":
self.pulse(0, 0, get_tdo=False)
self.state = "idle"
elif self.state == "idle":
self.pulse(1, 0, get_tdo=False)
self.state = "drselect"
elif self.state == "irpause":
self.pulse(1, 0, get_tdo=False)
self.state = "irexit2"
elif self.state == "irexit2":
if new_state in ("irupdate",
"idle") or new_state.startswith("dr"):
self.pulse(1, 0, get_tdo=False)
self.state = "irupdate"
else:
raise Exception(new_state)
elif self.state == "irupdate" or self.state == "drupdate":
if new_state == "idle":
self.pulse(0, 0, get_tdo=False)
self.state = "idle"
else:
self.pulse(1, 0, get_tdo=False)
self.state = "drselect"
elif self.state == "drselect":
if new_state.startswith("dr"):
self.pulse(0, 0, get_tdo=False)
self.state = "drcapture"
else:
self.pulse(1, 0, get_tdo=False)
self.state = "irselect"
elif self.state == "irselect":
assert new_state.startswith("ir")
self.pulse(0, 0, get_tdo=False)
self.state = "ircapture"
elif self.state == "drcapture":
if new_state in ("drexit1", "drpause"):
self.pulse(1, 0, get_tdo=False)
self.state = "drexit1"
elif new_state == "drshift":
self.pulse(0, 0, get_tdo=True)
self.state = "drshift"
else:
raise Exception(new_state)
elif self.state == "ircapture":
if new_state in ("irexit1", "irpause"):
self.pulse(1, 0, get_tdo=False)
self.state = "irexit1"
elif new_state == "irshift":
self.pulse(0, 0, get_tdo=True)
self.state = "irshift"
else:
raise Exception(new_state)
elif self.state == "drexit1":
if new_state == "drpause":
self.pulse(0, 0, get_tdo=False)
self.state = "drpause"
elif new_state in ("idle", "drupdate"):
self.pulse(1, 0, get_tdo=False)
self.state = "drupdate"
else:
raise Exception(new_state)
elif self.state == "irexit1":
if new_state == "irpause":
self.pulse(0, 0, get_tdo=False)
self.state = "irpause"
elif new_state == "idle":
self.pulse(1, 0, get_tdo=False)
self.state = "irupdate"
else:
raise Exception(new_state)
elif self.state == "drpause":
self.pulse(1, 0, get_tdo=False)
self.state = "drexit2"
elif self.state == "drexit2":
if new_state in ("drupdate", "idle", "irshift"):
self.pulse(1, 0, get_tdo=False)
self.state = "drupdate"
else:
raise Exception(new_state)
else:
raise Exception((self.state, new_state))
