def main(args):
if args.download or args.all:
repositoriesdownload.repositoriesdownload(args.framework, args.projects)
if args.delay or args.all:
delay.delay(args.framework, args.projects, args.githubtoken)
if args.githubmetadata or args.all:
githubmetadata.githubmetadata(args.framework, args.projects, args.githubtoken)
if args.numberofextensionfile or args.all:
numberofextensionfile.numberofextensionfile(args.framework, args.projects)
if args.currentframeworkversion or args.all:
currentframeworkversion.currentframeworkversion(args.framework, args.projects)
if args.forksahead or args.all:
forksahead.forksahead(args.framework, args.projects, args.githubtoken)
if args.importcount or args.all:
importcount.importcount(args.framework, args.projects)
if args.maintainers or args.all:
maintainers.maintainers(args.framework, args.projects, args.githubtoken)
if args.file_extension_changes or args.all:
file_extension_changes.file_extension_changes(args.framework, args.projects)
if args.file_extension_changes_forks or args.all:
file_extension_changes_forks.file_extension_changes_forks(args.framework, args.projects, args.githubtoken)
if args.understandmetrics or args.all:
understandmetrics.understandmetrics(args.framework, args.projects)
if args.metricsbycommit or args.all:
metricsbycommits.metrics_by_commits(args.framework, args.projects)
if args.stackoverflow:
stackoverflow.stackoverflow(args.framework, args.projects)
if args.generalprojects:
generalprojects.generalprojects(args.projects)
if args.allanswers:
allanswers.allanswers(args.framework, args.projects)
def main(path):
data = data_input(path)
pointcloud = delay.delay(data, target_channel)
PD = make_PD(pointcloud)
betti = betti_sequence(PD)
return betti
def __init__(self, libname, sram, spfile):
self.name = sram.name
self.num_words = sram.num_words
self.word_size = sram.word_size
self.addr_size = sram.addr_size
self.sh = setup_hold.setup_hold()
self.d = delay.delay(sram, spfile)
debug.info(1,"Writing to {0}".format(libname))
self.lib = open(libname, "w")
self.lib.write("library ({0}_lib)".format(self.name))
self.lib.write("{\n")
self.lib.write(" delay_model : \"table_lookup\";\n")
self.write_units()
self.write_defaults()
self.write_LUT()
self.lib.write(" default_operating_conditions : TT; \n")
self.write_bus()
self.lib.write("cell ({0})".format(self.name))
self.lib.write("{\n")
self.lib.write(" memory(){ \n")
self.lib.write(" type : ram;\n")
self.lib.write(" address_width : {0};\n".format(self.addr_size))
self.lib.write(" word_width : {0};\n".format(self.word_size))
self.lib.write(" }\n")
self.lib.write(" interface_timing : true;\n")
self.lib.write(" dont_use : true;\n")
self.lib.write(" map_only : true;\n")
self.lib.write(" dont_touch : true;\n")
self.lib.write(" area : {0};\n\n".format(sram.width * sram.height))
times = self.sh.analyze()
for i in times.keys():
times[i] = ch.round_time(times[i])
probe_address = "1" * self.addr_size
probe_data = self.word_size - 1
data = self.d.analyze(probe_address, probe_data)
for i in data.keys():
data[i] = ch.round_time(data[i])
self.write_data_bus(data, times)
self.write_addr_bus(times)
self.write_control_pins(times)
self.write_clk(data)
self.lib.close()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version = "hspice"
OPTS.force_spice = True
globals.set_spice()
import sram
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="test_sram1")
OPTS.check_lvsdrc = True
import delay
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(
1,
"Probe address {0} probe data {1}".format(probe_address,
probe_data))
d = delay.delay(s, tempspice)
data = d.analyze(probe_address, probe_data)
if OPTS.tech_name == "freepdk45":
self.assertTrue(isclose(data['delay1'], 0.013649))
self.assertTrue(isclose(data['delay0'], 0.22893))
self.assertTrue(isclose(data['min_period1'], 0.078582763671875))
self.assertTrue(isclose(data['min_period0'], 0.25543212890625))
elif OPTS.tech_name == "scn3me_subm":
self.assertTrue(isclose(data['delay1'], 1.5335))
self.assertTrue(isclose(data['delay0'], 2.2635000000000005))
self.assertTrue(isclose(data['min_period1'], 1.53564453125))
self.assertTrue(isclose(data['min_period0'], 2.998046875))
else:
self.assertTrue(False) # other techs fail
os.remove(tempspice)
globals.end_openram()
def compute_delay(self):
""" Do the analysis if we haven't characterized the SRAM yet """
try:
self.d
except AttributeError:
self.d = delay.delay(self.sram, self.spfile)
if self.use_model:
self.delay = self.d.analytical_model(self.sram, self.slews,
self.loads)
else:
probe_address = "1" * self.addr_size
probe_data = self.word_size - 1
self.delay = self.d.analyze(probe_address, probe_data,
self.slews, self.loads)
def main():
tabla = RAM()
visual = Rom()
registros = Rom()
reloj = Rom()
operacion = Rom()
r1= Register()
delay1=delay()
delay1.Htz()
registros.vis()
visual.vis()
reloj.vis()
operacion.vis()
print ("\n Proyecto 1 CPU Simulator ")
print ("*--------------------------------------------------------------------*")
print (""" Integrantes:
- Juan Luis Fernandez
- Rodrigo Reyes
- Esteban Samayoa\n
""")
delay1.tiempo()
if visual.v == True:
print ("*--------------------------------*")
print (" RAM ")
tabla.valoress()
delay1.tiempo()
if registros.b == True:
print (f"""
*---------------------------------*
REGISTROS:
Primer registro : {r1.R0}
Segundo registro : {r1.R1}
Tercer registro : {r1.R2}
""")
delay1.tiempo()
if reloj.c == True:
print ("*--------------------------------*")
print (f"""
Tiempo : {hrtzz.htz}
""")
delay1.tiempo()
if operacion.a == True:
cu1=CU()
cu1.operate()
def compute_delay(self):
""" Do the analysis if we haven't characterized the SRAM yet """
try:
self.d
except AttributeError:
self.d = delay.delay(self.sram, self.sim_sp_file)
if self.use_model:
self.delay = self.d.analytical_model(self.sram, self.slews,
self.loads)
else:
probe_address = "1" * self.addr_size
probe_data = self.word_size - 1
# We must trim based on a specific address and data bit
if OPTS.trim_netlist:
self.trimsp.trim(probe_address, probe_data)
self.delay = self.d.analyze(probe_address, probe_data,
self.slews, self.loads)
def runTest(self):
OPTS.analytical_delay = False
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
import sram
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="sram_func_test")
OPTS.check_lvsdrc = True
import delay
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(
1,
"Probe address {0} probe data {1}".format(probe_address,
probe_data))
d = delay.delay(s, tempspice)
d.set_probe(probe_address, probe_data)
# This will exit if it doesn't find a feasible period
import tech
load = tech.spice["FF_in_cap"] * 4
slew = tech.spice["rise_time"] * 2
feasible_period = d.find_feasible_period(load, slew)
os.remove(tempspice)
OPTS.analytical_delay = True
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.use_pex = False
import sram
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="test_sram1")
OPTS.check_lvsdrc = True
import delay
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(
1,
"Probe address {0} probe data {1}".format(probe_address,
probe_data))
d = delay.delay(s, tempspice)
d.set_probe(probe_address, probe_data)
# This will exit if it doesn't find a feasible period
feasible_period = d.find_feasible_period(2.0)
os.remove(tempspice)
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version = "hspice"
OPTS.force_spice = True
OPTS.analytical_delay = False
globals.set_spice()
import sram
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="sram1")
OPTS.check_lvsdrc = True
import delay
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(
1,
"Probe address {0} probe data {1}".format(probe_address,
probe_data))
d = delay.delay(s, tempspice)
import tech
loads = [tech.spice["FF_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data = d.analyze(probe_address, probe_data, slews, loads)
if OPTS.tech_name == "freepdk45":
golden_data = {
'read1_power': 0.025833000000000002,
'read0_power': 0.026039,
'write0_power': 0.024105,
'delay1': [0.047506],
'delay0': [0.13799999999999998],
'min_period': 0.322,
'write1_power': 0.024214,
'slew0': [0.026966],
'slew1': [0.019338]
}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {
'read1_power': 3.1765,
'read0_power': 3.1929,
'write0_power': 2.874,
'delay1': [0.8900045999999999],
'delay0': [1.9975000000000003],
'min_period': 5.781,
'write1_power': 2.6611,
'slew0': [1.2993000000000001],
'slew1': [0.9903856]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
# Check each result
for k in data.keys():
if type(data[k]) == list:
for i in range(len(data[k])):
self.assertTrue(isclose(data[k][i], golden_data[k][i]))
else:
self.assertTrue(isclose(data[k], golden_data[k]))
# reset these options
OPTS.check_lvsdrc = True
OPTS.spice_version = "hspice"
OPTS.force_spice = False
OPTS.analytical_delay = True
globals.set_spice()
os.remove(tempspice)
globals.end_openram()
class CU():
register = Register()
ram1 = RAM()
rom1 = Rom()
ram1.upcc()
ram1.instt()
delay1 = delay()
delay1.Htz()
ram1.valoress()
def operate(self):
for line in self.ram1.d:
print("-------------------------------------------------")
print("Fetch:")
print(f"La instrucción es: {self.ram1.d[line]}")
self.delay1.tiempo()
print("Decode:")
for j in self.rom1.instructions:
if self.ram1.d[line][0:4] == j:
print(self.rom1.instructions[j])
print(self.ram1.d[line][5:10])
self.delay1.tiempo()
print("Execute:")
if self.rom1.instructions[j] == "LOAD_R0":
self.rom1.valores()
posicion = int(self.ram1.d[line][5:10])
self.register.getvalue(self.rom1.val[posicion])
self.register.r0()
elif self.rom1.instructions[j] == "LOAD_R1":
self.rom1.valores()
posicion = int(self.ram1.d[line][5:10])
self.register.getvalue(self.rom1.val[posicion])
self.register.r1()
elif self.rom1.instructions[j] == "OUTPUT":
print(self.register.r1())
elif self.rom1.instructions[j] == "ADD":
a = self.ram1.d[line][5:7]
b = self.ram1.d[line][8:10]
print(a)
print(b)
alu1 = ALU(self.register.R0, self.register.R1, 0)
alu1.suma()
self.register.getvalue(alu1.result)
self.register.r1()
elif self.rom1.instructions[j] == "SUB":
a = self.ram1.d[line][5:7]
b = self.ram1.d[line][8:10]
print(a)
print(b)
alu1 = ALU(self.register.R0, self.register.R1, 0)
alu1.resta()
elif self.rom1.instructions[j] == "HALT":
exit()
elif self.rom1.instructions[j] == "AND":
a = self.ram1.d[line][5:7]
b = self.ram1.d[line][8:10]
print(a)
print(b)
alu1 = ALU(self.register.R0, self.register.R1, 0)
if alu1.And() == True:
print("La siguiente operación lógica es verdadera")
else:
print("La operación es falsa")
elif self.rom1.instructions[j] == "OR":
a = self.ram1.d[line][5:7]
b = self.ram1.d[line][8:10]
print(a)
print(b)
alu1 = ALU(self.register.R0, self.register.R1, 0)
if alu1.OR() == True:
print("La siguiente operación lógica es verdadera")
else:
print("La operación es falsa")
elif self.rom1.instructions[j] == "STORE_R0":
rom1 = Rom()
rom1.valores()
self.rom1.val[line][8:10] = self.register.R0
print(self.rom1.val[line][8:10])
elif self.rom1.instructions[j] == "STORE_R0":
rom1 = Rom()
rom1.valores()
self.rom1.val[line][8:10] = self.register.R1
print(self.rom1.val[line][8:10])
elif self.rom1.instructions[j] == "ILD_R0":
self.rom1.valores()
posicion = int(self.ram1.d[line][5:10])
self.register.getvalue(self.rom1.val[posicion])
self.register.r0()
elif self.rom1.instructions[j] == "ILD_R1":
self.rom1.valores()
posicion = int(self.ram1.d[line][5:10])
self.register.getvalue(self.rom1.val[posicion])
self.register.r1()
elif self.rom1.instructions[j] == "LOAD_R2":
self.rom1.valores()
posicion = int(self.ram1.d[line][5:10])
self.register.getvalue(self.rom1.val[posicion])
self.register.r2()
elif self.rom1.instructions[j] == "LOAD_R3":
pass
print("-------------------------------------------------")
self.delay1.tiempo()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version = "ngspice"
OPTS.force_spice = True
globals.set_spice()
import sram
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="test_sram1")
import delay
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(
1,
"Probe address {0} probe data {1}".format(probe_address,
probe_data))
d = delay.delay(s, tempspice)
import tech
loads = [tech.spice["FF_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data = d.analyze(probe_address, probe_data, slews, loads)
if OPTS.tech_name == "freepdk45":
self.assertTrue(isclose(data['delay1'][0],
0.0268)) # diff than hspice
self.assertTrue(isclose(data['delay0'][0],
0.1127)) # diff than hspice
self.assertTrue(isclose(data['slew1'][0],
0.0231)) # diff than hspice
self.assertTrue(isclose(data['slew0'][0],
0.0276)) # diff than hspice
self.assertTrue(isclose(data['min_period'],
0.071)) # diff than hspice
self.assertTrue(isclose(data['read0_power'],
0.0227)) # diff than hspice
self.assertTrue(isclose(data['read1_power'],
0.0223)) # diff than hspice
self.assertTrue(isclose(data['write0_power'],
0.02001)) # diff than hspice
self.assertTrue(isclose(data['write1_power'],
0.0193)) # diff than hspice
elif OPTS.tech_name == "scn3me_subm":
self.assertTrue(isclose(data['delay1'][0],
0.6228)) # diff than hspice
self.assertTrue(isclose(data['delay0'][0],
1.4147)) # diff than hspice
self.assertTrue(isclose(data['slew1'][0],
1.0567)) # diff than hspice
self.assertTrue(isclose(data['slew0'][0],
1.3454)) # diff than hspice
self.assertTrue(isclose(data['min_period'],
1.719)) # diff than hspice
self.assertTrue(isclose(data['read0_power'],
4.7812)) # diff than hspice
self.assertTrue(isclose(data['read1_power'],
5.5500)) # diff than hspice
self.assertTrue(isclose(data['write0_power'],
3.9314)) # diff than hspice
self.assertTrue(isclose(data['write1_power'],
3.4097)) # diff than hspice
else:
self.assertTrue(False) # other techs fail
# reset these options
OPTS.check_lvsdrc = True
OPTS.spice_version = "hspice"
OPTS.force_spice = False
globals.set_spice()
os.remove(tempspice)
globals.end_openram()
print("Genres:", genre)
db.inventory.update_one({"Title": item_title}, {
"$set": {"Genres": genres, "url": item_href}})
item = db.inventory.find({"Title": item_title})
for data in item:
pprint(data)
print("Added genre and url")
# can use cursor.count() to get number of docs that matches the find()
# curlist = list(cursor)
# if len(curlist) == 0:
# db.inventory.insert_one(data)
# pprint(data)
# print("added data")
# else:
# db.inventory.update_one(
# {"Title": item_title}, {"$set": data})
# print("updated data")
# delay(1, 5)
try:
pages = soup.find("div", {"class": "digg_pagination"}).find(
"a", {"class": "next_page"}).attrs["href"]
url = "https:"+pages
print("\nNext Page url:", url)
except:
next_page = False
print("No next page.")
i += 1
delay(15, 20)
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version = "ngspice"
OPTS.force_spice = True
globals.set_spice()
import sram
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="test_sram1")
import delay
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(
1,
"Probe address {0} probe data {1}".format(probe_address,
probe_data))
d = delay.delay(s, tempspice)
import tech
loads = [tech.spice["FF_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data = d.analyze(probe_address, probe_data, slews, loads)
if OPTS.tech_name == "freepdk45":
golden_data = {
'read1_power': 0.022260799999999997,
'read0_power': 0.02274298,
'write0_power': 0.02000899,
'delay1': [0.026754629999999998],
'delay0': [0.1126814],
'min_period': 0.273,
'write1_power': 0.01934197,
'slew0': [0.02760651],
'slew1': [0.023076919999999997]
}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {
'read1_power': 5.549996,
'read0_power': 4.781156,
'write0_power': 3.931431,
'delay1': [0.6227914],
'delay0': [1.414657],
'min_period': 4.688,
'write1_power': 3.409661,
'slew0': [1.345377],
'slew1': [1.05667]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
# Check each result
for k in data.keys():
if type(data[k]) == list:
for i in range(len(data[k])):
self.assertTrue(isclose(data[k][i], golden_data[k][i]))
else:
self.assertTrue(isclose(data[k], golden_data[k]))
# reset these options
OPTS.check_lvsdrc = True
OPTS.spice_version = "hspice"
OPTS.force_spice = False
globals.set_spice()
os.remove(tempspice)
globals.end_openram()
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version="ngspice"
OPTS.force_spice = True
OPTS.analytical_delay = False
globals.set_spice()
import sram
debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="sram1")
import delay
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(1, "Probe address {0} probe data {1}".format(probe_address, probe_data))
d = delay.delay(s,tempspice)
import tech
loads = [tech.spice["FF_in_cap"]*4]
slews = [tech.spice["rise_time"]*2]
data = d.analyze(probe_address, probe_data,slews,loads)
if OPTS.tech_name == "freepdk45":
golden_data = {'read1_power': 0.02527215,
'read0_power': 0.02573022,
'write0_power': 0.02237065,
'delay1': [0.04867785],
'delay0': [0.1423512],
'min_period': 0.332,
'write1_power': 0.02152122,
'slew0': [0.0273352],
'slew1': [0.021216870000000002]}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {'read1_power': 3.244839,
'read0_power': 3.088234,
'write0_power': 2.6857420000000003,
'delay1': [0.9200643],
'delay0': [2.0509399999999998],
'min_period': 6.563,
'write1_power': 2.378355,
'slew0': [1.342019],
'slew1': [1.040885]}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys())==len(golden_data.keys()))
# Check each result
for k in data.keys():
if type(data[k])==list:
for i in range(len(data[k])):
self.assertTrue(isclose(data[k][i],golden_data[k][i]))
else:
self.assertTrue(isclose(data[k],golden_data[k]))
# reset these options
OPTS.check_lvsdrc = True
OPTS.spice_version="hspice"
OPTS.force_spice = False
OPTS.analytical_delay = True
globals.set_spice()
os.remove(tempspice)
globals.end_openram()
print("Original Language:", item_lang)
data = getLNData(item_href, headers, item_title)
cursor = db.inventory.find({"Title": item_title})
# can use cursor.count() to get number of docs that matches the find()
curlist = list(cursor)
if len(curlist) == 0:
db.inventory.insert_one(data)
pprint(data)
print("added data")
else:
db.inventory.update_one(
{"Title": item_title}, {"$set": data})
print("updated data")
delay(1, 5)
try:
pages = soup.find("div", {"class": "digg_pagination"}).find(
"a", {"class": "next_page"}).attrs["href"]
url = "https:"+pages
print("\nNext Page url:", url)
except:
next_page = False
print("No next page.")
i += 1
delay(15, 20)
# db path for running the mongodb server\
def runTest(self):
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
# we will manually run lvs/drc
OPTS.check_lvsdrc = False
OPTS.spice_version = "hspice"
OPTS.force_spice = True
globals.set_spice()
import sram
debug.info(1,
"Testing timing for sample 1bit, 16words SRAM with 1 bank")
s = sram.sram(word_size=OPTS.config.word_size,
num_words=OPTS.config.num_words,
num_banks=OPTS.config.num_banks,
name="test_sram1")
OPTS.check_lvsdrc = True
import delay
tempspice = OPTS.openram_temp + "temp.sp"
s.sp_write(tempspice)
probe_address = "1" * s.addr_size
probe_data = s.word_size - 1
debug.info(
1,
"Probe address {0} probe data {1}".format(probe_address,
probe_data))
d = delay.delay(s, tempspice)
import tech
loads = [tech.spice["FF_in_cap"] * 4]
slews = [tech.spice["rise_time"] * 2]
data = d.analyze(probe_address, probe_data, slews, loads)
if OPTS.tech_name == "freepdk45":
golden_data = {
'read1_power': 0.017787999999999998,
'read0_power': 0.017827,
'write0_power': 0.016626,
'delay1': [0.02616],
'delay0': [0.10966999999999999],
'min_period': 0.264,
'write1_power': 0.015919000000000003,
'slew0': [0.027029],
'slew1': [0.021002999999999997]
}
elif OPTS.tech_name == "scn3me_subm":
golden_data = {
'read1_power': 4.5206,
'read0_power': 4.5492,
'write0_power': 3.8564,
'delay1': [0.5985562],
'delay0': [1.3725000000000003],
'min_period': 4.531,
'write1_power': 3.7291,
'slew0': [1.3013000000000001],
'slew1': [1.0045]
}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results
self.assertTrue(len(data.keys()) == len(golden_data.keys()))
# Check each result
for k in data.keys():
if type(data[k]) == list:
for i in range(len(data[k])):
self.assertTrue(isclose(data[k][i], golden_data[k][i]))
else:
self.assertTrue(isclose(data[k], golden_data[k]))
# reset these options
OPTS.check_lvsdrc = True
OPTS.spice_version = "hspice"
OPTS.force_spice = False
globals.set_spice()
os.remove(tempspice)
globals.end_openram()
