def build_design(self, des_template, substitutions, prefix=""):
"""
Run Diamond on a given design template, applying a map of substitutions, plus some standard substitutions
if not overriden.
:param des_template: path to template NCL/Verilog file
:param substitutions: dictionary containing template subsitutions to apply to NCL/Verilog file
:param prefix: prefix to append to filename, for running concurrent jobs without collisions
Returns the path to the output bitstream
"""
subst = dict(substitutions)
if "route" not in subst:
subst["route"] = ""
ext = des_template.split(".")[-1]
lpf_template = des_template.replace("." + ext, ".lpf")
desfile = path.join(self.workdir, prefix + "design." + ext)
bitfile = path.join(self.workdir, prefix + "design.bit")
lpffile = path.join(self.workdir, prefix + "design.lpf")
if path.exists(bitfile):
os.remove(bitfile)
with open(des_template, "r") as inf:
with open(desfile, "w") as ouf:
ouf.write(Template(inf.read()).substitute(**subst))
if path.exists(lpf_template):
with open(lpf_template, "r") as inf:
with open(lpffile, "w") as ouf:
ouf.write(Template(inf.read()).substitute(**subst))
diamond.run(self.device, desfile, no_trce=True)
if ext == "ncl" and self.ncd_specimen is None:
self.ncd_specimen = path.join(self.workdir, prefix + "design.tmp",
"par_impl.ncd")
return bitfile
def run_get_tiles(muxcfg):
with open("ccu2_template.ncl", "r") as inf:
with open("work/ccu2.ncl", "w") as ouf:
ouf.write(Template(inf.read()).substitute(muxcfg=muxcfg))
diamond.run(device, "work/ccu2.ncl")
bs = pytrellis.Bitstream.read_bit("work/ccu2.bit")
chip = bs.deserialise_chip()
return chip.tiles
def run_get_tiles(dir, io_type="LVCMOS33", loc="PB11D"):
with open("io_params_template.v", "r") as inf:
with open("work/io_params.v", "w") as ouf:
ouf.write(
Template(inf.read()).substitute(dir=dir,
io_type="\"" + io_type + "\"",
loc="\"" + loc + "\""))
diamond.run(device, "work/io_params.v")
bs = pytrellis.Bitstream.read_bit("work/io_params.bit")
chip = bs.deserialise_chip()
return chip.tiles
def run_get_tiles(mux_driver, sink):
route = ""
if mux_driver != "":
route = "route\n\t\t\t" + mux_driver + "." + sink + ";"
with open("center_mux_template.ncl", "r") as inf:
with open("work/center_mux.ncl", "w") as ouf:
ouf.write(Template(inf.read()).substitute(route=route))
diamond.run(device, "work/center_mux.ncl")
bs = pytrellis.Bitstream.read_bit("work/center_mux.bit")
chip = bs.deserialise_chip()
return chip.tiles
def main():
shutil.rmtree("work_tilegrid", ignore_errors=True)
os.mkdir("work_tilegrid")
shutil.copy(
path.join(database.get_trellis_root(), "minitests", "wire", "wire.v"),
"work_tilegrid/wire.v")
for family in sorted(devices.families.keys()):
for device in sorted(devices.families[family]["devices"].keys()):
diamond.run(device, "work_tilegrid/wire.v")
output_file = path.join(database.get_db_subdir(family, device),
"tilegrid.json")
extract_tilegrid.main([
"extract_tilegrid", "work_tilegrid/wire.tmp/output.test",
output_file
])
def run_get_bits(init_bits):
sop_terms = []
for i in range(16):
if init_bits & (1 << i) != 0:
p_terms = []
for j in range(4):
if i & (1 << j) != 0:
p_terms.append(lut_inputs[j])
else:
p_terms.append("~" + lut_inputs[j])
sop_terms.append("({})".format("*".join(p_terms)))
if len(sop_terms) == 0:
lut_func = "0"
else:
lut_func = "+".join(sop_terms)
with open("lut_init_template.ncl", "r") as inf:
with open("work/lut_init.ncl", "w") as ouf:
ouf.write(Template(inf.read()).substitute(lut_func=lut_func))
diamond.run(device, "work/lut_init.ncl")
bs = pytrellis.Bitstream.read_bit("work/lut_init.bit")
chip = bs.deserialise_chip()
tile = chip.tiles["R2C2"]
return tile.cram
timings = []
for i in range(0, 60, 2):
row = 7 + i
nets = ["R{}C10_F5_SLICE".format(row), "R{}C10_F5".format(row)]
for j in range(0, i, 2):
nets.append("R{}C10_V02N0701".format(row - (j + 1)))
nets.append("R7C10_A0")
nets.append("R7C10_A0_SLICE")
route = []
for k in range(len(nets) - 1):
route.append("{}.{}".format(nets[k], nets[k + 1]))
route_txt = ", \n".join(route)
desfile = "distance_{}.ncl".format(i)
with open(desfile, "w") as ouf:
ouf.write(Template(ncl).substitute(row=row, route=route_txt))
diamond.run(device, desfile)
with open(desfile.replace("ncl", "twr"), "r") as twrf:
for line in twrf:
m = re.match(r"\s+([0-9.]+)ns\s+R\d+C\d+C\.F1 to R7C10A\.A0\s+",
line)
if m:
timings.append(float(m.group(1)))
print("")
print("")
print("Length\tDelay")
for i in range(len(timings)):
print("{}\t{}".format(2 * i, timings[i]))