def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) cocotb.start_soon(Clock(dut.clk, 10, units="ns").start()) # AXI RAM self.axi_ram = AxiRam(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, size=2**16) # DMA RAM self.dma_ram = PsdpRam(PsdpRamBus.from_prefix(dut, "ram"), dut.clk, dut.rst, size=2**16) # Control self.read_desc_source = DescSource( DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst) self.read_desc_status_sink = DescStatusSink( DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst) self.write_desc_source = DescSource( DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst) self.write_desc_status_sink = DescStatusSink( DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst) dut.read_enable.setimmediatevalue(0) dut.write_enable.setimmediatevalue(0)
def __init__(self, dut): self.dut = dut self.log = logging.getLogger("cocotb.tb") self.log.setLevel(logging.DEBUG) # PCIe self.rc = RootComplex() self.dev = UltraScalePlusPcieDevice( # configuration options pcie_generation=3, # pcie_link_width=2, # user_clk_frequency=250e6, alignment="dword", cq_cc_straddle=False, rq_rc_straddle=False, rc_4tlp_straddle=False, enable_pf1=False, enable_client_tag=True, enable_extended_tag=False, enable_parity=False, enable_rx_msg_interface=False, enable_sriov=False, enable_extended_configuration=False, enable_pf0_msi=True, enable_pf1_msi=False, # signals user_clk=dut.clk, user_reset=dut.rst, rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"), pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0, pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0, pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1, pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1, rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"), cfg_max_payload=dut.max_payload_size, cfg_max_read_req=dut.max_read_request_size, cfg_fc_sel=0b100, cfg_fc_ph=dut.pcie_tx_fc_ph_av, cfg_fc_pd=dut.pcie_tx_fc_pd_av, cfg_fc_nph=dut.pcie_tx_fc_nph_av, ) self.dev.log.setLevel(logging.DEBUG) self.rc.make_port().connect(self.dev) # DMA RAM self.dma_ram = PsdpRam(PsdpRamBus.from_prefix(dut, "ram"), dut.clk, dut.rst, size=2**16) # Control self.read_desc_source = DescSource( DescBus.from_prefix(dut, "s_axis_read_desc"), dut.clk, dut.rst) self.read_desc_status_sink = DescStatusSink( DescStatusBus.from_prefix(dut, "m_axis_read_desc_status"), dut.clk, dut.rst) self.write_desc_source = DescSource( DescBus.from_prefix(dut, "s_axis_write_desc"), dut.clk, dut.rst) self.write_desc_status_sink = DescStatusSink( DescStatusBus.from_prefix(dut, "m_axis_write_desc_status"), dut.clk, dut.rst) dut.requester_id.setimmediatevalue(0) dut.requester_id_enable.setimmediatevalue(0) dut.ext_tag_enable.setimmediatevalue(0) dut.read_enable.setimmediatevalue(0) dut.write_enable.setimmediatevalue(0) # monitor error outputs self.status_error_cor_asserted = False self.status_error_uncor_asserted = False cocotb.fork(self._run_monitor_status_error_cor()) cocotb.fork(self._run_monitor_status_error_uncor())