def dp_system(mux_dp_bus, reset, clock): bg0_dp_bus = DPBus(data_w=2) bg1_dp_bus = DPBus(data_w=2) bg0_dp_bus.ready = True bg1_dp_bus.ready = True bg0 = dp_block_gen(bg0_dp_bus, clock, reset, g_count_max=4) bg1 = dp_block_gen(bg1_dp_bus, clock, reset, g_count_max=4) my_mux = dp_mux(mux_dp_bus, bg0_dp_bus, bg1_dp_bus) return bg0, bg1, my_mux
def dp_system(mux_src_out, reset, clock): mux_sel = Signal(bool(0)) bg0_src_in = DP_SISO() bg1_src_in = DP_SISO() bg0_src_in.ready = 1 bg1_src_in.ready = 1 bg0_src_out = DP_SOSI(data_w=2) bg1_src_out = DP_SOSI(data_w=2) bg0 = dp_block_gen(bg0_src_out, bg0_src_in, clock, reset, g_count_max=4) bg1 = dp_block_gen(bg1_src_out, bg1_src_in, clock, reset, g_count_max=4) my_mux = dp_mux(mux_src_out, bg0_src_out, bg1_src_out, mux_sel) return bg0, bg1, my_mux
#from myhdl import Signal, Simulation, delay, always_comb from dp_stream_pkg import * from dp_mux import dp_mux from random import randrange dp_mux_src_out, dp_mux_snk_in_a, dp_mux_snk_in_b = [DP_SOSI(data_w=4) for i in range(3)] sel = Signal(0) u_dp_mux = dp_mux(dp_mux_src_out, dp_mux_snk_in_a, dp_mux_snk_in_b, sel) def test(): print "z a b sel" for i in range(8): dp_mux_snk_in_a.data.next, dp_mux_snk_in_b.data.next, sel.next = randrange(8), randrange(8), randrange(2) yield delay(10) print "%s %s %s %s" % (dp_mux_src_out.data, dp_mux_snk_in_a.data, dp_mux_snk_in_b.data, sel) test_1 = test() sim = Simulation(u_dp_mux, test_1) sim.run()