def ameth_l(self, bytez, offset, tsize, prefixes, operflags):
reg = self.ROFFSETSIMD
imm = e_bits.parsebytes(bytez, offset, 1, sign=False)
idx = (imm & 0xF0) >> 4
if not (prefixes & PREFIX_VEX_L) or operflags & OP_NOVEXL:
reg += e_i386.RMETA_LOW128
return (1, i386RegOper(reg + idx, tsize))
def ameth_0(self, operflags, operval, tsize, prefixes):
# o = e_i386.i386Disasm.ameth_0(self, operflags, operval, tsize, prefixes)
if operflags & opcode86.OP_REG:
# for handling meta registers embedded in opcodes
if prefixes & PREFIX_OP_SIZE:
if self._dis_regctx.isMetaRegister(operval):
operval = (operval & RMETA_NMASK) | META_SIZES[tsize]
else:
operval |= META_SIZES[tsize]
width = self._dis_regctx.getRegisterWidth(operval) / 8
o = i386RegOper(operval, width)
elif operflags & opcode86.OP_IMM:
o = i386ImmOper(operval, tsize)
else:
raise Exception("Unknown ameth_0! operflags: 0x%.8x" % operflags)
# If it has a builtin register, we need to check for bump prefix
if prefixes & PREFIX_REX_W and isinstance(o, e_i386.i386RegOper):
o.reg &= 0xffff
if prefixes & PREFIX_REX_B and isinstance(o, e_i386.i386RegOper):
# the optable entries for AH with REX_B is terribly unhelpful.
if o.reg & e_i386.RMETA_HIGH8 == e_i386.RMETA_HIGH8:
o.reg &= REX_HIGH_DROP
o.reg += 4
if not (operflags & e_i386_const.OP_NOREXB):
o.reg += REX_BUMP
return o
def ameth_h(self, bytez, offset, tsize, prefixes, operflags):
osize = 0
vvvv = (prefixes >> VEX_V_SHIFT) & 0xf
offset = self.ROFFSETSIMD
if not (prefixes & PREFIX_VEX_L):
vvvv |= e_i386.RMETA_LOW128
oper = i386RegOper(offset + vvvv, tsize)
return osize, oper
def ameth_h(self, bytez, offset, tsize, prefixes, operflags):
osize = 0
vvvv = (prefixes >> VEX_V_SHIFT) & 0xf
offset = self.ROFFSETSIMD
if not (prefixes & PREFIX_VEX_L):
vvvv |= e_i386.RMETA_LOW128
oper = i386RegOper(offset + vvvv, tsize)
return osize, oper
def ameth_b(self, bytez, offset, tsize, prefixes, operflags):
osize = 0
oper = 0
vvvv = (prefixes >> VEX_V_SHIFT) & 0xf
oper = i386RegOper(vvvv, tsize)
# TODO: Disallowing reg_rip is probably wrong
if oper.tsize == 4:
oper.reg |= RMETA_LOW32
return osize, oper
def ameth_l(self, bytez, offset, tsize, prefixes, operflags):
osize = 1
imm = e_bits.parsebytes(bytez, offset, 1)
vvvv = (imm >> 4)
offset = self.ROFFSETSIMD
if not (prefixes & PREFIX_VEX_L):
vvvv |= e_i386.RMETA_LOW128
oper = i386RegOper(offset + vvvv, tsize)
return osize, oper
def ameth_l(self, bytez, offset, tsize, prefixes, operflags):
osize = 1
imm = e_bits.parsebytes(bytez, offset, 1)
vvvv = (imm >> 4)
offset = self.ROFFSETSIMD
if not (prefixes & PREFIX_VEX_L):
vvvv |= e_i386.RMETA_LOW128
oper = i386RegOper(offset + vvvv, tsize)
return osize, oper
def ameth_w(self, bytez, offset, tsize, prefixes, operflags):
mod,reg,rm = self.parse_modrm(ord(bytez[offset]))
if mod == 3:
vvvv = self.ROFFSETSIMD
if not (prefixes & PREFIX_VEX_L):
vvvv |= e_i386.RMETA_LOW128
osize, oper = (1, i386RegOper(rm + vvvv, tsize))
else:
osize, oper = self.extended_parse_modrm(bytez, offset, tsize, prefixes=prefixes)
if oper.tsize == 32 and not (prefixes & PREFIX_VEX_L):
oper.tsize = 16
self._dis_rex_exmodrm(oper, prefixes, operflags)
return osize,oper
def ameth_b(self, bytez, offset, tsize, prefixes, operflags):
osize = 0
oper = 0
vvvv = (prefixes >> VEX_V_SHIFT) & 0xf
oper = i386RegOper(vvvv, tsize)
return osize, oper
def ameth_b(self, bytez, offset, tsize, prefixes, operflags):
osize = 0
oper = 0
vvvv = (prefixes >> VEX_V_SHIFT) & 0xf
oper = i386RegOper(vvvv, tsize)
return osize, oper
