def main(isCold=False):
if (isCold != True) and (isCold != False):
print(
"Invalid input temperature parameter, will assume room temperature"
)
isCold = False
#initialize board
femb_config = CONFIG()
femb_config.COLD = isCold
#femb_config.COLD = True
femb_config.enableTest = 1
femb_config.isExternalClock = True
femb_config.is1MHzSAMPLERATE = False #COOL
print("\n")
print("Running test setup initialization process")
print("Configuration parameters:")
femb_config.printParameters()
#initialize readout to known working state
print("Initializing board")
initStatus = femb_config.initBoard()
if initStatus == False:
#setup in bad state
completeFailure()
return
asicStatus = [1, 1, 1, 1]
for asic in [0, 1, 2, 3]:
#for asic in [2]:
asicNum = int(asic)
if (asicNum < 0) or (asicNum > 3):
continue
print("\n")
print("Try initializing ASIC ", asicNum)
initStatus = femb_config.initAsic(asicNum)
if initStatus == False:
print("Could not initialize ASIC ", asicNum)
asicStatus[asicNum] = 0
#femb_config.printSyncRegister()
#use external pulser
femb_config.setFPGADac(0, 1, 0, 0) # write regs 4 and 5
#ideally check if function generator exists here...
#initialize funciton generator
funcgen = Keysight_33600A("/dev/usbtmc0", 1) #hardcoded to usbtmc0
xLow = 0.1
xHigh = 1.3
offsetV = (xLow + xHigh) * 0.5
amplitudeV = (xHigh - xLow) * 0.5
freq = 20173
funcgen.startSin(freq, amplitudeV, offsetV)
#setup is in good state
totalVictory()
print("ASIC STATUS", "\t", asicStatus)
def __init__(self,
datadir="data",
outlabel="funcgenMeasurement",
asicnum=0,
doReconfig=True,
doLongRamp=False,
isExternalClock=True,
is1MHzSAMPLERATE=True,
isCold=False):
#set internal variables
self.datadir = datadir
self.outlabel = outlabel + str("_asic_") + str(asicnum)
self.outpathlabel = os.path.join(self.datadir, self.outlabel)
self.asicnum = int(asicnum)
print("Test type\t" + str(self.outlabel))
print("Data path\t" + str(datadir))
print("ASIC socket #\t" + str(self.asicnum))
#import femb_udp modules from femb_udp package
self.femb_config = CONFIG()
self.write_data = WRITE_DATA(datadir)
self.cppfr = CPP_FILE_RUNNER()
self.funcgen = Keysight_33600A("/dev/usbtmc0",
1) #hardcoded to usbtmc0
#set appropriate UDP packet size
self.write_data.femb.MAX_PACKET_SIZE = 8000 #should be larger than largest expected packet size
#set test module status variables
self.status_check_setup = 0
self.status_record_data = 0
self.status_do_analysis = 0
self.status_archive_results = 0
#assign input to test and config module internal variables
self.doReconfig = doReconfig
self.doLongRamp = doLongRamp
self.isExternalClock = isExternalClock
self.is1MHzSAMPLERATE = is1MHzSAMPLERATE
self.isCold = isCold
self.femb_config.isExternalClock = self.isExternalClock #False = internal monostable, True = external
self.femb_config.is1MHzSAMPLERATE = self.is1MHzSAMPLERATE #False = 1MHz, True = 2MHz
self.femb_config.COLD = self.isCold
self.femb_config.enableTest = 1 # 0 = no test input, 1 = enabled
#define json output
self.jsondict = {'type': 'quadAdcTest_funcgen'}
#self.jsondict['version'] = '1.0'
self.jsondict['timestamp'] = str(self.write_data.date)
self.jsondict['asicnum'] = str(self.asicnum)
self.jsondict['doreconfig'] = str(self.doReconfig)
self.jsondict['extclock'] = str(self.isExternalClock)
self.jsondict['is1MHz'] = str(self.is1MHzSAMPLERATE)
self.jsondict['iscold'] = str(self.isCold)
def main():
femb_config = CONFIG()
#initialize readout to known working state
print("Turn off ASICs")
femb_config.turnOffAsics()
#ideally check if function generator exists here...
#initialize funciton generator
funcgen = Keysight_33600A("/dev/usbtmc0", 1) #hardcoded to usbtmc0
funcgen.stop()
def main():
#initialize board
femb_config = CONFIG()
#femb_config.isExternalClock = True
#femb_config.is1MHzSAMPLERATE = False #COOL
#initialize readout to known working state
print("Initializing board")
initStatus = femb_config.initBoard()
if initStatus == False :
#setup in bad state
completeFailure()
return
asicStatus = [1,1,1]
initStatus = femb_config.initAsic(0)
if initStatus == False :
print( "Could not initialize ASIC ", 0 )
asicStatus[0] = 0
initStatus = femb_config.initAsic(1)
if initStatus == False :
print( "Could not initialize ASIC ", 1 )
asicStatus[1] = 0
initStatus = femb_config.initAsic(2)
if initStatus == False :
print( "Could not initialize ASIC ", 2 )
asicStatus[2] = 0
#use external pulser
femb_config.setFPGADac(0,1,0,0) # write regs 4 and 5
#ideally check if function generator exists here...
#initialize funciton generator
funcgen = Keysight_33600A("/dev/usbtmc0",1) #hardcoded to usbtmc0
xLow = 0.1
xHigh = 1.3
offsetV = (xLow + xHigh)*0.5
amplitudeV = (xHigh - xLow)*0.5
freq = 20173
funcgen.startSin(freq,amplitudeV,offsetV)
#setup is in good state
totalVictory()
print("ASIC STATUS","\t",asicStatus)
def __init__(self,exitOnError=True):
super().__init__(exitOnError=exitOnError)
#declare board specific registers
self.FEMB_VER = "adctestP1single"
self.REG_RESET = 0
self.REG_ASIC_RESET = 1
self.REG_ASIC_SPIPROG = 2
self.REG_SEL_CH = 7
self.REG_HS = 17
self.REG_FESPI_BASE = 0x250 # 592 in decimal
self.REG_ADCSPI_BASE = 0x200 # 512 in decimal
self.REG_FESPI_RDBACK_BASE = 0x278 # 632 in decimal
self.REG_ADCSPI_RDBACK_BASE = 0x228 # 552 in decimal
self.REG_LATCHLOC1_4 = 4
self.REG_LATCHLOC5_8 = 14
self.REG_CLKPHASE = 6
self.REG_LATCHLOC1_4_data = 0x6
self.REG_LATCHLOC5_8_data = 0x0
self.REG_CLKPHASE_data = 0xfffc0000
self.REG_LATCHLOC1_4_data_1MHz = 0x5
self.REG_LATCHLOC5_8_data_1MHz = 0x0
self.REG_CLKPHASE_data_1MHz = 0xffff0000
self.REG_LATCHLOC1_4_data_cold = 0x6
self.REG_LATCHLOC5_8_data_cold = 0x0
self.REG_CLKPHASE_data_cold = 0xfffc0000
self.REG_LATCHLOC1_4_data_1MHz_cold = 0x4
self.REG_LATCHLOC5_8_data_1MHz_cold = 0x0
self.REG_CLKPHASE_data_1MHz_cold = 0xfffc0001
self.ADC_TESTPATTERN = [0x12, 0x345, 0x678, 0xf1f, 0xad, 0xc01, 0x234, 0x567, 0x89d, 0xeca, 0xff0, 0x123, 0x456, 0x789, 0xabc, 0xdef]
##################################
# external clock control registers
##################################
self.FPGA_FREQ_MHZ = 200 # frequency of FPGA clock in MHz
self.REG_EXTCLK_RD_EN_OFF = 23
self.REG_EXTCLK_ADC_OFF = 21
self.REG_EXTCLK_ADC_WID = 22
self.REG_EXTCLK_MSB_OFF = 25
self.REG_EXTCLK_MSB_WID = 26
self.REG_EXTCLK_PERIOD = 20
self.REG_EXTCLK_LSB_FC_WID2 = 32
self.REG_EXTCLK_LSB_FC_OFF1 = 29
self.REG_EXTCLK_RD_EN_WID = 24
self.REG_EXTCLK_LSB_FC_WID1 = 30
self.REG_EXTCLK_LSB_FC_OFF2 = 31
self.REG_EXTCLK_LSB_S_WID = 28
self.REG_EXTCLK_LSB_S_OFF = 27
self.REG_EXTCLK_INV = 33
##################################
##################################
self.NASICS = 1
self.FUNCGENINTER = Keysight_33600A("/dev/usbtmc1",1)
self.POWERSUPPLYINTER = RigolDP800("/dev/usbtmc0",["CH2","CH3","CH1"]) # turn on CH2 first
self.F2DEFAULT = 0
self.CLKDEFAULT = "fifo"
## Firmware update related variables
self.FIRMWAREPATH2MHZ = "/home/oper/Documents/CarlosForkedRepo/femb_python/femb_python/test_measurements/adc_clock_test/code/S_SKT_ADC_CHP_TST.sof"
#self.FIRMWAREPATH1MHZ = "/opt/sw/releases/femb_firmware-0.1.0/adc_tester/S7_1M_SBND_FPGA.sof"
self.FIRMWAREPROGEXE = "/opt/sw/intelFPGA/17.0/qprogrammer/bin/quartus_pgm"
#self.FIRMWAREPROGCABLE = "USB-Blaster"
self.FIRMWAREPROGCABLE = "USB-BlasterII"
self.SAMPLERATE = 2e6
#initialize FEMB UDP object
self.femb = FEMB_UDP()
self.adc_reg = ADC_ASIC_REG_MAPPING()
def __init__(self, exitOnError=True):
super().__init__(exitOnError=exitOnError)
#declare board specific registers
self.FEMB_VER = "adctestP1quad"
self.REG_RESET = 0 # bit 0 system, 1 reg, 2 alg, 3 udp
self.REG_PWR_CTRL = 1 # bit 0-3 pwr, 8-15 blue LEDs near buttons
self.REG_ASIC_SPIPROG_RESET = 2 # bit 0 FE SPI, 1 ADC SPI, 4 FE ASIC RESET, 5 ADC ASIC RESET, 6 SOFT ADC RESET & SPI readback check
# I zero out REG_ASIC_SPIPROG_RESET a lot because only transitions from 0 to 1 do anything
self.REG_SEL_CH = 3 # bit 0-7 chip, 8-15 channel, 31 WIB mode
self.REG_DAC1 = 4 # bit 0-15 DAC val, 16-19 tp mode select, 31 set dac
self.REG_DAC2 = 5 # bit 0-15 tp period, 16-31 tp shift
self.REG_FPGA_TST_PATT = 6 # bit 0-11 tst patt, 16 enable
self.REG_ADC_CLK = 7 # bit 0-3 clk phase, 8 clk speed sel
self.REG_LATCHLOC = 8 # bit 0-7 ADC1, 8-15 ADC2, 16-23 ADC3, 24-31 ADC4
self.REG_STOP_ADC = 9 # bit 0 stops sending convert, read ADC HEADER redundant with reg 2
self.REG_UDP_FRAME_SIZE = 63 # bits 0-11
self.REG_FIRMWARE_VERSION = 0xFF # 255 in decimal
self.CONFIG_FIRMWARE_VERSION = 259 # this file is written for this
self.REG_LATCHLOC_data_2MHz = 0x02020202
self.REG_LATCHLOC_data_1MHz = 0x0
self.REG_LATCHLOC_data_2MHz_cold = 0x02020202
self.REG_LATCHLOC_data_1MHz_cold = 0x0
self.REG_CLKPHASE_data_2MHz = 0x4
self.REG_CLKPHASE_data_1MHz = 0x0
self.REG_CLKPHASE_data_2MHz_cold = 0x4
self.REG_CLKPHASE_data_1MHz_cold = 0x0
self.DEFAULT_FPGA_TST_PATTERN = 0x12
self.ADC_TESTPATTERN = [
0x12, 0x345, 0x678, 0xf1f, 0xad, 0xc01, 0x234, 0x567, 0x89d, 0xeca,
0xff0, 0x123, 0x456, 0x789, 0xabc, 0xdef
]
# registers 64-88 are SPI to ASICs
# 88 is last register besides 255 which is firmware version
self.REG_FESPI_BASE = 84 # this configures all FE ASICs
self.REG_ADCSPI_BASES = [64, 69, 74, 79] # for each chip
self.REG_EXTCLK_INV = 10
self.REG_EXTCLK_BASES = [11, 20, 29, 38] # for each chip
self.FPGA_FREQ_MHZ = 200 # frequency of FPGA clock in MHz
self.REG_PLL_BASES = [17, 26, 35, 44] # for each chip
self.NASICS = 4
#self.FUNCGENINTER = DummyFuncGen("","")
self.FUNCGENINTER = Keysight_33600A("/dev/usbtmc0", 1)
self.POWERSUPPLYINTER = DummyPowerSupply("", "")
self.F2DEFAULT = 0
self.CLKDEFAULT = "fifo"
self.SAMPLERATE = 2e6
#initialize FEMB UDP object
self.femb = FEMB_UDP()
self.adc_regs = []
for i in range(self.NASICS):
self.adc_regs.append(ADC_ASIC_REG_MAPPING())
#self.defaultConfigFunc = lambda: self.configAdcAsic()
self.defaultConfigFunc = lambda: self.configAdcAsic(clockMonostable=
True)
def __init__(self, exitOnError=True):
super().__init__(exitOnError=exitOnError)
#declare board specific registers
self.FEMB_VER = "adctestP1single_clkTest"
self.REG_RESET = 0 # checked (good)
self.REG_ASIC_RESET = 1 # checked (good)
self.REG_ASIC_SPIPROG = 2 # checked (good)
self.REG_SEL_CH = 7 # checked (good)
self.REG_HS = 17 # checked (wtf)
self.REG_ADCSPI_BASE = 0x200 # 512 in decimal updated (good)
self.REG_ADCSPI_RDBACK_BASE = 0x250 # 592 in decimal updated (good)
self.REG_LATCHLOC1_4 = 4 # checked (good) latch_loc0(7 downto 0)
self.REG_CLKPHASE = 6 # checked (good) is it the same as phase control?
self.REG_LATCHLOC1_4_data_1MHz = 0x6060604 # update
self.REG_CLKPHASE_data_1MHz = 0x14 # update
self.REG_LATCHLOC1_4_data_2MHz = 0x6060604 # update
self.REG_CLKPHASE_data_2MHz = 0x14 # update
self.ADC_TESTPATTERN = [
0x12, 0x345, 0x678, 0xf1f, 0xad, 0xc01, 0x234, 0x567, 0x89d, 0xeca,
0xff0, 0x123, 0x456, 0x789, 0xabc, 0xdef
]
##################################
# external clock control registers
##################################
self.FPGA_FREQ_MHZ = 200 # frequency of FPGA clock in MHz
self.REG_EXTCLK_PERIOD = 20
self.REG_EXTCLK_INV = 21 # checked (good)
self.REG_EXTCLK_RST_OFF = 22 # checked (good)
self.REG_EXTCLK_RST_WID = 23 # checked (good)
self.REG_EXTCLK_READ_OFF = 24 # checked (good)
self.REG_EXTCLK_READ_WID = 25 # checked (good)
self.REG_EXTCLK_IDXM_OFF = 26 # checked (good)
self.REG_EXTCLK_IDXM_WID = 27 # checked (good)
self.REG_EXTCLK_IDXL_OFF = 28 # checked (good)
self.REG_EXTCLK_IDXL_WID = 29 # checked (good)
self.REG_EXTCLK_IDL1_OFF = 30 # checked (good)
self.REG_EXTCLK_IDL1_WID = 31 # checked (good)
self.REG_EXTCLK_IDL2_OFF = 32 # checked (good)
self.REG_EXTCLK_IDL2_WID = 33 # checked (good)
self.REG_EXTCLK_PLL_STEP0 = 34 # checked (good)
self.REG_EXTCLK_PLL_STEP1 = 35 # checked (good)
self.REG_EXTCLK_PLL_STEP2 = 36 # checked (good)
self.EC_RST_OFF = 0
self.EC_RST_WID = 50
self.EC_RD_OFF = 490
self.EC_RD_WID = 10
self.EC_IDXM_OFF = 210
self.EC_IDXM_WID = 285
self.EC_IDXL_OFF = 490
self.EC_IDXL_WID = 10
self.EC_IDL1_OFF = 50
self.EC_IDL1_WID = 190
self.EC_IDL2_OFF = 490
self.EC_IDL2_WID = 10
self.EC_PLL_STEP0 = 0x0014000d #0x000b000f # found in labview
self.EC_PLL_STEP1 = 0x00120006 #0x000e0008 # found in labview
self.EC_PLL_STEP2 = 0x80190009 # found in labview
self.inv_rst = True
self.inv_read = False
self.inv_idxm = False
self.inv_idxl = False
self.inv_idl = False
#self.inv_clk_dis=True
##################################
##################################
self.NASICS = 1
self.NCHNS = 16
self.FUNCGENINTER = Keysight_33600A("/dev/usbtmc1", 1)
self.POWERSUPPLYINTER = RigolDP800(
"/dev/usbtmc0", ["CH2", "CH3", "CH1"]) # turn on CH2 first
self.F2DEFAULT = 0
self.CLKDEFAULT = "fifo"
self.frame_size = 0x0efb
self.BPS = 13 #Bytes per sample
## Firmware update related variables
self.FIRMWAREVERSION = "A01"
self.FIRMWAREPATH2MHZ = "/home/oper/Documents/CarlosForkedRepo/femb_python/femb_python/test_measurements/adc_clk_tst/S_SKT_ADC_CHP_TST.sof"
self.FIRMWAREPATH1MHZ = "/home/oper/Documents/CarlosForkedRepo/femb_python/femb_python/test_measurements/adc_clk_tst/S_SKT_ADC_CHP_TST.sof"
self.FIRMWAREPROGEXE = "/opt/sw/intelFPGA/17.0/qprogrammer/bin/quartus_pgm"
#self.FIRMWAREPROGCABLE = "USB-Blaster"
self.FIRMWAREPROGCABLE = "USB-BlasterII"
self.SAMPLERATE = 2e6
#initialize FEMB UDP object
self.femb = FEMB_UDP()
self.adc_reg = ADC_ASIC_REG_MAPPING()
self.adc_reg_new = ADC_ASIC_REG_MAPPING_NEW()
self.femb_eh = FPGA_UDP()
self.PC_IP = self.femb_eh.PC_IP
self.FPGA_IP = self.femb_eh.FPGA_IP