def test_dataflow_partition_tlastmarker():
model = ModelWrapper(build_dir + "/test_dataflow_partition_create.onnx")
model_path = getCustomOp(model.graph.node[2]).get_nodeattr("model")
model = ModelWrapper(model_path)
model = model.transform(InsertTLastMarker())
assert model.graph.node[-1].op_type == "TLastMarker"
assert model.graph.node[-1].domain == "finn"
tl_node = getCustomOp(model.graph.node[-1])
assert tl_node.get_nodeattr("NumIters") == 1
assert tl_node.get_nodeattr("StreamWidth") == 320
assert tl_node.get_nodeattr("ElemWidth") == 32
model.save(build_dir + "/test_dataflow_partition_tlastmarker.onnx")
model = model.transform(InsertTLastMarker())
model.save(build_dir + "/test_dataflow_partition_tlastmarker2.onnx")
def test_end2end_tfc_w1a2_fold_and_tlastmarker():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_dataflow_model.onnx")
fc0 = model.graph.node[0]
fc1 = model.graph.node[1]
fc2 = model.graph.node[2]
fc3 = model.graph.node[3]
fc0w = getCustomOp(fc0)
fc1w = getCustomOp(fc1)
fc2w = getCustomOp(fc2)
fc3w = getCustomOp(fc3)
fc0w.set_nodeattr("inFIFODepth", 50)
fc0w.set_nodeattr("SIMD", 8)
fc0w.set_nodeattr("PE", 16)
fc0w.set_nodeattr("outFIFODepth", 4)
fc1w.set_nodeattr("SIMD", 16)
fc1w.set_nodeattr("PE", 16)
fc1w.set_nodeattr("outFIFODepth", 4)
fc2w.set_nodeattr("SIMD", 16)
fc2w.set_nodeattr("PE", 16)
fc2w.set_nodeattr("outFIFODepth", 4)
fc3w.set_nodeattr("SIMD", 16)
fc3w.set_nodeattr("PE", 10)
fc3w.set_nodeattr("outFIFODepth", 50)
model = model.transform(InsertTLastMarker())
model.save(build_dir + "/end2end_tfc_w1a2_folded.onnx")
def test_end2end_cnv_w1a1_fold_and_tlastmarker():
model = ModelWrapper(build_dir + "/end2end_cnv_w1a1_dataflow_model.onnx")
fc_layers = model.get_nodes_by_op_type("StreamingFCLayer_Batch")
# each tuple is (PE, SIMD, in_fifo_depth) for a layer
folding = [
(16, 3, 128),
(32, 32, 128),
(16, 32, 128),
(16, 32, 128),
(4, 32, 81),
(1, 32, 2),
(1, 4, 2),
(1, 8, 128),
(5, 1, 3),
]
for fcl, (pe, simd, ififodepth) in zip(fc_layers, folding):
fcl_inst = getCustomOp(fcl)
fcl_inst.set_nodeattr("PE", pe)
fcl_inst.set_nodeattr("SIMD", simd)
fcl_inst.set_nodeattr("inFIFODepth", ififodepth)
swg_layers = model.get_nodes_by_op_type("ConvolutionInputGenerator")
for i in range(len(swg_layers)):
swg_inst = getCustomOp(swg_layers[i])
simd = folding[i][1]
swg_inst.set_nodeattr("SIMD", simd)
model = model.transform(InsertDWC())
model = model.transform(InsertFIFO())
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(AnnotateResources("estimate"))
model.save(build_dir + "/end2end_cnv_w1a1_folded.onnx")
def apply(self, model):
_check_vitis_envvars()
# first infer layouts
model = model.transform(InferDataLayouts())
# prepare at global level, then break up into kernels
prep_transforms = [
MakePYNQDriver(platform="alveo"),
InsertIODMA(512),
InsertDWC(),
]
for trn in prep_transforms:
model = model.transform(trn)
model = model.transform(GiveUniqueNodeNames())
model = model.transform(GiveReadableTensorNames())
model = model.transform(Floorplan(floorplan=self.floorplan_file))
model = model.transform(CreateDataflowPartition())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(GiveReadableTensorNames())
# Build each kernel individually
sdp_nodes = model.get_nodes_by_op_type("StreamingDataflowPartition")
for sdp_node in sdp_nodes:
sdp_node = getCustomOp(sdp_node)
dataflow_model_filename = sdp_node.get_nodeattr("model")
kernel_model = ModelWrapper(dataflow_model_filename)
kernel_model = kernel_model.transform(InsertFIFO())
kernel_model = kernel_model.transform(
InsertTLastMarker(both=True, external=False, dynamic=False))
kernel_model = kernel_model.transform(GiveUniqueNodeNames())
kernel_model.save(dataflow_model_filename)
kernel_model = kernel_model.transform(
PrepareIP(self.fpga_part, self.period_ns))
kernel_model = kernel_model.transform(HLSSynthIP())
kernel_model = kernel_model.transform(
CreateStitchedIP(self.fpga_part, self.period_ns,
sdp_node.onnx_node.name, True))
kernel_model = kernel_model.transform(
CreateVitisXO(sdp_node.onnx_node.name))
kernel_model.set_metadata_prop("platform", "alveo")
kernel_model.save(dataflow_model_filename)
# Assemble design from kernels
model = model.transform(
VitisLink(
self.platform,
round(1000 / self.period_ns),
strategy=self.strategy,
enable_debug=self.enable_debug,
))
# set platform attribute for correct remote execution
model.set_metadata_prop("platform", "alveo")
return (model, False)
def test_fpgadataflow_ipstitch_gen_model(): # exec_mode):
model = create_one_fc_model()
if model.graph.node[0].op_type == "StreamingDataflowPartition":
sdp_node = getCustomOp(model.graph.node[0])
assert sdp_node.__class__.__name__ == "StreamingDataflowPartition"
assert os.path.isfile(sdp_node.get_nodeattr("model"))
model = ModelWrapper(sdp_node.get_nodeattr("model"))
model.set_metadata_prop("exec_mode", "remote_pynq")
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(CodeGen_ipgen(test_fpga_part, 5))
model = model.transform(HLSSynth_IPGen())
assert model.graph.node[0].op_type == "StreamingFCLayer_Batch"
assert model.graph.node[-1].op_type == "TLastMarker"
model.save(ip_stitch_model_dir + "/test_fpgadataflow_ipstitch_gen_model.onnx")
def test_fpgadataflow_ipstitch_gen_model(mem_mode):
model = create_one_fc_model(mem_mode)
if model.graph.node[0].op_type == "StreamingDataflowPartition":
sdp_node = getCustomOp(model.graph.node[0])
assert sdp_node.__class__.__name__ == "StreamingDataflowPartition"
assert os.path.isfile(sdp_node.get_nodeattr("model"))
model = load_test_checkpoint_or_skip(sdp_node.get_nodeattr("model"))
model.set_metadata_prop("exec_mode", "remote_pynq")
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(PrepareIP(test_fpga_part, 5))
model = model.transform(HLSSynthIP())
assert model.graph.node[0].op_type == "StreamingFCLayer_Batch"
assert model.graph.node[-1].op_type == "TLastMarker"
model.save(ip_stitch_model_dir +
"/test_fpgadataflow_ipstitch_gen_model_%s.onnx" % mem_mode)
def test_fpgadataflow_fifo_rtlsim(Shape, folded_shape, depth, finn_dtype):
# generate input data
x = gen_finn_dt_tensor(finn_dtype, Shape)
input_dict = prepare_inputs(x, finn_dtype)
model = make_single_fifo_modelwrapper(Shape, depth, folded_shape, finn_dtype)
model = model.transform(SetExecMode("rtlsim"))
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(PrepareIP(test_fpga_part, target_clk_ns))
model = model.transform(HLSSynthIP())
model = model.transform(PrepareRTLSim())
y = oxe.execute_onnx(model, input_dict)["outp"]
assert (
y == x
).all(), """The output values are not the same as the
input values anymore."""
assert y.shape == tuple(Shape), """The output shape is incorrect."""
model = model.transform(ReplaceVerilogRelPaths())
model = model.transform(CreateStitchedIP(test_fpga_part))
model = model.transform(MakePYNQProject(test_pynq_board))
model = model.transform(SynthPYNQProject())
model = model.transform(MakePYNQDriver())
ip = os.environ["PYNQ_IP"]
username = os.getenv("PYNQ_USERNAME", "xilinx")
password = os.getenv("PYNQ_PASSWORD", "xilinx")
port = os.getenv("PYNQ_PORT", 22)
target_dir = os.getenv("PYNQ_TARGET_DIR", "/home/xilinx/finn")
model = model.transform(DeployToPYNQ(ip, port, username, password, target_dir))
res = throughput_test(model)
expected_dict = {}
expected_dict["runtime[ms]"] = []
expected_dict["throughput[images/s]"] = []
expected_dict["DRAM_in_bandwidth[Mb/s]"] = []
expected_dict["DRAM_out_bandwidth[Mb/s]"] = []
for key in expected_dict:
assert (
key in res
), """Throughput test not successful, no value for {}
in result dictionary""".format(
key
)
def test_end2end_tfc_w1a2_fold_and_tlastmarker():
model = ModelWrapper(build_dir + "/end2end_tfc_w1a2_dataflow_model.onnx")
fc_layers = model.get_nodes_by_op_type("StreamingFCLayer_Batch")
# (PE, SIMD, in_fifo_depth, out_fifo_depth, ramstyle) for each layer
config = [
(16, 49, 16, 64, "block"),
(8, 8, 64, 64, "auto"),
(8, 8, 64, 64, "auto"),
(10, 8, 64, 10, "distributed"),
]
for fcl, (pe, simd, ififo, ofifo, ramstyle) in zip(fc_layers, config):
fcl_inst = getCustomOp(fcl)
fcl_inst.set_nodeattr("PE", pe)
fcl_inst.set_nodeattr("SIMD", simd)
fcl_inst.set_nodeattr("inFIFODepth", ififo)
fcl_inst.set_nodeattr("outFIFODepth", ofifo)
fcl_inst.set_nodeattr("ram_style", ramstyle)
model = model.transform(InsertDWC())
model = model.transform(InsertFIFO())
model = model.transform(InsertTLastMarker())
model = model.transform(GiveUniqueNodeNames())
model = model.transform(AnnotateResources("estimate"))
model.save(build_dir + "/end2end_tfc_w1a2_folded.onnx")