def openComm(config): argList = getArgs() handle = fl.FLHandle() try: fpga_vid_pid_did = argList['fpga_vid_pid_did'] try: handle = fl.flOpen(fpga_vid_pid_did) except fl.FLException as ex: fpga_vid_pid = argList['fpga_vid_pid'] fl.flLoadStandardFirmware(fpga_vid_pid, fpga_vid_pid_did) #might need to add delay here if not fl.flAwaitDevice(fpga_vid_pid, 10000): raise fl.FLException('FPGALink device did not renumerate properly') handle = fl.flOpen(fpga_vid_pid_did) isNeroCapable = fl.flIsNeroCapable(handle) isCommCapable = fl.flIsCommCapable(handle, 1) fl.flSelectConduit(handle, 1) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) return (fpga, handle, Optimizer(handle, fpga, config)) else: return None #open comm failed
def initComTest(self): """ Test intial connection capabilities to FPGA board over USB. Returns: results(list): list of strings representing reports of passed and failed tests. """ results = [] fl.flInitialise(self.debug_level) #initializes library if fl.flIsDeviceAvailable(self.vid_pid_did): #checks if fpga is available results.append('P','USB bus with: ', self.vid_pid_did,' was found.') try: handle = fl.flOpen(self.vid_pid_did) #opens connection to FPGA board results.append('P','Successfully opened connection to FPGA board.') if fl.flIsNeroCapable(handle): #checks if device is Nero capable results.append('P', 'Device is Nero capable.') else: results.append('F', 'Device is not Nero capable.') if fl.flIsCommCapable(handle, self.conduit): #checks if FPGA board is capable of communication results.append('P','FPGA board supports functions: flIsFPGARunning(), flReadChannel(), flWriteChannel(), flSetAsyncWriteChunkSize(), flWriteChannelAsync(), flFlushAsyncWrites(), \c flAwaitAsyncWrites(), \c flReadChannelAsyncSubmit(),flReadChannelAsyncAwait().') try: fl.flSelectConduit(handle, self.conduit) #selects given conduit results.append('P','Selected conduit ', self.conduit) if fl.flIsFPGARunning(handle): #checks if board is ready to acccept commands results.append('P','FPGA board is ready to accept commands.') except: results.append('F','Conduit was out of range or device did not respond.') else: results.append('F','FPGA board cannot communicate.') fl.flClose(handle) #closes connection to FPGA board to avoid errors results.append('P','Connection to the FPGA board was closed.') except: results.append('F','Connection to FPGA board failed.') else: results.append('F','The VID:PID:DID ', self.vid_pid_did,' is invalid or no USB buses were found.') return results
def main(): argList = get_args() print(argList) handle = fl.FLHandle() try: fl.flInitialise(0) vp = argList.v[0] print("Attempting to open connection to FPGALink device {}...".format( vp)) try: handle = fl.flOpen(vp) except fl.FLException as ex: handle = ids(vp, argList) if argList.c: isNeroCapable, isCommCapable = conduit_selection(int(argList.c[0])) else: isNeroCapable, isCommCapable = conduit_selection() jtag_chain(isNeroCapable, argList, vp, handle) configure(argList, isNeroCapable, handle, vp) if argList.f and not isCommCapable: raise fl.FLException( "Data file load requested but device at {} does not support CommFPGA" .format(vp)) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) if argList.ppm: M = int(eval(argList.ppm[0])) print("Setting PPM order to: ", M) fpga.setPPM_M(M) if argList.txdel: delay = int(eval(argList.txdel[0])) print("Setting transmitter loopback delay to %i (0x%X)" % (delay, delay)) fpga.setTXdelay(delay) if argList.dac: dacval = int(eval(argList.dac[0])) print("Setting DAC value to %i (0x%X)" % (dacval, dacval)) fpga.writeDAC(dacval) if argList.prbs: print("Enabling PRBS") fpga.usePRBS() else: print("Disabling PRBS") fpga.usePRBS(False) if argList.peak: obslength = float(argList.peak) print("Measuring peak power...") peakDAC = fpga.binSearchPeak(M, target=1.0 / M, obslength=obslength) print(" DAC = %i" % peakDAC) #alg testing goes here, but alg is not up to date!! opt_alg(argList, fpga) except fl.FLException as ex: print(ex) finally: fl.flClose(handle)
def main(): argList = get_args() print (argList) handle = fl.FLHandle() try: fl.flInitialise(0) vp = argList.v[0] print("Attempting to open connection to FPGALink device {}...".format(vp)) try: handle = fl.flOpen(vp) except fl.FLException as ex: handle = ids(vp, argList) # if ( argList.d ): # print("Configuring ports...") # rb = "{:0{}b}".format(fl.flMultiBitPortAccess(handle, argList.d[0]), 32) # print("Readback: 28 24 20 16 12 8 4 0\n {} {} {} {} {} {} {} {}".format( # rb[0:4], rb[4:8], rb[8:12], rb[12:16], rb[16:20], rb[20:24], rb[24:28], rb[28:32])) # fl.flSleep(100) if argList.c: isNeroCapable, isCommCapable = conduit_selection(int(argList.c[0])) else: isNeroCapable, isCommCapable = conduit_selection() jtag_chain(isNeroCapable, argList, vp, handle) configure(argList, isNeroCapable, handle, vp) if argList.f and not isCommCapable: raise fl.FLException("Data file load requested but device at {} does not support CommFPGA".format(vp)) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) # define channels writechannel = 0x02 statuschannel = 0x05 resetchannel = 0x08 if argList.ppm: M = int(eval(argList.ppm[0])) print ("Setting PPM order to",M) fpga.setPPM_M(M) writedelay,num_bytes,trackingbyte = fpga.setModulatorParams(M) if not argList.f: fpga.setTrackingMode(writechannel,trackingbyte,M) if argList.txdel: delay = int(eval(argList.txdel[0])) print ("Setting transmitter loopback delay to %i (0x%X)"%(delay,delay)) fpga.setTXdelay(delay) if argList.dac: dacval = int(eval(argList.dac[0])) print ("Setting DAC value to %i (0x%X)"%(dacval,dacval)) fpga.writeDAC(dacval) if argList.prbs: # dacval = int(eval(argList.dac[0])) # print ("Setting DAC value to %i (0x%X)"%(dacval,dacval)) print ("Enabling PRBS") fpga.usePRBS() else: print ("Disabling PRBS") fpga.usePRBS(False) if argList.peak: obslength = float(argList.peak) print ("Measuring peak power...") peakDAC = fpga.binSearchPeak(M,target=1.0/M,obslength=obslength) print (" DAC = %i"%peakDAC) if argList.ser: obslength = float(argList.ser) print ("Measuring slot error rate...") cycles,errors,ones,ser = fpga.measureSER(obslength=obslength) print (" cycles = 0x%-12X"%(cycles)) print (" errors = 0x%-12X"%(errors)) print (" ones = 0x%-12X target=0x%-12X"%(ones,cycles/M)) print (" SlotER = %e"%(ser)) data_to_write(argList, fpga, writechannel, resetchannel, statuschannel, writedelay, vp, M, num_bytes) except fl.FLException as ex: print(ex) finally: fl.flClose(handle)
def NODECTRLmain(): argList = get_args() handle = fl.FLHandle() try: fl.flInitialise(0) vp = argList.v[0] print("Attempting to open connection to FPGALink device {}...".format(vp)) try: handle = fl.flOpen(vp) except fl.FLException as ex: handle = ids(vp, argList) if argList.c: isNeroCapable, isCommCapable = conduit_selection(int(argList.c[0])) else: isNeroCapable, isCommCapable = conduit_selection() jtag_chain(isNeroCapable, argList, vp, handle) configure(argList, isNeroCapable, handle, vp) if argList.f and not isCommCapable: raise fl.FLException("Data file load requested but device at {} does not support CommFPGA".format(vp)) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) # define channels ##must update these channels writechannel = 0x02 statuschannel = 0x05 resetchannel = 0x08 writedelay,num_bytes,trackingbyte = fpga.setModulatorParams(M) if argList.ppm: M = int(eval(argList.ppm[0])) print ("Setting PPM order to: ",M) fpga.setPPM_M(M) if not argList.f: fpga.setTrackingMode(writechannel,trackingbyte,M) if argList.txdel: delay = int(eval(argList.txdel[0])) print ("Setting transmitter loopback delay to %i (0x%X)"%(delay,delay)) fpga.setTXdelay(delay) if argList.dac: dacval = int(eval(argList.dac[0])) print ("Setting DAC value to %i (0x%X)"%(dacval,dacval)) fpga.writeDAC(dacval) if argList.prbs: print ("Enabling PRBS") fpga.usePRBS() else: print ("Disabling PRBS") fpga.usePRBS(False) if argList.peak: obslength = float(argList.peak) print ("Measuring peak power...") peakDAC = fpga.binSearchPeak(M,target=1.0/M,obslength=obslength) print (" DAC = %i"%peakDAC) if argList.ser: obslength = float(argList.ser) print ("Measuring slot error rate...") cycles,errors,ones,ser = fpga.measureSER(obslength=obslength) print (" cycles = 0x%-12X"%(cycles)) print (" errors = 0x%-12X"%(errors)) print (" ones = 0x%-12X target=0x%-12X"%(ones,cycles/M)) print (" SlotER = %e"%(ser)) data_to_write(argList, fpga, writechannel, resetchannel, statuschannel, writedelay, vp, M, num_bytes) #alg testing goes here, but alg is not up to date!! #opt_alg(argList, fpga) except fl.FLException as ex: print(ex) finally: fl.flClose(handle)
def SPImain(): argList = get_args() handle = fl.FLHandle() try: fl.flInitialise(0) vp = argList.v[0] print("Attempting to open connection to FPGALink device {}...".format(vp)) try: handle = fl.flOpen(vp) except fl.FLException as ex: if argList.i: ivp = argList.i[0] print("Loading firmware into {}...".format(ivp)) fl.flLoadStandardFirmware(ivp, vp) mem_map = tester(ivp, vp) # Long delay for renumeration # TODO: fix this hack. The timeout value specified in flAwaitDevice() below doesn't seem to work time.sleep(3) print("Awaiting renumeration...") if not fl.flAwaitDevice(vp, 10000): raise fl.FLException("FPGALink device did not renumerate properly as {}".format(vp)) print("Attempting to open connection to FPGALink device {} again...".format(vp)) handle = fl.flOpen(vp) else: raise fl.FLException("Could not open FPGALink device at {} and no initial VID:PID was supplied".format(vp)) # if ( argList.d ): # print("Configuring ports...") # rb = "{:0{}b}".format(fl.flMultiBitPortAccess(handle, argList.d[0]), 32) # print("Readback: 28 24 20 16 12 8 4 0\n {} {} {} {} {} {} {} {}".format( # rb[0:4], rb[4:8], rb[8:12], rb[12:16], rb[16:20], rb[20:24], rb[24:28], rb[28:32])) # fl.flSleep(100) conduit = 1 if argList.c: conduit = int(argList.c[0]) isNeroCapable = fl.flIsNeroCapable(handle) isCommCapable = fl.flIsCommCapable(handle, conduit) fl.flSelectConduit(handle, conduit) if argList.f and not(isCommCapable): raise fl.FLException("Data file load requested but device at {} does not support CommFPGA".format(vp)) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) opt = Optimizer(handle, fpga) #Test setting LD Bias to 0.150A (channels 26, 27) #opt.setCurrent(0.150) #this section of code looks like setLaserCurrent() curr = 0.150 code = curr/(4.096*1.1*((1/6.81)+(1/16500)))*4096 first_byte, second_byte = opt.code2bytes(code) spi_data = [first_byte, second_byte] update_SPI(handle, [26,27], spi_data) #Test reading LD Bias (channels 64 and 65) rx_bias = read_SPI(handle, [mem_map.getAddress('CC3a'), mem_map.getAddress('CC3b')]) for r in rx_bias: print "Bias bytes read: ", r print (rx_bias[1]*256 + rx_bias[0])/4096 * (4.096*1.1*((1/6.81)+(1/16500))) #Test writing/reading to LD Temp #TODO Constants are estimated; may need to verify with vendor R_known = 10000 Vcc = 0.8 B = 3900 R_0 = 10000 T_0 = 25 #writing temp 35C T = 35 V_set = Vcc/(((m.exp(B/T)*(R_0 * m.exp(-B/T_0)))/R_known)+1) V_code = opt.voltage2code(V_set) #convert voltage to code fb, sb = opt.code2byte(V_code) #convert code to bytes update_SPI(handle, [mem_map.getAddress('LTSa'),mem_map.getAddress('LTSb')], [fb, sb]) #reading temp bytes__meas = read_SPI(handle, [mem_map.getAddress('LTMa'),mem_map.getAddress('LTMb')]) #read ADC value code_meas = bytes_meas[1]*256 + bytes_meas[0] #convert bytes to double V_meas = opt.code2voltage(code_meas) #convert ADC to voltage
# print("Readback: 28 24 20 16 12 8 4 0\n {} {} {} {} {} {} {} {}".format( # rb[0:4], rb[4:8], rb[8:12], rb[12:16], rb[16:20], rb[20:24], rb[24:28], rb[28:32])) # fl.flSleep(100) conduit = 1 if argList.c: conduit = int(argList.c[0]) isNeroCapable = fl.flIsNeroCapable(handle) isCommCapable = fl.flIsCommCapable(handle, conduit) fl.flSelectConduit(handle, conduit) if argList.f and not(isCommCapable): raise fl.FLException("Data file load requested but device at {} does not support CommFPGA".format(vp)) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) #Test setting LD Bias to 0.150A (channels 26, 27) curr = 0.150 code = curr/(4.096*1.1*((1/6.81)+(1/16500)))*4096 first_byte, second_byte = code2bytes(code) spi_data = [first_byte, second_byte] update_SPI(handle, [mem_map.getAddress('LCCa'),mem_map.getAddress('LCCb')], spi_data) #### #Test reading LD Bias (channels 64 and 65) rx_bias = read_SPI(handle, [100,101]) for r in rx_bias: print "Bias bytes read: ", r print (rx_bias[1]*256 + rx_bias[0])/4096 * (4.096*1.1*((1/6.81)+(1/16500))) #Test writing/reading to LD Temp #TODO Constants are estimated; may need to verify with vendor
def SPImain(): argList = getArgs() handle = fl.FLHandle() try: fl.flInitialise(0) vp = argList['fpga_vid_pid_did'] print("Attempting to open connection to FPGALink device {}...".format(vp)) try: handle = fl.flOpen(vp) except fl.FLException as ex: ivp = argList['fpga_vid_pid'] print("Loading firmware into {}...".format(ivp)) fl.flLoadStandardFirmware(ivp, vp) mem_map = mmap.Tester(ivp, vp) # Long delay for renumeration # TODO: fix this hack. The timeout value specified in flAwaitDevice() below doesn't seem to work time.sleep(3) print("Awaiting renumeration...") if not fl.flAwaitDevice(vp, 10000): raise fl.FLException("FPGALink device did not renumerate properly as {}".format(vp)) print("Attempting to open connection to FPGALink device {} again...".format(vp)) handle = fl.flOpen(vp) # if ( argList.d ): # print("Configuring ports...") # rb = "{:0{}b}".format(fl.flMultiBitPortAccess(handle, argList.d[0]), 32) # print("Readback: 28 24 20 16 12 8 4 0\n {} {} {} {} {} {} {} {}".format( # rb[0:4], rb[4:8], rb[8:12], rb[12:16], rb[16:20], rb[20:24], rb[24:28], rb[28:32])) # fl.flSleep(100) conduit = 1 isNeroCapable = fl.flIsNeroCapable(handle) isCommCapable = fl.flIsCommCapable(handle, conduit) fl.flSelectConduit(handle, conduit) if argList['dataToWrite'] != None and not(isCommCapable): raise fl.FLException("Data file load requested but device at {} does not support CommFPGA".format(vp)) if isCommCapable and fl.flIsFPGARunning(handle): fpga = NodeFPGA(handle) opt = Optimizer(handle, fpga) #Test setting LD Bias to 0.150A (channels 26, 27) #opt.setCurrent(0.150) #this section of code looks like setLaserCurrent() curr = 0.150 code = curr/(4.096*1.1*((1/6.81)+(1/16500)))*4096 first_byte, second_byte = opt.code2bytes(code) spi_data = [first_byte, second_byte] updateSPI(handle, [mem_map.getAddress('LCCa'), mem_map.getAddress('LCCb')], spi_data) #Test reading LD Bias (channels 64 and 65) rx_bias = readSPI(handle, [mem_map.getAddress('CC3a'), mem_map.getAddress('CC3b')]) for r in rx_bias: print ("Bias bytes read: ", r) print (rx_bias[1]*256 + rx_bias[0])/4096 * (4.096*1.1*((1/6.81)+(1/16500))) #Test writing/reading to LD Temp #TODO Constants are estimated; may need to verify with vendor R_known = 10000 Vcc = 0.8 B = 3900 R_0 = 10000 T_0 = 25 #writing temp 35C T = 35 V_set = Vcc/(((m.exp(B/T)*(R_0 * m.exp(-B/T_0)))/R_known)+1) V_code = opt.voltage2code(V_set) #convert voltage to code fb, sb = opt.code2byte(V_code) #convert code to bytes updateSPI(handle, [mem_map.getAddress('LTSa'),mem_map.getAddress('LTSb')], [fb, sb]) #reading temp bytes__meas = readSPI(handle, [mem_map.getAddress('LTMa'),mem_map.getAddress('LTMb')]) #read ADC value code_meas = bytes_meas[1]*256 + bytes_meas[0] #convert bytes to double V_meas = opt.code2voltage(code_meas) #convert ADC to voltage R_t = R_known * (Vcc/V_meas - 1) T = B/m.log(R_t/R_0 * m.exp(-B/T_0)) print ("Temp read: ", T) #Test reading from RTD A = 3.81e-3 #from datasheet B = -6.02e-7 #from datasheet R_t0 = 1000 T_bm = readSPI(handle, [mem_map.getAddress('TE1a'),mem_map.getAddress('TE1b')]) #temp code measured T_cm = 256*T_bm[1] + T_bm[0] #convert bytes to double T_meas = opt.code2voltage(T_cm) #convert ADC to voltage R_T = R_known * (Vcc/T_meas - 1) C = 1 -( R_T/R_t0) T_R = (-A + (A**2-(4*B*C))**0.5) / (2*B) print ("RTD temp: ", T_R)
print("spiRecv() got {} bytes: {{\n {}\n}}".format( len(bs), " ".join(["{:02X}".format(b) for b in bs]))) fl.progClose(conn) print("jtagScanChain(): {") for idCode in fl.jtagScanChain(conn, PROG_CONFIG): print(" 0x{:08X}".format(idCode)) print("}") print("flProgram()...") fl.flProgram(conn, "J:{}:../../../../hdlmake/apps/makestuff/swled/cksum/vhdl/fpga.xsvf".format(PROG_CONFIG)) print("...done.") fl.flSelectConduit(conn, CONDUIT) print("flIsFPGARunning(): {}".format(fl.flIsFPGARunning(conn))) fl.flWriteChannel(conn, 0, BYTE_ARRAY) bs = fl.flReadChannel(conn, 1, 16) print("flReadChannel(1, 16) got {} bytes: {{\n {}\n}}".format( len(bs), " ".join(["{:02X}".format(b) for b in bs]))) print("flReadChannel(2) got {:02X}".format(fl.flReadChannel(conn, 2))) fl.flReadChannelAsyncSubmit(conn, 0, 4) fl.flReadChannelAsyncSubmit(conn, 1, 8) fl.flReadChannelAsyncSubmit(conn, 2, 16) for i in range(3): bs = fl.flReadChannelAsyncAwait(conn)
raise fl.FLException( "JTAG chain scan requested but FPGALink device at {} does not support NeroJTAG".format(vp) ) if argList.p: progConfig = argList.p[0] print("Programming device with config {}...".format(progConfig)) if isNeroCapable: fl.flProgram(handle, progConfig) else: raise fl.FLException("Device program requested but device at {} does not support NeroProg".format(vp)) if argList.f and not (isCommCapable): raise fl.FLException("Data file load requested but device at {} does not support CommFPGA".format(vp)) if isCommCapable and fl.flIsFPGARunning(handle): print("Zeroing R1 & R2...") fl.flWriteChannel(handle, 0x01, 0x00) fl.flWriteChannel(handle, 0x02, 0x00) if argList.f: dataFile = argList.f[0] print("Writing {} to FPGALink device {}...".format(dataFile, vp)) for chunk in readFile(dataFile): fl.flWriteChannelAsync(handle, 0x00, chunk) print("Reading channel 0...") print("Got 0x{:02X}".format(fl.flReadChannel(handle, 0x00))) print("Reading channel 1...") print("Got 0x{:02X}".format(fl.flReadChannel(handle, 0x01))) print("Reading channel 2...") print("Got 0x{:02X}".format(fl.flReadChannel(handle, 0x02)))