def test_files(tool):
prj = Project(tool)
prj.add_files(get_path('../hdl/*.vhdl'))
prj.add_files(get_path('../hdl/*.v'))
assert len(prj.get_files()['verilog']) == 3
assert len(prj.get_files()['vhdl']) == 4
assert len(prj.get_files()['constraint']) == 0
def test_files():
prj = Project()
prj.set_top(get_pathfile('../hdl/fakes/top.vhdl'))
assert prj.tool.top == "Top1"
prj.set_top(get_pathfile('../hdl/fakes/top.v'))
assert prj.tool.top == "Top1"
prj.set_top(get_pathfile('../README.md'))
assert prj.tool.top == "UNDEFINED"
def test_libero():
prj = Project('libero')
assert get_part(prj) == "mpf100t-1-fcg484"
prj.set_part('m2s010-3-tq144')
assert get_part(prj) == "m2s010-3-tq144"
prj.set_part('m2s010-tq144-2')
assert get_part(prj) == "m2s010-2-tq144"
prj.set_part('m2s010-tq144')
assert get_part(prj) == "m2s010-std-tq144"
def test_ise():
prj = Project('ise')
assert get_part(prj) == "xc7k160t-3-fbg484"
prj.set_part('XC6SLX9-2-CSG324')
assert get_part(prj) == "xc6slx9-2-csg324"
prj.set_part('XC6SLX9-2L-CSG324')
assert get_part(prj) == "xc6slx9-2l-csg324"
prj.set_part('XC6SLX9-CSG324-3')
assert get_part(prj) == "xc6slx9-3-csg324"
def test_default():
prj = Project()
assert prj.tool.top == "UNDEFINED"
def test_names():
prj = Project()
prj.set_top('test1')
assert prj.tool.top == "test1"
prj.set_top('test2')
assert prj.tool.top == "test2"
"""Generic GHDL example project."""
import logging
from fpga.project import Project
logging.basicConfig()
prj = Project('ghdl')
prj.set_outdir('../../build/ghdl')
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.set_top('Top')
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Docker not found')
"""PyFPGA Multi Vendor VHDL example.
The main idea of a multi-vendor project is to implements the same HDL code
with different tools, to make comparisons. The project name is not important
and the default devices are used.
"""
import logging
from fpga.project import Project, TOOLS
logging.basicConfig()
for tool in TOOLS:
PRJ = Project(tool)
PRJ.set_outdir('../../build/multi/vhdl/%s' % tool)
PRJ.add_files('../../hdl/blinking.vhdl', library='examples')
PRJ.add_files('../../hdl/examples_pkg.vhdl', library='examples')
PRJ.add_files('../../hdl/top.vhdl')
PRJ.set_top('Top')
try:
PRJ.generate(to_task='syn')
except RuntimeError:
print('ERROR:generate:{} not found'.format(tool))
import argparse
import logging
from fpga.project import Project
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--lang',
choices=['verilog', 'vhdl'],
default='verilog',
)
args = parser.parse_args()
prj = Project('yosys')
prj.set_outdir('../../build/yosys-{}'.format(args.lang))
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.set_top('Top')
try:
import argparse
import logging
from fpga.project import Project
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
args = parser.parse_args()
prj = Project('ise')
prj.set_part('XC6SLX9-2-CSG324')
prj.set_outdir('../../build/ise')
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.set_top('Top')
prj.add_files('s6micro.xcf')
prj.add_files('s6micro.ucf')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
"""Zybo block design example project."""
import logging
from fpga.project import Project
logging.basicConfig()
prj = Project('vivado', 'zybo-design')
prj.set_part('xc7z010-1-clg400')
prj.set_outdir('../../build/zybo-design')
prj.add_files('../../hdl/blinking.vhdl')
prj.add_files('zybo.xdc')
prj.add_files('design.tcl', filetype='design')
export = """
set PROJECT %s
if { [ catch {
# Vitis
write_hw_platform -fixed -force -include_bit -file ${PROJECT}.xsa
} ] } {
# SDK
write_hwdef -force -file ${PROJECT}.hwdef
write_sysdef -force -hwdef [glob -nocomplain *.hwdef] \\
-bitfile [glob -nocomplain *.bit] -file ${PROJECT}.hdf
}
""" % ('zybo-design')
prj.add_hook(export, 'postbit')
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
parser.add_argument('--board', choices=['nexys3', 's6micro'], default='nexys3')
args = parser.parse_args()
BOARDS = {
'nexys3': ['XC6SLX16-3-CSG324', 'nexys3.ucf', 'nexys3.xcf'],
's6micro': ['XC6SLX9-2-CSG324', 's6micro.ucf', 's6micro.xcf']
}
prj = Project('ise')
prj.set_part(BOARDS[args.board][0])
prj.set_outdir('../../build/ise-{}'.format(args.board))
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.set_top('Top')
prj.add_files(BOARDS[args.board][1])
prj.add_files(BOARDS[args.board][2])
if args.action in ['generate', 'all']:
try:
prj.generate()
"""PyFPGA Multi Vendor Verilog example.
The main idea of a multi-vendor project is to implements the same HDL code
with different tools, to make comparisons. The project name is not important
and the default devices could be used.
"""
import logging
from fpga.project import Project, TOOLS
logging.basicConfig()
for tool in TOOLS:
if tool == 'ghdl':
continue
PRJ = Project(tool)
PRJ.set_outdir('../../build/multi/verilog/%s' % tool)
PRJ.add_path('../../hdl/headers1')
PRJ.add_path('../../hdl/headers2')
PRJ.add_files('../../hdl/blinking.v')
PRJ.add_files('../../hdl/top.v')
PRJ.set_top('Top')
try:
PRJ.generate(to_task='syn')
except RuntimeError:
print('ERROR:generate:{} not found'.format(tool))
parser = argparse.ArgumentParser()
parser.add_argument('--action',
choices=['generate', 'transfer', 'all'],
default='generate')
parser.add_argument('--lang', choices=['verilog', 'vhdl'], default='verilog')
parser.add_argument('--board',
choices=['orangecrab', 'ecp5evn'],
default='orangecrab')
args = parser.parse_args()
BOARDS = {
'orangecrab': ['25k-CSFBGA285', 'orangecrab_r0.2.lpf'],
'ecp5evn': ['um5g-85k-CABGA381', 'ecp5evn.lpf']
}
prj = Project('openflow')
prj.set_outdir('../../build/prjtrellis-{}-{}'.format(args.board, args.lang))
prj.set_part(BOARDS[args.board][0])
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files(BOARDS[args.board][1])
prj.set_top('Top')
def main():
"""Solves the main functionality of this helper."""
# Parsing the command-line.
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument('-v',
'--version',
action='version',
version='v{}'.format(version))
parser.add_argument('project',
metavar='PRJFILE',
help='a vendor project file')
parser.add_argument('--run',
metavar='TASK',
choices=TASKS[1:len(TASKS)],
default='bit',
help='task to perform [{}] ({})'.format(
'bit', " | ".join(TASKS[1:len(TASKS)])))
parser.add_argument('--clean',
action='store_true',
help='clean the generated project files')
args = parser.parse_args()
# Detecting a Project file
tool_per_ext = {
'.xise': 'ise',
'.prjx': 'libero',
'.qpf': 'quartus',
'.xpr': 'vivado'
}
if not os.path.exists(args.project):
sys.exit('Project file not found')
outdir = os.path.dirname(args.project)
project, extension = os.path.splitext(args.project)
project = os.path.basename(project)
tool = ''
if extension in tool_per_ext:
tool = tool_per_ext[extension]
print('{} Project file found.'.format(tool))
else:
sys.exit('Unknown Project file extension')
# Solving with PyFPGA
prj = Project(tool, project=project, relative_to_script=False)
prj.set_outdir(outdir)
prj.set_top(project)
try:
if args.clean:
prj.clean()
else:
prj.generate(args.run, 'syn')
except RuntimeError:
logging.error('{} not found'.format(tool))
except Exception as e:
sys.exit('{} ({})'.format(type(e).__name__, e))
set_property strategy "Flow_PerfOptimized_high" $obj
set_property "steps.synth_design.args.fanout_limit" "400" $obj
set_property "steps.synth_design.args.keep_equivalent_registers" "1" $obj
set_property "steps.synth_design.args.resource_sharing" "off" $obj
set_property "steps.synth_design.args.no_lc" "1" $obj
set_property "steps.synth_design.args.shreg_min_size" "5" $obj
set obj [get_runs impl_1]
set_property strategy "Performance_Explore" $obj
set_property "steps.opt_design.args.directive" "Explore" $obj
set_property "steps.place_design.args.directive" "Explore" $obj
set_property "steps.phys_opt_design.is_enabled" "1" $obj
set_property "steps.phys_opt_design.args.directive" "Explore" $obj
set_property "steps.route_design.args.directive" "Explore" $obj
"""
}
}
for tool in commands:
for strategy in commands[tool]:
PRJ = Project(tool)
PRJ.set_outdir('../../build/hooks/%s-%s' % (tool, strategy))
PRJ.add_files('../../hdl/blinking.vhdl')
PRJ.set_top('Blinking')
PRJ.add_hook('puts "Appling {} optimizations"'.format(strategy),
'project')
PRJ.add_hook(commands[tool][strategy], 'project')
try:
PRJ.generate(to_task='syn')
except RuntimeError:
print('ERROR:generate:{} not found'.format(tool))
import argparse
import logging
from fpga.project import Project
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
args = parser.parse_args()
prj = Project('libero')
prj.set_part('m2s010-1-tq144')
prj.set_outdir('../../build/libero')
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.set_top('Top')
prj.add_files('mkr.pdc')
prj.add_files('mkr.sdc')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
"""
import logging
from fpga.project import Project, TOOLS
logging.basicConfig()
for hdl in ['vhdl', 'verilog']:
for tool in TOOLS:
if tool == 'ghdl':
continue
if hdl == 'vhdl':
if tool in ['openflow', 'yosys', 'yosys-ise', 'yosys-vivado']:
continue
PRJ = Project(tool)
PRJ.set_param('FREQ', '50000000')
PRJ.set_param('SECS', '2')
PRJ.set_outdir('../../build/multi/params/%s/%s' % (tool, hdl))
if hdl == 'vhdl':
PRJ.add_files('../../hdl/blinking.vhdl')
else:
PRJ.add_path('../../hdl/headers1')
PRJ.add_path('../../hdl/headers2')
PRJ.add_files('../../hdl/blinking.v')
PRJ.set_top('Blinking')
# PRJ.set_param('INT', '15')
# PRJ.set_param('REA', '1.5')
# PRJ.set_param('LOG', "'1'")
# PRJ.set_param('VEC', '"10101010"')
# PRJ.set_param('STR', '"WXYZ"')
"""PyFPGA example about Memory Content Files inclusion.
This example is mainly used as a test of this feature through the different
tools.
"""
import logging
from fpga.project import Project, TOOLS
logging.basicConfig()
for hdl in ['vhdl', 'verilog']:
for tool in TOOLS:
if tool == 'ghdl' and hdl == 'verilog':
continue
PRJ = Project(tool)
PRJ.set_outdir('../../build/multi/memory/%s/%s' % (tool, hdl))
if hdl == 'vhdl':
PRJ.add_files('../../hdl/ram.vhdl')
else:
PRJ.add_files('../../hdl/ram.v')
PRJ.set_top('ram')
try:
PRJ.generate(to_task='syn')
except RuntimeError:
print('ERROR:generate:{} not found'.format(tool))
import logging
from fpga.project import Project
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action', choices=['generate', 'transfer', 'all'], default='generate',
)
parser.add_argument(
'--lang', choices=['verilog', 'vhdl'], default='verilog',
)
args = parser.parse_args()
prj = Project('yosys-ise')
prj.set_outdir('../../build/yosys-ise-{}'.format(args.lang))
prj.set_part('XC6SLX9-2-CSG324')
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files('../ise/s6micro.ucf')
prj.set_top('Top')
def main():
"""Solves the main functionality of this helper."""
# Parsing the command-line.
parser = argparse.ArgumentParser(
description=__doc__,
epilog=EPILOGUE,
formatter_class=argparse.RawDescriptionHelpFormatter)
parser.add_argument('-v',
'--version',
action='version',
version='v{}'.format(version))
parser.add_argument('bit',
metavar='BITFILE',
nargs='?',
help='a bitstream file')
parser.add_argument('-t',
'--tool',
metavar='TOOL',
default='vivado',
choices=TOOLS,
help='backend tool to be used [vivado]')
parser.add_argument('-o',
'--outdir',
metavar='PATH',
default='temp',
help='where to generate files [temp]')
parser.add_argument('-d',
'--device',
metavar='DEVTYPE',
choices=DEVS,
default=DEVS[0],
help='the target device type [{}]'.format(DEVS[0]))
parser.add_argument('-p',
'--position',
metavar='POSITION',
choices=POSITIONS,
type=int,
default=1,
help='the device position into the JTAG chain [1]')
parser.add_argument('-m',
'--memname',
metavar='MEMNAME',
default='',
help='memory name if spi or bpi selected')
parser.add_argument('-w',
'--width',
metavar='MEMWIDTH',
choices=MEMWIDTHS,
type=int,
default=1,
help='memory width if spi or bpi selected [1]')
parser.add_argument('--run',
metavar='ACTION',
choices=ACTIONS,
default=ACTIONS[0],
help='action to perform [{}]'.format(ACTIONS[0]))
args = parser.parse_args()
# Solving with PyFPGA
prj = Project(args.tool, relative_to_script=False)
prj.set_outdir(args.outdir)
if args.run == 'program':
devtype = args.device
prj.set_bitstream(args.bit)
elif args.run == 'detect':
devtype = 'detect'
else: # args.run == 'unlock'
devtype = 'unlock'
try:
prj.transfer(devtype, args.position, args.memname, args.width)
except RuntimeError:
logging.error('{} not found'.format(args.tool))
except Exception as e:
sys.exit('{} ({})'.format(type(e).__name__, e))
ROOT = Path(__file__).parent.resolve()
def build(prj):
prj.add_files(str(ROOT.parent / 'src' / '*.vhd'), 'examples')
prj.set_top('demo')
try:
prj.generate()
#prj.transfer()
except Exception as e:
print('{} ({})'.format(type(e).__name__, e))
for toolchain in ['vivado', 'yosys']:
if toolchain == 'vivado' and which('vivado'):
prj = Project('vivado', 'vhdl-cfg_vivado')
prj.set_outdir(str(ROOT / 'build' / 'vivado'))
prj.set_part('xc7z020clg400-1') # PYNQ-Z1
#! TODO I/O constraints file is missing
build(prj)
continue
if toolchain == 'yosys' and which('yosys'):
prj = Project('yosys', 'vhdl-cfg_yosys')
prj.set_outdir(str(ROOT / 'build' / 'yosys'))
#! TODO Is this the expected part format for Lattice devices?
"""
import logging
from fpga.project import Project
logging.basicConfig()
PROJECTS = {
'prj1':
Project(
'vivado', 'vivado-prj', {
'outdir':
'../../build/multi/projects/vivado',
'part':
'xc7k70t-3-fbg484',
'vhdl': [['../../hdl/blinking.vhdl', 'examples'],
['../../hdl/examples_pkg.vhdl', 'examples'],
'../../hdl/top.vhdl'],
'top':
'Top'
}),
'prj2':
Project(
'ise', 'ise-prj', {
'outdir': '../../build/multi/projects/ise',
'part': 'xc6slx9-2-csg324',
'vhdl': ['../../hdl/blinking.vhdl'],
'top': 'Blinking'
}),
'prj3':
Project(
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
parser.add_argument(
'--lang',
choices=['verilog', 'vhdl'],
default='verilog',
)
args = parser.parse_args()
prj = Project('yosys-vivado')
prj.set_outdir('../../build/yosys-vivado-{}'.format(args.lang))
prj.set_part('xc7z010-1-clg400')
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files('../vivado/zybo.xdc')
prj.set_top('Top')
import argparse
import logging
from fpga.project import Project
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
args = parser.parse_args()
prj = Project('quartus')
prj.set_part('5CSEBA6U23I7')
prj.set_outdir('../../build/quartus')
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.set_top('Top')
prj.add_files('de10nano.sdc')
prj.add_files('de10nano.tcl')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
import logging
from fpga.project import Project
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action', choices=['generate', 'transfer', 'all'], default='generate',
)
parser.add_argument(
'--lang', choices=['verilog', 'vhdl'], default='verilog',
)
args = parser.parse_args()
prj = Project('openflow')
prj.set_outdir('../../build/icestorm-{}'.format(args.lang))
prj.set_part('hx4k-tq144')
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files('*.pcf')
prj.set_top('Top')
import argparse
import logging
from fpga.project import Project
logging.basicConfig()
parser = argparse.ArgumentParser()
parser.add_argument(
'--action',
choices=['generate', 'transfer', 'all'],
default='generate',
)
args = parser.parse_args()
prj = Project('vivado')
prj.set_part('xc7z010-1-clg400')
prj.set_outdir('../../build/vivado')
prj.set_param('FREQ', '125000000')
prj.add_files('../../hdl/blinking.vhdl')
prj.add_files('zybo.xdc')
prj.set_top('Blinking')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Vivado not found')
