Пример #1
0
    def bench_async():
        q, d = create_signals(2, 8)
        p_rst = create_signals(1)
        clock, reset = create_clock_reset(rst_active=False, rst_async=True)

        dffa_inst = ff.dff(clock, d, q, reset=reset)

        clock_gen = clocker(clock)

        @always(clock.negedge)
        def stimulus():
            if reset and p_rst:
                assert d == q

            p_rst.next = reset
            d.next = randrange(2)

        @instance
        def reset_gen():
            yield delay(5)
            reset.next = 1

            while True:
                yield delay(randrange(500, 1000))
                reset.next = 0
                yield delay(randrange(80, 140))
                reset.next = 1

        return dffa_inst, clock_gen, stimulus, reset_gen
Пример #2
0
    def bench_async():
        q, d = create_signals(2, 8)
        p_rst = create_signals(1)
        clock, reset = create_clock_reset(rst_active=False, rst_async=True)

        dffa_inst = ff.dff_reset(q, d, clock, reset)

        clock_gen = clocker(clock)

        @always(clock.negedge)
        def stimulus():
            if reset and p_rst:
                assert d == q

            p_rst.next = reset
            d.next = randrange(2)

        @instance
        def reset_gen():
            yield delay(5)
            reset.next = 1

            while True:
                yield delay(randrange(500, 1000))
                reset.next = 0
                yield delay(randrange(80, 140))
                reset.next = 1

        return dffa_inst, clock_gen, stimulus, reset_gen
Пример #3
0
    def bench(tests=1000):
        M = 6
        load_left, load_right, left_ready, right_ready, sdata, ws, sclk, reset = create_signals(8)
        left, right, left_out, right_out, left_check, right_check = [Signal(intbv(0,_nrbits=M)) for _ in range(6)]

        transmitter = i2s.I2S_Transmitter(left, right, load_left, load_right, sdata, ws, sclk, reset)
        receiver = i2s.I2S_Receiver(sdata, ws, left_out, right_out, left_ready, right_ready, sclk, reset)

        clockgen = clocker(sclk)

        ws_count = Signal(intbv(0, min=0, max=M))
        ws_gen = clockdiv(sclk.negedge, ws, ws_count, M)

        @always(sclk.negedge)
        def left_right_gen():
            if ws_count == 0 and not ws:
                right_check.next = right
                right.next = randrange(2 ** M)
                load_right.next = True
                load_left.next = False
            elif ws_count == 0 and ws:
                left_check.next = left
                left.next = randrange(2 ** M)
                load_left.next = True
                load_right.next = False

        @instance
        def check():
            prev_left = True
            prev_right = True
            yield sclk.posedge
            reset.next = False

            for i in range(tests):
            # while True:
                yield sclk.posedge
                if ws_count == 0:
                    # We start a new ws round but we still need to get the LSB of the previous data stream
                    if ws:
                        assert left[0] == sdata
                    else:
                        assert right[0] == sdata
                else:
                    if ws:
                        assert right[M - ws_count] == sdata
                    else:
                        assert left[M - ws_count] == sdata

                if left_ready ^ prev_left:
                    assert left_out == left_check
                if right_ready ^ prev_right:
                    assert right_out == right_check

                prev_left = left_ready
                prev_right = right_ready

            raise StopSimulation

        return transmitter, receiver, clockgen, ws_gen, left_right_gen, check
Пример #4
0
    def bench(tests=1000):
        M = 6
        load_left, load_right, left_ready, right_ready, sdata, ws, sclk, reset = create_signals(8)
        left, right, left_out, right_out, left_check, right_check = [Signal(intbv(0, _nrbits=M)) for _ in range(6)]

        transmitter = i2s.I2S_Transmitter(left, right, load_left, load_right, sdata, ws, sclk, reset)
        receiver = i2s.I2S_Receiver(sdata, ws, left_out, right_out, left_ready, right_ready, sclk, reset)

        clockgen = clocker(sclk)

        ws_count = Signal(intbv(0, min=0, max=M))
        ws_gen = clockdiv(sclk.negedge, ws, ws_count, M)

        @always(sclk.negedge)
        def left_right_gen():
            if ws_count == 0 and not ws:
                right_check.next = right
                right.next = randrange(2 ** M)
                load_right.next = True
                load_left.next = False
            elif ws_count == 0 and ws:
                left_check.next = left
                left.next = randrange(2 ** M)
                load_left.next = True
                load_right.next = False

        @instance
        def check():
            prev_left = True
            prev_right = True
            yield sclk.posedge
            reset.next = False

            for i in range(tests):
                # while True:
                yield sclk.posedge
                if ws_count == 0:
                    # We start a new ws round but we still need to get the LSB of the previous data stream
                    if ws:
                        assert left[0] == sdata
                    else:
                        assert right[0] == sdata
                else:
                    if ws:
                        assert right[M - ws_count] == sdata
                    else:
                        assert left[M - ws_count] == sdata

                if left_ready ^ prev_left:
                    assert left_out == left_check
                if right_ready ^ prev_right:
                    assert right_out == right_check

                prev_left = left_ready
                prev_right = right_ready

            raise StopSimulation

        return transmitter, receiver, clockgen, ws_gen, left_right_gen, check
Пример #5
0
    def bench():
        q, d, clock = create_signals(3)

        dff_inst = ff.dff(clock, d, q)
        clock_gen = clocker(clock)

        @always(clock.negedge)
        def stimulus():
            assert d.val == q.val, ("D ({}) != Q ({})".format(int(d), int(q)))
            d.next = randrange(2)

        return dff_inst, clock_gen, stimulus
Пример #6
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    def bench(bus_width=4):
        assert bus_width > 2
        sdata, start, sclk = create_signals(3)
        dout = create_signals(1, bus_width, signed=True)

        s2p = i2s.Serial2Parallel(sdata, start, dout, sclk)

        output_data = [randrange(-2 ** (bus_width - 1), 2 ** (bus_width - 1))
                       for _ in range(20)]

        input_data = [int_to_bit_list(output_data[i], bus_width, signed=True)
                      for i in range(len(output_data))]

        clockgen = clocker(sclk)

        start_count = create_signals(1, (0, bus_width * 2))
        start_gen = clockdiv(sclk.negedge, start, start_count,
                             bus_width * 2 - 2, True)

        @instance
        def stimulus():
            for i in range(len(input_data)):
                for j in range(len(input_data[i])):
                    yield sclk.negedge
                    sdata.next = input_data[i][j]
                    if j == 0:
                        yield start.posedge

            raise StopSimulation

        @instance
        def check():
            # printstr = "{{start_count:>{busw}}} | {{sdata:>{busw}}} | {{dout:>{busw}}}"
            # printstr = printstr.format(busw=bus_width).format
            # print(printstr(start_count="sc", sdata="sd", dout="ou"))
            yield sclk.negedge

            i = 0
            for _ in range(50):
                # print(printstr(start_count=start_count, sdata=int(sdata),
                #                dout=binarystring(dout, prefix=None)))
                if start_count == 0:
                    if i > 1:
                        # i == 0 is the first load, data is ready at i == 2
                        assert dout == output_data[i - 2]
                    i += 1

                yield sclk.negedge

            raise StopSimulation    # No asserts yet

        return s2p, clockgen, start_gen, stimulus, check
Пример #7
0
def benchEncoder(tests=1000):

    din, dclk, dout, clock, reset = [Signal(False) for _ in range(5)]
    # formatter = ("|" + " {:^10} |" * 6).format
    # splitter = "+" + ("=" * 12 + "+") * 6

    dut = biphasemark.Encoder(din, dclk, dout, clock, reset)

    clockgen = clocker(clock)

    test_din = []
    test_clock = []
    test_dout = []

    for i in range(tests):
        sample = bool(random.randint(0, 1))
        test_din.append(sample)
        test_din.append(sample)
        test_clock.append(True)
        test_clock.append(False)
        try:
            prev_out = test_dout[(i * 2) - 1]
        except IndexError:
            prev_out = False

        test_dout.append(not prev_out)
        if sample:
            test_dout.append(prev_out)
        else:
            test_dout.append(not prev_out)

    @instance
    def check():
        yield clock.negedge
        reset.next = False

        # print formatter('din', 'dclk', 'dout', 'expect', 'clock', 'reset')
        # print splitter
        for i, c, o in zip(test_din, test_clock, test_dout):
            yield clock.negedge
            din.next = i
            dclk.next = c
            yield clock.negedge
            yield clock.negedge
            yield clock.negedge
            # print formatter(din, dclk, dout, o, clock, reset)

            assert dout == o

        raise StopSimulation

    return dut, clockgen, check
Пример #8
0
def benchEncoder(tests=1000):

    din, dclk, dout, clock, reset = [Signal(False) for _ in range(5)]
    # formatter = ("|" + " {:^10} |" * 6).format
    # splitter = "+" + ("=" * 12 + "+") * 6

    dut = biphasemark.Encoder(din, dclk, dout, clock, reset)

    clockgen = clocker(clock)

    test_din = []
    test_clock = []
    test_dout = []

    for i in range(tests):
        sample = bool(random.randint(0, 1))
        test_din.append(sample)
        test_din.append(sample)
        test_clock.append(True)
        test_clock.append(False)
        try:
            prev_out = test_dout[(i * 2) - 1]
        except IndexError:
            prev_out = False

        test_dout.append(not prev_out)
        if sample:
            test_dout.append(prev_out)
        else:
            test_dout.append(not prev_out)

    @instance
    def check():
        yield clock.negedge
        reset.next = False

        # print formatter('din', 'dclk', 'dout', 'expect', 'clock', 'reset')
        # print splitter
        for i, c, o in zip(test_din, test_clock, test_dout):
            yield clock.negedge
            din.next = i
            dclk.next = c
            yield clock.negedge
            yield clock.negedge
            yield clock.negedge
            # print formatter(din, dclk, dout, o, clock, reset)

            assert dout == o

        raise StopSimulation

    return dut, clockgen, check
Пример #9
0
    def bench():
        ticks = 5
        BITS = 35
        MAX = 2**BITS // 2
        MAXOUT = 2**(BITS * 2) // 2

        a, b = create_signals(2, BITS, signed=True)
        pipeA, pipeB = [
            create_signals(ticks, BITS, signed=True) for _ in range(2)
        ]
        p = create_signals(1, 2 * BITS, signed=True)
        clk, rst = create_signals(2)

        mult_inst = mult.Multiplier35Bit(a, b, p, clk, rst)

        clock_gen = clocker(clk)

        @instance
        def stimulus():
            iA, iB, pA, pB = 0, 0, 1, 1
            yield clk.negedge
            rst.next = False

            while True:
                yield clk.negedge
                a.next = randrange(-MAX, MAX)
                b.next = randrange(-MAX, MAX)
                pipeA[iA].next = a
                pipeB[iB].next = b
                iA = (iA + 1) % ticks
                iB = (iB + 1) % ticks

                if (p != pipeA[pA] * pipeB[pB]):
                    f_a = float(a)
                    f_b = float(b)
                    f_p = float(p)
                    f_pipeA = float(pipeA[pA])
                    f_pipeB = float(pipeB[pB])
                    print("{:5.4f}x{:5.4f} = {:5.4f}".format(
                        f_a / float(MAX), f_b /
                        float(MAX), (f_pipeA * f_pipeB) / float(MAXOUT)) +
                          " but got {:5.4f}, error: {:5.4f}".format(
                              f_p / float(MAXOUT), (f_pipeA * f_pipeB - f_p) /
                              float(MAXOUT)))
                assert p == pipeA[iA] * pipeB[iB], \
                    "Difference: p - a * b = {}".format(
                        bin(p - pipeA[iA] * pipeB[pB], 2 * BITS))

                pA = (pA + 1) % ticks
                pB = (pB + 1) % ticks

        return mult_inst, clock_gen, stimulus
Пример #10
0
    def bench():
        q, d, clock = create_signals(3)

        # dff_inst = ff.dff(q, d, clock)
        dff_inst = dff(q, d, clock)
        clock_gen = clocker(clock)

        @always(clock.negedge)
        def stimulus():
            assert d == q
            d.next = randrange(2)

        return dff_inst, clock_gen, stimulus
Пример #11
0
    def bench(tests=1000, bus_width=24):
        assert bus_width > 2
        bus_width = 24
        load_left, load_right, sdata, ws, sclk, reset = create_signals(6)
        left, right = create_signals(2, bus_width, signed=True)

        transmitter = i2s.I2S_Transmitter(left, right, load_left, load_right,
                                          sdata, ws, sclk, reset)

        clockgen = clocker(sclk)

        ws_count = create_signals(1, (0, bus_width))
        ws_gen = clockdiv(sclk.negedge, ws, ws_count, bus_width)

        MAX = 2 ** (bus_width - 1)

        @always(sclk.negedge)
        def left_right_gen():
            if ws_count == 0 and not ws:
                right.next = randrange(-MAX, MAX)
                load_right.next = True
                load_left.next = False
            elif ws_count == 0 and ws:
                left.next = randrange(-MAX, MAX)
                load_left.next = True
                load_right.next = False

        @instance
        def check():
            yield sclk.posedge
            reset.next = False

            for i in range(tests):
                yield sclk.posedge
                if ws_count == 0:
                    # We start a new ws round but we still need to get the LSB
                    # of the previous data stream
                    if ws:
                        assert left[0] == sdata
                    else:
                        assert right[0] == sdata
                else:
                    if ws:
                        assert right[bus_width - ws_count] == sdata
                    else:
                        assert left[bus_width - ws_count] == sdata

            raise StopSimulation

        return transmitter, clockgen, ws_gen, left_right_gen, check
Пример #12
0
    def bench():
        ticks = 5
        BITS = 35
        MAX = 2 ** BITS // 2
        MAXOUT = 2 ** (BITS * 2) // 2

        a, b = create_signals(2, BITS, signed=True)
        pipeA, pipeB = [create_signals(ticks, BITS, signed=True) for _ in range(2)]
        p = create_signals(1, 2 * BITS, signed=True)
        clk, rst = create_signals(2)

        mult_inst = mult.Multiplier35Bit(a, b, p, clk, rst)

        clock_gen = clocker(clk)

        @instance
        def stimulus():
            iA, iB, pA, pB = 0, 0, 1, 1
            yield clk.negedge
            rst.next = False

            while True:
                yield clk.negedge
                a.next = randrange(-MAX, MAX)
                b.next = randrange(-MAX, MAX)
                pipeA[iA].next = a
                pipeB[iB].next = b
                iA = (iA + 1) % ticks
                iB = (iB + 1) % ticks

                if (p != pipeA[pA] * pipeB[pB]):
                    f_a = float(a)
                    f_b = float(b)
                    f_p = float(p)
                    f_pipeA = float(pipeA[pA])
                    f_pipeB = float(pipeB[pB])
                    print("{:5.4f}x{:5.4f} = {:5.4f}".format(
                        f_a/float(MAX), f_b/float(MAX),
                        (f_pipeA * f_pipeB)/float(MAXOUT)) +
                        " but got {:5.4f}, error: {:5.4f}".format(
                            f_p/float(MAXOUT),
                            (f_pipeA * f_pipeB - f_p)/float(MAXOUT)))
                assert p == pipeA[iA] * pipeB[iB], \
                    "Difference: p - a * b = {}".format(
                        bin(p - pipeA[iA] * pipeB[pB], 2 * BITS))

                pA = (pA + 1) % ticks
                pB = (pB + 1) % ticks

        return mult_inst, clock_gen, stimulus
Пример #13
0
    def bench(tests=1000, bus_width=24):
        assert bus_width > 2
        bus_width = 24
        load_left, load_right, sdata, ws, sclk, reset = create_signals(6)
        left, right = create_signals(2, bus_width, signed=True)

        transmitter = i2s.I2S_Transmitter(left, right, load_left, load_right, sdata, ws, sclk, reset)

        clockgen = clocker(sclk)

        ws_count = create_signals(1, (0, bus_width))
        ws_gen = clockdiv(sclk.negedge, ws, ws_count, bus_width)

        MAX = 2 ** (bus_width - 1)

        @always(sclk.negedge)
        def left_right_gen():
            if ws_count == 0 and not ws:
                right.next = randrange(-MAX, MAX)
                load_right.next = True
                load_left.next = False
            elif ws_count == 0 and ws:
                left.next = randrange(-MAX, MAX)
                load_left.next = True
                load_right.next = False

        @instance
        def check():
            yield sclk.posedge
            reset.next = False

            for i in range(tests):
                yield sclk.posedge
                if ws_count == 0:
                    # We start a new ws round but we still need to get the LSB
                    # of the previous data stream
                    if ws:
                        assert left[0] == sdata
                    else:
                        assert right[0] == sdata
                else:
                    if ws:
                        assert right[bus_width - ws_count] == sdata
                    else:
                        assert left[bus_width - ws_count] == sdata

            raise StopSimulation

        return transmitter, clockgen, ws_gen, left_right_gen, check
Пример #14
0
    def bench(bus_width=4):
        assert bus_width > 2
        sdata, start, sclk = create_signals(3)
        dout = create_signals(1, bus_width, signed=True)

        s2p = i2s.Serial2Parallel(sdata, start, dout, sclk)

        output_data = [randrange(-2 ** (bus_width - 1), 2 ** (bus_width - 1)) for _ in range(20)]

        input_data = [int_to_bit_list(output_data[i], bus_width, signed=True) for i in range(len(output_data))]

        clockgen = clocker(sclk)

        start_count = create_signals(1, (0, bus_width * 2))
        start_gen = clockdiv(sclk.negedge, start, start_count, bus_width * 2 - 2, True)

        @instance
        def stimulus():
            for i in range(len(input_data)):
                for j in range(len(input_data[i])):
                    yield sclk.negedge
                    sdata.next = input_data[i][j]
                    if j == 0:
                        yield start.posedge

            raise StopSimulation

        @instance
        def check():
            # printstr = "{{start_count:>{busw}}} | {{sdata:>{busw}}} | {{dout:>{busw}}}"
            # printstr = printstr.format(busw=bus_width).format
            # print(printstr(start_count="sc", sdata="sd", dout="ou"))
            yield sclk.negedge

            i = 0
            for _ in range(50):
                # print(printstr(start_count=start_count, sdata=int(sdata),
                #                dout=binarystring(dout, prefix=None)))
                if start_count == 0:
                    if i > 1:
                        # i == 0 is the first load, data is ready at i == 2
                        assert dout == output_data[i - 2]
                    i += 1

                yield sclk.negedge

            raise StopSimulation  # No asserts yet

        return s2p, clockgen, start_gen, stimulus, check
Пример #15
0
    def bench():
        M = 8
        load, dout_msb, dout_lsb = create_signals(3)
        clock, reset = create_clock_reset()
        din = Signal(intbv(0, min=0, max=2**M))

        dut = p2s.p2s_msb(din, load, dout_msb, clock, reset)
        dut2 = p2s.p2s_lsb(din, load, dout_lsb, clock, reset)

        clockgen = clocker(clock)

        def input_gen():
            for i in range(2**M):
                yield i

        @instance
        def input_switch():
            yield clock.negedge
            a = input_gen()

            for i in range(2**M):
                din.next = next(a)
                for k in range(M):
                    yield clock.negedge
                    load.next = k == 0

        @instance
        def check():
            yield clock.negedge
            reset.next = False

            for j in range(2**M):
                yield load.negedge
                o_msb = intbv(0, min=din.min, max=din.max)
                o_lsb = intbv(0, min=din.min, max=din.max)
                for k in range(M):
                    yield clock.negedge
                    o_msb[M - 1 - k] = dout_msb
                    o_lsb[k] = dout_lsb

                # print(j, o_msb, o_lsb)
                # assert j == o_msb == o_lsb

            raise StopSimulation

        return dut, dut2, clockgen, input_switch, check
Пример #16
0
    def bench():
        M = 8
        load, dout_msb, dout_lsb = create_signals(3)
        clock, reset = create_clock_reset()
        din = Signal(intbv(0, min=0, max=2**M))

        dut = p2s.p2s_msb(din, load, dout_msb, clock, reset)
        dut2 = p2s.p2s_lsb(din, load, dout_lsb, clock, reset)

        clockgen = clocker(clock)

        def input_gen():
            for i in range(2 ** M):
                yield i

        @instance
        def input_switch():
            yield clock.negedge
            a = input_gen()

            for i in range(2 ** M):
                din.next = next(a)
                for k in range(M):
                    yield clock.negedge
                    load.next = k == 0

        @instance
        def check():
            yield clock.negedge
            reset.next = False

            for j in range(2 ** M):
                yield load.negedge
                o_msb = intbv(0, min=din.min, max=din.max)
                o_lsb = intbv(0, min=din.min, max=din.max)
                for k in range(M):
                    yield clock.negedge
                    o_msb[M - 1 - k] = dout_msb
                    o_lsb[k] = dout_lsb

                # print(j, o_msb, o_lsb)
                # assert j == o_msb == o_lsb

            raise StopSimulation

        return dut, dut2, clockgen, input_switch, check
Пример #17
0
    def bench():
        serin, serout, clk = create_signals(3)
        dout = create_signals(1, 3)
        crc_poly = myhdl.intbv(0, _nrbits=4)
        crc_poly[:] = 11

        clockgen = clocker(clk)
        crc_stream = check_crc_stream(serin, clk, crc_poly, dout)

        # Padded 1 bit to the front and 3 to the back
        input_stream = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
                        1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0,
                        1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0,
                        1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0,
                        1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 1, 1, 0, 0, 0, 0]

        @myhdl.instance
        def create_input():
            i = 0
            while True:
                yield clk.negedge
                i += 1
                if i >= len(input_stream):
                    raise myhdl.StopSimulation
                serin.next = input_stream[i]

        @myhdl.always(clk.posedge)
        def print_out():
            if frame_counter == 0:
                print("ZERO")
            print("|{:^6}|{:^6}|{:^6}|".format(int(serin), myhdl.bin(dout, dout._nrbits), serout))

        frame_counter = create_signals(1, (0, 16), mod=True)

        @myhdl.always(clk.posedge)
        def frame_counting():
            frame_counter.next = frame_counter + 1

        crc2 = check_crc_stream2(serin, serout, clk, crc_poly, frame_counter, 16)

        return clockgen, crc_stream, create_input, print_out, frame_counting, crc2
Пример #18
0
    def bench():
        BITS = 35
        MAX = 2**BITS // 2

        a, b = create_signals(2, BITS, signed=True)
        p = create_signals(1, 2 * BITS, signed=True)
        clk, rst = create_clock_reset()
        address_in, address_out = create_signals(2, 3, mod=True)
        pipeline = {i: (0, 0, 0, 0)
                    for i in range(len(address_in))}  # Check pipeline

        mult_inst = mult.AddressableMultiplier35Bit(a, b, p, address_in,
                                                    address_out, clk, rst)

        clock_gen = clocker(clk)

        @instance
        def stimulus():
            yield clk.negedge
            rst.next = False

            while True:
                yield clk.negedge
                a.next = randrange(-MAX, MAX)
                b.next = randrange(-MAX, MAX)
                address_in.next = address_in + 1

                check_address, check_a, check_b, check_p = pipeline[int(
                    address_out)]

                # print('-' * 20)
                # print(address_out, address_in)
                # print('-' * 20)
                # print(pipeline)
                # print('-' * 20)
                assert check_address == address_out and check_p == p

                pipeline[int(address_in)] = int(address_in), int(a), int(
                    b), int(a * b)

        return mult_inst, clock_gen, stimulus
Пример #19
0
    def bench(tests=1000):
        M = 6
        clock_delay = 4 * M

        left_ready, right_ready, sdata, sdata_out, ws, sclk, reset = create_signals(7)
        left, right = [Signal(intbv(0, _nrbits=M)) for _ in range(2)]
        sdata_pipe = Signal(intbv(0, _nrbits=clock_delay))

        transmitter = i2s.I2S_Transmitter(left, right, left_ready, right_ready, sdata_out, ws, sclk, reset)
        receiver = i2s.I2S_Receiver(sdata, ws, left, right, left_ready, right_ready, sclk, reset)

        clockgen = clocker(sclk)

        ws_count = Signal(intbv(0, min=0, max=M))
        ws_gen = clockdiv(sclk.negedge, ws, ws_count, M)

        @always(sclk.negedge)
        def data_gen():
            sdata.next = randrange(2)
            sdata_pipe.next = concat(sdata, sdata_pipe[clock_delay:1])

        @instance
        def check():
            check_counter = 0
            yield sclk.posedge
            reset.next = False

            for i in range(tests):
            # while True:
                yield sclk.posedge

                if check_counter <= 6 * M:
                    check_counter += 1
                else:
                    assert sdata_pipe[0] == sdata_out

            raise StopSimulation

        return transmitter, receiver, clockgen, ws_gen, data_gen, check
Пример #20
0
    def bench(tests=1000):
        M = 6
        clock_delay = 4 * M

        left_ready, right_ready, sdata, sdata_out, ws, sclk, reset = create_signals(7)
        left, right = [Signal(intbv(0, _nrbits=M)) for _ in range(2)]
        sdata_pipe = Signal(intbv(0, _nrbits=clock_delay))

        transmitter = i2s.I2S_Transmitter(left, right, left_ready, right_ready, sdata_out, ws, sclk, reset)
        receiver = i2s.I2S_Receiver(sdata, ws, left, right, left_ready, right_ready, sclk, reset)

        clockgen = clocker(sclk)

        ws_count = Signal(intbv(0, min=0, max=M))
        ws_gen = clockdiv(sclk.negedge, ws, ws_count, M)

        @always(sclk.negedge)
        def data_gen():
            sdata.next = randrange(2)
            sdata_pipe.next = concat(sdata, sdata_pipe[clock_delay:1])

        @instance
        def check():
            check_counter = 0
            yield sclk.posedge
            reset.next = False

            for i in range(tests):
                # while True:
                yield sclk.posedge

                if check_counter <= 6 * M:
                    check_counter += 1
                else:
                    assert sdata_pipe[0] == sdata_out

            raise StopSimulation

        return transmitter, receiver, clockgen, ws_gen, data_gen, check
Пример #21
0
    def bench():
        BITS = 35
        MAX = 2 ** BITS // 2

        a, b = create_signals(2, BITS, signed=True)
        p = create_signals(1, 2 * BITS, signed=True)
        clk, rst = create_clock_reset()
        address_in, address_out = create_signals(2, 3, mod=True)
        pipeline = {i: (0, 0, 0, 0) for i in range(len(address_in))}  # Check pipeline

        mult_inst = mult.AddressableMultiplier35Bit(a, b, p, address_in, address_out, clk, rst)

        clock_gen = clocker(clk)

        @instance
        def stimulus():
            yield clk.negedge
            rst.next = False

            while True:
                yield clk.negedge
                a.next = randrange(-MAX, MAX)
                b.next = randrange(-MAX, MAX)
                address_in.next = address_in + 1

                check_address, check_a, check_b, check_p = pipeline[int(address_out)]

                # print('-' * 20)
                # print(address_out, address_in)
                # print('-' * 20)
                # print(pipeline)
                # print('-' * 20)
                assert check_address == address_out and check_p == p

                pipeline[int(address_in)] = int(address_in), int(a), int(b), int(a * b)

        return mult_inst, clock_gen, stimulus
Пример #22
0
    def bench():
        M = 16

        d, load, sdata, sclk, reset = create_signals(5)
        p_in = create_signals(1, (0, M))

        shifter = i2s.ShiftRegister(p_in, d, load, sdata, sclk, reset)

        clockgen = clocker(sclk)

        testData = []
        pl = len(p_in)
        p = intbv(0, min=0, max=M)
        for i in range(M):
            p[:] = i
            testData.append((p[:], False, True, p[pl - 1]))

            for j in range(pl - 1):
                testData.append((p[:], False, False, p[pl - 2 - j]))

        @instance
        def stimulus():
            yield sclk.posedge
            reset.next = False
            yield sclk.posedge

            for p, din, l, sd in testData:
                p_in.next = p
                d.next = din
                load.next = l
                yield sclk.posedge
                assert sd == sdata

            raise StopSimulation

        return shifter, clockgen, stimulus
Пример #23
0
    def bench_sync():
        q, d = create_signals(2, 8)
        p_rst = create_signals(1)
        clock, reset = create_clock_reset()

        dffa_inst = ff.dff_reset(q, d, clock, reset)

        clock_gen = clocker(clock)

        @always(clock.negedge)
        def stimulus():
            if not p_rst:
                assert d == q
            # print("CLK DOWN | {} | {} | {} | {} | {} ".format(reset, p_rst, d,
            #       q, clock))

            d.next = randrange(2)

        @always(clock.posedge)
        def reset_buf_dly():
            # print("CLK UP   | {} | {} | {} | {} | {} ".format(reset, p_rst, d,
            #       q, clock))
            p_rst.next = reset

        @instance
        def reset_gen():
            yield delay(5)
            reset.next = 0

            while True:
                yield delay(randrange(500, 1000))
                reset.next = 1
                yield delay(randrange(80, 140))
                reset.next = 0

        return dffa_inst, clock_gen, stimulus, reset_gen, reset_buf_dly
Пример #24
0
    def bench():
        ws, wsd, nwsd, wsp, clk = create_signals(5)

        wordsel = i2s.WordSelect(ws, wsd, nwsd, wsp, clk)

        testData = [
            [False, False, True, False],
            [True, True, False, True],
            [True, True, False, False],
            [True, True, False, False],
            [True, True, False, False],
            [False, False, True, True],
            [False, False, True, False],
            [False, False, True, False]
        ]

        clockgen = clocker(clk)

        @instance
        def stimulus():
            yield clk.negedge

            for x in range(50):
                for w, wd, nwd, wp in testData:
                    ws.next = w
                    yield clk.negedge
                    # print "ws: {ws}, wsd: {wsd} (exp: {wd}), wsp: {wsp} (exp: {wp})".format(
                    #     ws=ws, wsd=wsd, wd=wd, wsp=wsp, wp=wp
                    # )
                    assert wd == wsd
                    assert nwd == nwsd == (not wsd)
                    assert wp == wsp

            raise StopSimulation

        return wordsel, clockgen, stimulus
Пример #25
0
    def bench():
        M = 16

        d, load, sdata, sclk, reset = create_signals(5)
        p_in = create_signals(1, (0, M))

        shifter = i2s.ShiftRegister(p_in, d, load, sdata, sclk, reset)

        clockgen = clocker(sclk)

        testData = []
        pl = len(p_in)
        p = intbv(0, min=0, max=M)
        for i in range(M):
            p[:] = i
            testData.append((p[:], False, True, p[pl - 1]))

            for j in range(pl - 1):
                testData.append((p[:], False, False, p[pl - 2 - j]))

        @instance
        def stimulus():
            yield sclk.posedge
            reset.next = False
            yield sclk.posedge

            for p, din, l, sd in testData:
                p_in.next = p
                d.next = din
                load.next = l
                yield sclk.posedge
                assert sd == sdata

            raise StopSimulation

        return shifter, clockgen, stimulus
Пример #26
0
    def bench():
        ws, wsd, nwsd, wsp, clk = create_signals(5)

        wordsel = i2s.WordSelect(ws, wsd, nwsd, wsp, clk)

        testData = [
            [False, False, True, False],
            [True, True, False, True],
            [True, True, False, False],
            [True, True, False, False],
            [True, True, False, False],
            [False, False, True, True],
            [False, False, True, False],
            [False, False, True, False],
        ]

        clockgen = clocker(clk)

        @instance
        def stimulus():
            yield clk.negedge

            for x in range(50):
                for w, wd, nwd, wp in testData:
                    ws.next = w
                    yield clk.negedge
                    # print "ws: {ws}, wsd: {wsd} (exp: {wd}), wsp: {wsp} (exp: {wp})".format(
                    #     ws=ws, wsd=wsd, wd=wd, wsp=wsp, wp=wp
                    # )
                    assert wd == wsd
                    assert nwd == nwsd == (not wsd)
                    assert wp == wsp

            raise StopSimulation

        return wordsel, clockgen, stimulus
Пример #27
0
    def bench_sync():
        q, d = create_signals(2, 8)
        p_rst = create_signals(1)
        clock, reset = create_clock_reset()

        dffa_inst = ff.dff_reset(q, d, clock, reset)

        clock_gen = clocker(clock)

        @always(clock.negedge)
        def stimulus():
            if not p_rst:
                assert d == q
            # print("CLK DOWN | {} | {} | {} | {} | {} ".format(reset, p_rst, d,
            #       q, clock))

            d.next = randrange(2)

        @always(clock.posedge)
        def reset_buf_dly():
            # print("CLK UP   | {} | {} | {} | {} | {} ".format(reset, p_rst, d,
            #       q, clock))
            p_rst.next = reset

        @instance
        def reset_gen():
            yield delay(5)
            reset.next = 0

            while True:
                yield delay(randrange(500, 1000))
                reset.next = 1
                yield delay(randrange(80, 140))
                reset.next = 0

        return dffa_inst, clock_gen, stimulus, reset_gen, reset_buf_dly
Пример #28
0
def benchDecoder(tests=1000, data_length=50):

    din, locked, dclk, dout, clock, reset = [Signal(False) for _ in range(6)]
    # formatter = ("|" + " {:^10} |" * 6).format
    # splitter = "+" + ("=" * 12 + "+") * 6

    dut = biphasemark.Decoder(din, locked, dclk, dout, clock, reset)

    clockgen = clocker(clock)

    test_din, test_clock, test_dout = [[] for _ in range(3)]

    for i in range(tests):
        test_din.append([])
        test_clock.append([False])
        test_dout.append([False, False])
        for j in range(data_length):
            sample = bool(random.randint(0, 1))
            test_dout[i].append(sample)
            test_dout[i].append(sample)

            try:
                prev_out = test_din[i][(j * 2) - 1]
            except IndexError:
                prev_out = False

            test_din[i].append(not prev_out)
            if sample:
                test_din[i].append(prev_out)
            else:
                test_din[i].append(not prev_out)

            if test_din[i][0] and test_din[i][1]:
                test_clock[i].append(True)
                test_clock[i].append(False)
            else:
                test_clock[i].append(False)
                test_clock[i].append(True)


        test_clock[i].pop()
        test_dout[i].pop()
        test_dout[i].pop()

    @instance
    def check():
        yield clock.negedge
        reset.next = False

        for j in range(tests):
            for k in range(15):
                yield clock.negedge
                reset.next = k == 0
            # print splitter
            # print formatter('Test', 'nr', j + 1, ' ', ' ', ' ')
            # print splitter
            # print formatter('din', 'locked', 'expclk', 'dclk', 'expout', 'dout')
            # print splitter
            count = 0
            for i, c, o in zip(test_din[j], test_clock[j], test_dout[j]):
                yield clock.negedge
                din.next = i
                for _ in range(j + 5):
                    yield clock.negedge
                # print formatter(din, locked, c, dclk, o, dout)

                if locked:
                    # if dclk != c:
                    #     print formatter('dclk', 'error', 'expect', c, 'got', dclk)
                    assert dclk == c

                    if count > 2:
                        # if dout != o:
                        #     print formatter('dout', 'error', 'expect', o, 'got', dout)
                        assert dout == o, "Dout error: expected %s got %s" % (o, dout)
                    count += 1

                for _ in range(j + 2):
                    yield clock.negedge

        raise StopSimulation

    return dut, clockgen, check
Пример #29
0
    def bench():
        BITS = 35
        MAX = 2 ** (BITS - 1)

        # The input signals

        # The numbers to multiply. a * b and c * d
        a, b, c, d, e, f = create_signals(6, BITS, signed=True)
        # The load signal, max = number of inputs signals + 1
        # A value of 0 will not load anything.
        load = create_signals(1, 2)

        # The output signals

        # The multiplied output signals
        p_ab, p_cd, p_ef = create_signals(3, 2 * BITS, signed=True)
        ab_ready, cd_ready, ef_ready = create_signals(3)

        p_sigs = create_signals(3, 2 * BITS, signed=True)
        p_rdys = create_signals(3)

        # Test bench global clock and reset
        clk, rst = create_clock_reset()

        # Test bench check values
        pipeline1 = []
        pipeline2 = []
        pipeline3 = []

        mult_inst = mult.ThreePortMultiplier35Bit(a, b, c, d, e, f, load,
                                                  clk, rst,
                                                  p_ab, ab_ready,
                                                  p_cd, cd_ready,
                                                  p_ef, ef_ready)

        mult_inst2 = mult.SharedMultiplier([a, c, e], [b, d, f], load, clk, rst,
                                           p_sigs, p_rdys)

        clock_gen = clocker(clk)

        # Loader
        @instance
        def loader():
            i = 0
            while True:
                yield clk.negedge

                if i < 5:
                    load.next = 0
                elif i < 10:
                    load.next = 1
                elif i < 15:
                    load.next = 2
                elif i < 20:
                    load.next = 3

                i += 1
                i %= 20

        def string_mult(a, b):
            return "| {:5.2e} * {:5.2e} = {:5.2e}".format(*map(float, (a, b, a * b)))

        @instance
        def stimulus():
            yield clk.negedge
            rst.next = False

            while True:
                yield clk.negedge
                a.next = randrange(-MAX, MAX)
                b.next = randrange(-MAX, MAX)
                c.next = randrange(-MAX, MAX)
                d.next = randrange(-MAX, MAX)
                e.next = randrange(-MAX, MAX)
                f.next = randrange(-MAX, MAX)

                # check_address, check_a, check_b, check_p = pipeline[int(address_out)]

                print('-' * 20)
                print(load, string_mult(a, b), string_mult(c, d), string_mult(e, f))
                print('-' * 20)
                if ab_ready:
                    print("AB: {:5.2e}".format(float(p_ab)))
                if cd_ready:
                    print("CD: {:5.2e}".format(float(p_cd)))
                if ef_ready:
                    print("EF: {:5.2e}".format(float(p_ef)))
                print('-' * 20)
                if p_rdys[0]:
                    print("AB2: {:5.2e}".format(float(p_sigs[0])))
                if p_rdys[1]:
                    print("CD2: {:5.2e}".format(float(p_sigs[1])))
                if p_rdys[2]:
                    print("EF2: {:5.2e}".format(float(p_sigs[2])))
                print('-' * 20)
                # assert check_address == address_out and check_p == p

                # pipeline[int(address_in)] = int(address_in), int(a), int(b), int(a * b)

        return mult_inst, mult_inst2, clock_gen, loader, stimulus
Пример #30
0
    def bench():
        BITS = 35
        MAX = 2**(BITS - 1)

        # The input signals

        # The numbers to multiply. a * b and c * d
        a, b, c, d, e, f = create_signals(6, BITS, signed=True)
        # The load signal, max = number of inputs signals + 1
        # A value of 0 will not load anything.
        load = create_signals(1, 2)

        # The output signals

        # The multiplied output signals
        p_ab, p_cd, p_ef = create_signals(3, 2 * BITS, signed=True)
        ab_ready, cd_ready, ef_ready = create_signals(3)

        p_sigs = create_signals(3, 2 * BITS, signed=True)
        p_rdys = create_signals(3)

        # Test bench global clock and reset
        clk, rst = create_clock_reset()

        # Test bench check values
        pipeline1 = []
        pipeline2 = []
        pipeline3 = []

        mult_inst = mult.ThreePortMultiplier35Bit(a, b, c, d, e, f, load, clk,
                                                  rst, p_ab, ab_ready, p_cd,
                                                  cd_ready, p_ef, ef_ready)

        mult_inst2 = mult.SharedMultiplier([a, c, e], [b, d, f], load, clk,
                                           rst, p_sigs, p_rdys)

        clock_gen = clocker(clk)

        # Loader
        @instance
        def loader():
            i = 0
            while True:
                yield clk.negedge

                if i < 5:
                    load.next = 0
                elif i < 10:
                    load.next = 1
                elif i < 15:
                    load.next = 2
                elif i < 20:
                    load.next = 3

                i += 1
                i %= 20

        def string_mult(a, b):
            return "| {:5.2e} * {:5.2e} = {:5.2e}".format(
                *map(float, (a, b, a * b)))

        @instance
        def stimulus():
            yield clk.negedge
            rst.next = False

            while True:
                yield clk.negedge
                a.next = randrange(-MAX, MAX)
                b.next = randrange(-MAX, MAX)
                c.next = randrange(-MAX, MAX)
                d.next = randrange(-MAX, MAX)
                e.next = randrange(-MAX, MAX)
                f.next = randrange(-MAX, MAX)

                # check_address, check_a, check_b, check_p = pipeline[int(address_out)]

                print('-' * 20)
                print(load, string_mult(a, b), string_mult(c, d),
                      string_mult(e, f))
                print('-' * 20)
                if ab_ready:
                    print("AB: {:5.2e}".format(float(p_ab)))
                if cd_ready:
                    print("CD: {:5.2e}".format(float(p_cd)))
                if ef_ready:
                    print("EF: {:5.2e}".format(float(p_ef)))
                print('-' * 20)
                if p_rdys[0]:
                    print("AB2: {:5.2e}".format(float(p_sigs[0])))
                if p_rdys[1]:
                    print("CD2: {:5.2e}".format(float(p_sigs[1])))
                if p_rdys[2]:
                    print("EF2: {:5.2e}".format(float(p_sigs[2])))
                print('-' * 20)
                # assert check_address == address_out and check_p == p

                # pipeline[int(address_in)] = int(address_in), int(a), int(b), int(a * b)

        return mult_inst, mult_inst2, clock_gen, loader, stimulus
Пример #31
0
    def bench(tests=1000, data_length=50):
        din, dclk, encoded, locked, decoded_clk, decoded, clock, reset = [Signal(False) for _ in range(8)]

        encoder = biphasemark.Encoder(din, dclk, encoded, clock, reset)
        decoder = biphasemark.Decoder(encoded, locked, decoded_clk, decoded, clock, reset)

        clockgen = clocker(clock)

        test_din = []
        test_clock = []
        test_encoded = []
        test_decoded = []

        for i in range(tests):
            test_din.append([])
            test_clock.append([])
            test_encoded.append([])
            test_decoded.append([])
            for j in range(data_length):
                sample = bool(random.randint(0, 1))
                test_din[i].append(sample)
                test_din[i].append(sample)
                test_clock[i].append(True)
                test_clock[i].append(False)
                try:
                    prev_out = test_encoded[i][(j * 2) - 1]
                except IndexError:
                    prev_out = False

                test_encoded[i].append(not prev_out)
                if sample:
                    test_encoded[i].append(prev_out)
                else:
                    test_encoded[i].append(not prev_out)

            test_decoded[i] = [False, False] + test_din[i]
            test_decoded[i].pop()
            test_decoded[i].pop()

        @instance
        def check():
            yield clock.negedge
            reset.next = False

            for j in range(tests):
                for k in range(15):
                    yield clock.negedge
                    reset.next = k == 0

                count = 0
                for i, c, e, d in zip(test_din[j], test_clock[j], test_encoded[j], test_decoded[j]):
                    yield clock.negedge
                    din.next = i
                    dclk.next = c
                    for _ in range(5):
                        yield clock.negedge

                    assert e == encoded, "Encoder issue: expected {} got {}".format(e, encoded)
                    if locked:
                        if count > 2:
                            assert d == decoded, "Decoder issue: expected {} got {}".format(d, decoded)
                        else:
                            count += 1

            raise StopSimulation

        return encoder, decoder, clockgen, check
Пример #32
0
    def bench(tests=24 * 64):
        cs1, valid1, user1, cs2, valid2, user2 = create_signals(6)
        audio1, audio2 = create_signals(2, 24, signed=True)
        frame0, ce_word, ce_bit, ce_bp, sdata, clk, rst = create_signals(7)

        transmitter = aes3.AES3_TX(audio1,
                                   cs1,
                                   valid1,
                                   user1,
                                   audio2,
                                   cs2,
                                   valid2,
                                   user2,
                                   frame0,
                                   ce_word,
                                   ce_bit,
                                   ce_bp,
                                   sdata,
                                   clk,
                                   rst,
                                   auto_clk=False)

        clk_count = create_signals(1, (0, 512), mod=True)

        clockgen = clocker(clk)

        @always(clk.posedge)
        def counter():
            clk_count.next = clk_count + 1

        @always_comb
        def biphase_clocker():
            if clk_count[1:0] == 0:
                ce_bp.next = 1
            else:
                ce_bp.next = 0

        @always_comb
        def bit_clocker():
            if clk_count[2:0] == 0:
                ce_bit.next = 1
            else:
                ce_bit.next = 0

        @always_comb
        def word_clocker():
            if clk_count == 0:
                ce_word.next = 1
            else:
                ce_word.next = 0

        @instance
        def check():
            had_frame_zero = False
            yield clk.posedge
            rst.next = True
            frame0.next = 0
            yield clk.posedge
            frame0.next = 0
            yield ce_word.posedge

            print('| ce_word | ce_bit  | ce_bp   | frame0  | sdata')
            for i in range(tests):
                rst.next = False
                frame0.next = 0
                if ce_bp:
                    print("| {:>7} | {:>7} | {:>7} | {:>7} | {:>7}".format(
                        ce_word, ce_bit, ce_bp, frame0, sdata))
                if clk_count == 0 and not had_frame_zero:
                    frame0.next = 1
                    had_frame_zero = True

                if ce_word:
                    audio1.next = randrange(audio1.min, audio1.max)
                    audio2.next = randrange(audio2.min, audio2.max)
                yield clk.negedge

            raise StopSimulation

        return transmitter, clockgen, check, counter, biphase_clocker, bit_clocker, word_clocker
Пример #33
0
    def bench(tests=24 * 64):
        cs1, valid1, user1, cs2, valid2, user2 = create_signals(6)
        audio1, audio2 = create_signals(2, 24, signed=True)
        frame0, ce_word, ce_bit, ce_bp, sdata, clk, rst = create_signals(7)

        transmitter = aes3.AES3_TX(
            audio1,
            cs1,
            valid1,
            user1,
            audio2,
            cs2,
            valid2,
            user2,
            frame0,
            ce_word,
            ce_bit,
            ce_bp,
            sdata,
            clk,
            rst,
            auto_clk=False,
        )

        clk_count = create_signals(1, (0, 512), mod=True)

        clockgen = clocker(clk)

        @always(clk.posedge)
        def counter():
            clk_count.next = clk_count + 1

        @always_comb
        def biphase_clocker():
            if clk_count[1:0] == 0:
                ce_bp.next = 1
            else:
                ce_bp.next = 0

        @always_comb
        def bit_clocker():
            if clk_count[2:0] == 0:
                ce_bit.next = 1
            else:
                ce_bit.next = 0

        @always_comb
        def word_clocker():
            if clk_count == 0:
                ce_word.next = 1
            else:
                ce_word.next = 0

        @instance
        def check():
            had_frame_zero = False
            yield clk.posedge
            rst.next = True
            frame0.next = 0
            yield clk.posedge
            frame0.next = 0
            yield ce_word.posedge

            print("| ce_word | ce_bit  | ce_bp   | frame0  | sdata")
            for i in range(tests):
                rst.next = False
                frame0.next = 0
                if ce_bp:
                    print("| {:>7} | {:>7} | {:>7} | {:>7} | {:>7}".format(ce_word, ce_bit, ce_bp, frame0, sdata))
                if clk_count == 0 and not had_frame_zero:
                    frame0.next = 1
                    had_frame_zero = True

                if ce_word:
                    audio1.next = randrange(audio1.min, audio1.max)
                    audio2.next = randrange(audio2.min, audio2.max)
                yield clk.negedge

            raise StopSimulation

        return transmitter, clockgen, check, counter, biphase_clocker, bit_clocker, word_clocker
Пример #34
0
def benchDecoder(tests=1000, data_length=50):

    din, locked, dclk, dout, clock, reset = [Signal(False) for _ in range(6)]
    # formatter = ("|" + " {:^10} |" * 6).format
    # splitter = "+" + ("=" * 12 + "+") * 6

    dut = biphasemark.Decoder(din, locked, dclk, dout, clock, reset)

    clockgen = clocker(clock)

    test_din, test_clock, test_dout = [[] for _ in range(3)]

    for i in range(tests):
        test_din.append([])
        test_clock.append([False])
        test_dout.append([False, False])
        for j in range(data_length):
            sample = bool(random.randint(0, 1))
            test_dout[i].append(sample)
            test_dout[i].append(sample)

            try:
                prev_out = test_din[i][(j * 2) - 1]
            except IndexError:
                prev_out = False

            test_din[i].append(not prev_out)
            if sample:
                test_din[i].append(prev_out)
            else:
                test_din[i].append(not prev_out)

            if test_din[i][0] and test_din[i][1]:
                test_clock[i].append(True)
                test_clock[i].append(False)
            else:
                test_clock[i].append(False)
                test_clock[i].append(True)

        test_clock[i].pop()
        test_dout[i].pop()
        test_dout[i].pop()

    @instance
    def check():
        yield clock.negedge
        reset.next = False

        for j in range(tests):
            for k in range(15):
                yield clock.negedge
                reset.next = k == 0
            # print splitter
            # print formatter('Test', 'nr', j + 1, ' ', ' ', ' ')
            # print splitter
            # print formatter('din', 'locked', 'expclk', 'dclk', 'expout', 'dout')
            # print splitter
            count = 0
            for i, c, o in zip(test_din[j], test_clock[j], test_dout[j]):
                yield clock.negedge
                din.next = i
                for _ in range(j + 5):
                    yield clock.negedge
                # print formatter(din, locked, c, dclk, o, dout)

                if locked:
                    # if dclk != c:
                    #     print formatter('dclk', 'error', 'expect', c, 'got', dclk)
                    assert dclk == c

                    if count > 2:
                        # if dout != o:
                        #     print formatter('dout', 'error', 'expect', o, 'got', dout)
                        assert dout == o, "Dout error: expected %s got %s" % (
                            o, dout)
                    count += 1

                for _ in range(j + 2):
                    yield clock.negedge

        raise StopSimulation

    return dut, clockgen, check
Пример #35
0
    def bench():
        M = 256
        N = M - 1
        din, locked, clock, reset = [Signal(False) for _ in range(4)]
        current, prev = [Signal(intbv(0, min=0, max=M)) for _ in range(2)]
        minimum = Signal(intbv(N, min=0, max=M))

        dut = biphasemark.EdgeCounter(din, locked, minimum, current, prev,
                                      clock, reset)

        # formatter = ("|" + "{:^8}|" * 5).format
        # splitter = ("+" + "=" * 8) * 5 + "+"

        clockgen = clocker(clock)

        ticks = 5
        half = ticks - 1
        whole = ticks * 2 - 1
        data_in = [
            [False, False, True, True, False, False, True],  # 000
            [False, False, True, True, False, True, False],  # 001
            [False, False, True, False, True, True, False],  # 010
            [False, False, True, False, True, False, True],  # 011
            [False, True, False, False, True, True, False],  # 100
            [False, True, False, False, True, False, True],  # 101
            [False, True, False, True, False, False, True],  # 110
            [False, True, False, True, False, True, False],  # 111
            [True, True, False, False, True, True, False],  # 000
            [True, True, False, False, True, False, True],  # 001
            [True, True, False, True, False, False, True],  # 010
            [True, True, False, True, False, True, False],  # 011
            [True, False, True, True, False, False, True],  # 100
            [True, False, True, True, False, True, False],  # 101
            [True, False, True, False, True, True, False],  # 110
            [True, False, True, False, True, False, True]  # 111
        ]
        data_out = [
            [
                [False, N, 0, 0],
                [False, N, 0, 0],
                [False, N, 0,
                 0],  # Here comes the first edge and starts the count
                [False, N, 0, 0],
                [False, whole, whole,
                 0],  # Second edge and first output values
                [False, whole, whole, 0],
                [False, whole, whole, whole],
            ],
            [
                [False, N, 0, 0],
                [False, N, 0, 0],
                [False, N, 0,
                 0],  # Here comes the first edge and starts the count
                [False, N, 0, 0],
                [False, whole, whole,
                 0],  # Second edge and first output values (no lock)
                [True, half, half, whole],  # Third edge, definitely got a one
                [True, half, half, half],
            ],
            [
                [False, 0, 0, 0],
                [False, 0, 0, 0],
                [False, 0, 0, 0],
                [True, ticks, ticks, ticks * 2],
                [True, ticks, ticks, ticks],
                [True, ticks, ticks * 2, ticks],
            ],
        ]

        @instance
        def check():
            yield clock.negedge
            reset.next = False

            for i in range(len(data_in)):
                # print splitter
                # print formatter('din', 'locked', 'min', 'current', 'prev')
                # print splitter
                yield clock.negedge
                reset.next = True
                yield clock.negedge
                reset.next = False
                for j in range(len(data_in[i])):
                    din.next = data_in[i][j]
                    yield clock.negedge
                    yield clock.negedge
                    yield clock.negedge
                    yield clock.negedge
                    yield clock.negedge
                    # print formatter(din, locked, minimum, current, prev)

            raise StopSimulation

        return dut, clockgen, check
Пример #36
0
    def bench(tests=1000, data_length=50):
        din, dclk, encoded, locked, decoded_clk, decoded, clock, reset = [
            Signal(False) for _ in range(8)
        ]

        encoder = biphasemark.Encoder(din, dclk, encoded, clock, reset)
        decoder = biphasemark.Decoder(encoded, locked, decoded_clk, decoded,
                                      clock, reset)

        clockgen = clocker(clock)

        test_din = []
        test_clock = []
        test_encoded = []
        test_decoded = []

        for i in range(tests):
            test_din.append([])
            test_clock.append([])
            test_encoded.append([])
            test_decoded.append([])
            for j in range(data_length):
                sample = bool(random.randint(0, 1))
                test_din[i].append(sample)
                test_din[i].append(sample)
                test_clock[i].append(True)
                test_clock[i].append(False)
                try:
                    prev_out = test_encoded[i][(j * 2) - 1]
                except IndexError:
                    prev_out = False

                test_encoded[i].append(not prev_out)
                if sample:
                    test_encoded[i].append(prev_out)
                else:
                    test_encoded[i].append(not prev_out)

            test_decoded[i] = [False, False] + test_din[i]
            test_decoded[i].pop()
            test_decoded[i].pop()

        @instance
        def check():
            yield clock.negedge
            reset.next = False

            for j in range(tests):
                for k in range(15):
                    yield clock.negedge
                    reset.next = k == 0

                count = 0
                for i, c, e, d in zip(test_din[j], test_clock[j],
                                      test_encoded[j], test_decoded[j]):
                    yield clock.negedge
                    din.next = i
                    dclk.next = c
                    for _ in range(5):
                        yield clock.negedge

                    assert e == encoded, "Encoder issue: expected {} got {}".format(
                        e, encoded)
                    if locked:
                        if count > 2:
                            assert d == decoded, "Decoder issue: expected {} got {}".format(
                                d, decoded)
                        else:
                            count += 1

            raise StopSimulation

        return encoder, decoder, clockgen, check
Пример #37
0
    def bench():
        M = 256
        N = M - 1
        din, locked, clock, reset = [Signal(False) for _ in range(4)]
        current, prev = [Signal(intbv(0, min=0, max=M)) for _ in range(2)]
        minimum = Signal(intbv(N, min=0, max=M))

        dut = biphasemark.EdgeCounter(din, locked, minimum, current, prev, clock, reset)

        # formatter = ("|" + "{:^8}|" * 5).format
        # splitter = ("+" + "=" * 8) * 5 + "+"

        clockgen = clocker(clock)

        ticks = 5
        half = ticks - 1
        whole = ticks * 2 - 1
        data_in = [
            [False, False, True, True, False, False, True], # 000
            [False, False, True, True, False, True, False], # 001
            [False, False, True, False, True, True, False], # 010
            [False, False, True, False, True, False, True], # 011
            [False, True, False, False, True, True, False], # 100
            [False, True, False, False, True, False, True], # 101
            [False, True, False, True, False, False, True], # 110
            [False, True, False, True, False, True, False], # 111
            [True, True, False, False, True, True, False],  # 000
            [True, True, False, False, True, False, True],  # 001
            [True, True, False, True, False, False, True],  # 010
            [True, True, False, True, False, True, False],  # 011
            [True, False, True, True, False, False, True],  # 100
            [True, False, True, True, False, True, False],  # 101
            [True, False, True, False, True, True, False],  # 110
            [True, False, True, False, True, False, True]   # 111
        ]
        data_out = [
            [
                [False, N, 0, 0],
                [False, N, 0, 0],
                [False, N, 0, 0],             # Here comes the first edge and starts the count
                [False, N, 0, 0],
                [False, whole, whole, 0],       # Second edge and first output values
                [False, whole, whole, 0],
                [False, whole, whole, whole],
            ],
            [
                [False, N, 0, 0],
                [False, N, 0, 0],
                [False, N, 0, 0],             # Here comes the first edge and starts the count
                [False, N, 0, 0],
                [False, whole, whole, 0],     # Second edge and first output values (no lock)
                [True, half, half, whole],      # Third edge, definitely got a one
                [True, half, half, half],
            ],
            [
                [False, 0, 0, 0],
                [False, 0, 0, 0],
                [False, 0, 0, 0],
                [True, ticks, ticks, ticks * 2],
                [True, ticks, ticks, ticks],
                [True, ticks, ticks * 2, ticks],
            ],
        ]

        @instance
        def check():
            yield clock.negedge
            reset.next = False

            for i in range(len(data_in)):
                # print splitter
                # print formatter('din', 'locked', 'min', 'current', 'prev')
                # print splitter
                yield clock.negedge
                reset.next = True
                yield clock.negedge
                reset.next = False
                for j in range(len(data_in[i])):
                    din.next = data_in[i][j]
                    yield clock.negedge
                    yield clock.negedge
                    yield clock.negedge
                    yield clock.negedge
                    yield clock.negedge
                    # print formatter(din, locked, minimum, current, prev)

            raise StopSimulation

        return dut, clockgen, check