Пример #1
0
class SimpleExample(EnvExperiment):
    """
    Initializes an experiment and setup, and does a characterization on a single
    qubit.
    """

    def build(self):
        address = '0.0.0.0:2452'
        self.pip = FPGA(address, verbosity=1)   # Initializes an FPGA object to use as the base of our setup
        self.pip.load("PIPISTRELLO_DEFAULT")    # Defines the ports and methods for acting on this setup
        self.pip.connect(self)                  # We connect the experiment to the FPGA

    @kernel
    def run(self):

        # Now we run a blocking experiment which characterizes the setup,
        # and then displays the results
        self.pip.initialize()
        self.pip.characterize()
def fpga_setup(bitfile_path):
    #bitfile and hwh file have to be in the same directory
    start = time.time()
    fpga = FPGA(bitfile_path)
    print("Bitfile Loading Time: " + str(time.time() - start) + "s")
    return fpga
Пример #3
0
  if bitfile.processed[settings.chain]:
    logger.log("Loading pre-processed bitstream...", False)
    start_time = time.time()
    processed_bitstream = BitFile.load_processed(bitfileName, settings.chain)
    logger.log("Loaded pre-processed bitstream in %f seconds" % (time.time() - start_time), False)
  else:
    logger.log("Pre-processing bitstream for chain = %d..." % settings.chain, False)
    start_time = time.time()
    processed_bitstream = BitFile.pre_process(bitfile.bitstream, jtag, settings.chain, logger.updateProgress)
    logger.log("Pre-processed bitstream in %f seconds" % (time.time() - start_time), False)
    logger.log("Saving pre-processed bitstream...", False)
    start_time = time.time()
    BitFile.save_processed(bitfileName, processed_bitstream, settings.chain)
    logger.log("Saved pre-processed bitstream in %f seconds" % (time.time() - start_time), False)
  
  logger.log("Beginning programming...", False)
  if settings.chain == 2:
    logger.log("Programming both FPGAs...", False)
  else:
    logger.log("Programming FPGA %d..." % settings.chain, False)
  start_time = time.time()
  FPGA.programBitstream(ft232r, jtag, logger, processed_bitstream)
  if settings.chain == 2:
    logger.log("Programmed both FPGAs in %f seconds" % (time.time() - start_time), False)
  else:
    logger.log("Programmed FPGA %d in %f seconds" % (settings.chain, time.time() - start_time), False)
  
  if settings.sleep:
    for fpga in fpga_list:
      fpga.sleep()
Пример #4
0
            #
            #     dlen -= (bsize / 4) * 3
            #     self.drx += bsize


if __name__ == '__main__':
    from fpga import FPGA
    from programmer_avr import AVRISP
    from programmer_xmega import XMEGAPDI, supported_xmega
    from serial import USART

    cwtestusb = NAEUSB()
    cwtestusb.con()

    #Connect required modules up here
    fpga = FPGA(cwtestusb)
    xmega = XMEGAPDI(cwtestusb)
    avr = AVRISP(cwtestusb)
    usart = USART(cwtestusb)

    force = True
    if fpga.isFPGAProgrammed() == False or force:
        from datetime import datetime
        starttime = datetime.now()
        fpga.FPGAProgram(open(r"C:\E\Documents\academic\sidechannel\chipwhisperer\hardware\capture\chipwhisperer-lite\hdl\cwlite_ise\cwlite_interface.bit", "rb"))
        # fpga.FPGAProgram(open(r"C:\Users\colin\dropbox\engineering\git_repos\CW305_ArtixTarget\temp\artix7test\artix7test.runs\impl_1\cw305_top.bit", "rb"))
        # fpga.FPGAProgram(open(r"C:\E\Documents\academic\sidechannel\chipwhisperer\hardware\api\chipwhisperer-lite\hdl\cwlite_ise_spifake\cwlite_interface.bit", "rb"))
        stoptime = datetime.now()
        print "FPGA Config time: %s" % str(stoptime - starttime)

    # print fpga.cmdReadMem(10, 6)
Пример #5
0
            # TODO: This probably isn't needed, and causes slow-downs on Mac OS X.
            self.usbdev().read(self.rep, 1000, timeout=0.010)
        except:
            pass

if __name__ == '__main__':
    from fpga import FPGA
    from programmer_avr import AVRISP
    from programmer_xmega import XMEGAPDI, supported_xmega
    from serial import USART

    cwtestusb = NAEUSB()
    cwtestusb.con()

    #Connect required modules up here
    fpga = FPGA(cwtestusb)
    xmega = XMEGAPDI(cwtestusb)
    avr = AVRISP(cwtestusb)
    usart = USART(cwtestusb)

    force = True
    if fpga.isFPGAProgrammed() == False or force:
        from datetime import datetime
        starttime = datetime.now()
        fpga.FPGAProgram(open(r"C:\E\Documents\academic\sidechannel\chipwhisperer\hardware\capture\chipwhisperer-lite\hdl\cwlite_ise\cwlite_interface.bit", "rb"))
        # fpga.FPGAProgram(open(r"C:\Users\colin\dropbox\engineering\git_repos\CW305_ArtixTarget\temp\artix7test\artix7test.runs\impl_1\cw305_top.bit", "rb"))
        # fpga.FPGAProgram(open(r"C:\E\Documents\academic\sidechannel\chipwhisperer\hardware\api\chipwhisperer-lite\hdl\cwlite_ise_spifake\cwlite_interface.bit", "rb"))
        stoptime = datetime.now()
        print "FPGA Config time: %s" % str(stoptime - starttime)

    # print fpga.cmdReadMem(10, 6)
Пример #6
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logger.log(" Date: %s" % bitfile.date, False)
logger.log(" Time: %s" % bitfile.time, False)
logger.log(" Bitstream Length: %d" % len(bitfile.bitstream), False)

fpga_list = []

with FT232R() as ft232r:
    portlist = FT232R_PortList(7, 6, 5, 4, 3, 2, 1, 0)
    if ft232r.open(settings.devicenum, portlist):
        logger.reportOpened(ft232r.devicenum, ft232r.serial)
    else:
        logger.log("ERROR: FT232R device not opened!", False)
        sys.exit()

    if settings.chain == 0 or settings.chain == 1:
        fpga_list.append(FPGA(ft232r, settings.chain, logger))
    elif settings.chain == 2:
        fpga_list.append(FPGA(ft232r, 0, logger))
        fpga_list.append(FPGA(ft232r, 1, logger))
    else:
        logger.log("ERROR: Invalid chain option!", False)
        parser.print_usage()
        sys.exit()

    for id, fpga in enumerate(fpga_list):
        fpga.id = id
        logger.reportDebug("Discovering FPGA %d ..." % id, False)
        fpga.detect()

        logger.reportDebug(
            "Found %i device%s:" %
Пример #7
0
logger = ConsoleLogger(settings.verbose)
rpcclient = RPCClient(settings, logger, goldqueue)

try:
    # open FT232R
    ft232r = FT232R()
    portlist = FT232R_PortList(7, 6, 5, 4, 3, 2, 1, 0)
    if ft232r.open(settings.devicenum, portlist):
        logger.reportOpened(ft232r.devicenum, ft232r.serial)
    else:
        logger.log("ERROR: FT232R device not opened!", False)
        sys.exit()

    if settings.chain == 0 or settings.chain == 1:
        fpga_list.append(FPGA(ft232r, settings.chain, logger))
    elif settings.chain == 2:
        fpga_list.append(FPGA(ft232r, 0, logger))
        fpga_list.append(FPGA(ft232r, 1, logger))
    else:
        logger.log("ERROR: Invalid chain option!", False)
        parser.print_usage()
        sys.exit()

    logger.fpga_list = fpga_list
    rpcclient.fpga_list = fpga_list

    for id, fpga in enumerate(fpga_list):
        fpga.id = id
        logger.reportDebug("Discovering FPGA %d..." % id, False)
        fpga.detect()
Пример #8
0
 def build(self):
     address = '0.0.0.0:2452'
     self.pip = FPGA(address, verbosity=1)   # Initializes an FPGA object to use as the base of our setup
     self.pip.load("PIPISTRELLO_DEFAULT")    # Defines the ports and methods for acting on this setup
     self.pip.connect(self)                  # We connect the experiment to the FPGA