def shuffle_right(word, amount):
""" shuffle a word right (x2) adding 0's to the left """
network = word[0].network
res = [Tie(network, False) for i in range(amount)] + word
if amount:
carry = Or(*res[len(word):])
else:
carry = Tie(network, False)
return res[:len(word)], carry
def tie_word(network, size, value=0):
""" an entire word of ties """
res = []
for i in range(size):
res.append(Tie(network, value=value % 2))
value //= 2
return res
def ripple_incr(word):
""" increment a word by 1 """
c = Tie(word[0].network, True)
rw = []
for a in word:
r, c = half_adder(a, c)
rw.append(r)
return rw, c
def low_literal(clock, write, address, data_in, size):
"""
mirror the address bits back on the low bits of the data bus, pad with 0's
address read write
N N -
"""
data_out = []
data_out.extend(address[:size])
for i in range(len(data_in) - size):
data_out.append(Tie(clock.network, False))
return data_out
def high_literal(clock, write, address, data_in, size):
"""
mirror the address bits back on the high bits of the data bus, pad with 0's
address read write
N N<<(word_size-size) -
"""
data_out = []
for i in range(len(data_in) - size):
data_out.append(Tie(clock.network, False))
data_out.extend(address[:size])
return data_out
def memory(clock, write, address, data_in, size):
"""
a block of RAM
address read write
N [N] [N]
"""
# address_decode can't deal with empty addresses (aka 1 word memories)
if not size:
control_lines = [Tie(clock.network, True)]
else:
control_lines = address_decode(address[:size])
# otherwise it's a simple pile of registers switched by the control lines
registers = []
data_in_ = invert(data_in)
for line in control_lines:
registers.append(
register(data_in_,
And(line, clock, write),
negate_in=True,
negate_out=True))
return word_switch_(control_lines, *registers)
def pad(word, length, value=False):
""" right pad a word out to a specific length """
tie = Tie(word[0].network, value)
return word + [tie] * (length - len(word))