def __init__(self, platform, with_analyzer=True, with_loopback=False):
sys_clk_freq = int(100e6)
# SoCMini ----------------------------------------------------------------------------------
SoCMini.__init__(self,
platform,
sys_clk_freq,
ident="PCIe Screamer",
ident_version=True)
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq)
# Serial Wishbone Bridge -------------------------------------------------------------------
self.submodules.bridge = UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=3e6)
self.add_wb_master(self.bridge.wishbone)
# PCIe PHY ---------------------------------------------------------------------------------
self.submodules.pcie_phy = S7PCIEPHY(platform,
platform.request("pcie_x1"))
self.add_csr("pcie_phy")
# USB FT601 PHY ----------------------------------------------------------------------------
self.submodules.usb_phy = FT601Sync(platform.request("usb_fifo"),
dw=32,
timeout=1024)
# USB Loopback -----------------------------------------------------------------------------
if with_loopback:
self.submodules.usb_loopback_fifo = stream.SyncFIFO(
phy_description(32), 2048)
self.comb += [
self.usb_phy.source.connect(self.usb_loopback_fifo.sink),
self.usb_loopback_fifo.source.connect(self.usb_phy.sink)
]
# USB Core ---------------------------------------------------------------------------------
else:
self.submodules.usb_core = USBCore(self.usb_phy, sys_clk_freq)
# USB <--> Wishbone --------------------------------------------------------------------
self.submodules.etherbone = Etherbone(self.usb_core,
self.usb_map["wishbone"])
self.add_wb_master(self.etherbone.master.bus)
# USB <--> TLP -------------------------------------------------------------------------
self.submodules.tlp = TLP(self.usb_core, self.usb_map["tlp"])
self.comb += [
self.pcie_phy.source.connect(self.tlp.sender.sink),
self.tlp.receiver.source.connect(self.pcie_phy.sink)
]
# Wishbone --> MSI -------------------------------------------------------------------------
self.submodules.msi = MSI()
self.comb += self.msi.source.connect(self.pcie_phy.msi)
self.add_csr("msi")
# Led blink --------------------------------------------------------------------------------
usb_counter = Signal(32)
self.sync.usb += usb_counter.eq(usb_counter + 1)
self.comb += platform.request("user_led", 0).eq(usb_counter[26])
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += platform.request("user_led", 1).eq(pcie_counter[26])
# Analyzer ---------------------------------------------------------------------------------
if with_analyzer:
analyzer_signals = [
self.pcie_phy.sink,
self.pcie_phy.source,
]
self.submodules.analyzer = LiteScopeAnalyzer(
analyzer_signals, 1024, csr_csv="test/analyzer.csv")
self.add_csr("analyzer")
def __init__(self,
platform,
with_cpu=False,
with_analyzer=True,
with_loopback=False):
clk_freq = int(100e6)
SoCSDRAM.__init__(self,
platform,
clk_freq,
cpu_type="lm32" if with_cpu else None,
integrated_rom_size=0x8000 if with_cpu else 0,
integrated_sram_size=0x8000,
with_uart=with_cpu,
ident="PCIe Injector example design",
with_timer=with_cpu)
self.submodules.crg = _CRG(platform)
if not with_cpu:
# use serial as wishbone bridge when no cpu
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
clk_freq,
baudrate=3000000))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# sdram
self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
sdram_module = MT41K256M16(self.clk_freq, "1:4")
self.register_sdram(self.ddrphy, sdram_module.geom_settings,
sdram_module.timing_settings)
# pcie endpoint
self.submodules.pciephy = S7PCIEPHY(platform,
platform.request("pcie_x1"),
cd="sys")
# usb core
usb_pads = platform.request("usb_fifo")
# self.submodules.usb_phy = FT245PHYSynchronous(usb_pads, clk_freq, fifo_depth=16)
self.submodules.usb_phy = FT601Sync(usb_pads, dw=32, timeout=1024)
if with_loopback:
self.submodules.usb_loopback_fifo = stream.SyncFIFO(
phy_description(32), 2048)
self.comb += [
self.usb_phy.source.connect(self.usb_loopback_fifo.sink),
self.usb_loopback_fifo.source.connect(self.usb_phy.sink)
]
else:
self.submodules.usb_core = USBCore(self.usb_phy, clk_freq)
# usb <--> wishbone
self.submodules.etherbone = Etherbone(self.usb_core,
self.usb_map["wishbone"])
self.add_wb_master(self.etherbone.master.bus)
# usb <--> tlp
self.submodules.tlp = TLP(self.usb_core, self.usb_map["tlp"])
self.comb += [
self.pciephy.source.connect(self.tlp.sender.sink),
self.tlp.receiver.source.connect(self.pciephy.sink)
]
# wishbone --> msi
self.submodules.msi = MSI()
self.comb += self.msi.source.connect(self.pciephy.msi)
# led blink
usb_counter = Signal(32)
self.sync.usb += usb_counter.eq(usb_counter + 1)
self.comb += platform.request("user_led", 0).eq(usb_counter[26])
pcie_counter = Signal(32)
self.sync.pcie += pcie_counter.eq(pcie_counter + 1)
self.comb += platform.request("user_led", 1).eq(pcie_counter[26])
# timing constraints
self.crg.cd_sys.clk.attr.add("keep")
self.crg.cd_usb.clk.attr.add("keep")
self.platform.add_period_constraint(self.crg.cd_sys.clk, 10.0)
self.platform.add_period_constraint(self.crg.cd_usb.clk, 10.0)
self.platform.add_period_constraint(
self.platform.lookup_request("pcie_x1").clk_p, 10.0)
if with_analyzer:
analyzer_signals = [
self.pciephy.sink.valid, self.pciephy.sink.ready,
self.pciephy.sink.last, self.pciephy.sink.dat,
self.pciephy.sink.be, self.pciephy.source.valid,
self.pciephy.source.ready, self.pciephy.source.last,
self.pciephy.source.dat, self.pciephy.source.be
]
self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals,
1024,
cd="sys")