reg_write32b(RegAddr.REG_RXSLIDE,0)
# Calculate the recommended topbot value, according to the phase between them.
if phase[1]==1:
if phase[0]==0:
topbot_final=1
else:
topbot_final=0
else:
if phase[5]==0:
topbot_final=0
else:
topbot_final=1
print phase
if topbot_final==1:
# If recommended value is 1, then shift phase by 5
reg_read32b(RegAddr.REG_TOPBOT)
reg_write1b(RegAddr.REG_TOPBOT,ch,1)
reg_read32b(RegAddr.REG_TOPBOT)
for i in range(5):
reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
reg_write32b(RegAddr.REG_RXSLIDE,0)
reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
reg_write32b(RegAddr.REG_RXSLIDE,0)
#print "aaa"
# Print the final 10 phases sampled results
for i in range(10):
phase[i]=reg_read1b(RegAddr.REG_CLK_SAMPLED,ch)
reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
reg_write32b(RegAddr.REG_RXSLIDE,0)
reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
reg_write32b(RegAddr.REG_RXSLIDE, 0) reg_write32b(RegAddr.REG_RXSLIDE, 2**ch) reg_write32b(RegAddr.REG_RXSLIDE, 0) reg_write32b(RegAddr.REG_RXSLIDE, 2**ch) reg_write32b(RegAddr.REG_RXSLIDE, 0) reg_write32b(RegAddr.REG_RXSLIDE, 2**ch) reg_write32b(RegAddr.REG_RXSLIDE, 0) reg_write32b(RegAddr.REG_RXSLIDE, 2**ch) reg_write32b(RegAddr.REG_RXSLIDE, 0) reg_write32b(RegAddr.REG_RXSLIDE, 2**ch) reg_write32b(RegAddr.REG_RXSLIDE, 0) reg_write32b(RegAddr.REG_RXSLIDE, 2**ch) reg_write32b(RegAddr.REG_RXSLIDE, 0) reg_write32b(RegAddr.REG_RXSLIDE, 2**ch) reg_write32b(RegAddr.REG_RXSLIDE, 0) reg_write32b(RegAddr.REG_RXSLIDE, 2**ch) reg_write32b(RegAddr.REG_RXSLIDE, 0) reg_write32b(RegAddr.REG_RXSLIDE, 2**ch) reg_write32b(RegAddr.REG_RXSLIDE, 0) reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 1) #time.sleep(0.1) reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 0) time.sleep(1) ret = reg_read32b(RegAddr.REG_RX_ALIGNMENT_DONE) print "RX_LOCK is " + str(ret) reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 2) time.sleep(1) reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 0)
# print "oddeven is "+str(oddeven)
reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
reg_write32b(RegAddr.REG_RXSLIDE,0)
reg_write32b(RegAddr.REG_RXSLIDE,2**ch)
reg_write32b(RegAddr.REG_RXSLIDE,0)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,1)
# time.sleep(0.1)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,0)
# time.sleep(timewait)
ret=reg_read1b(RegAddr.REG_RX_ALIGNMENT_DONE,ch)
else:
bot_find=0
phase_cnt=0
else:
phase_cnt=0
bot_find=1
topbot_final=1 # bot
'''
#print "aaa"
reg_read32b(RegAddr.REG_TOPBOT)
#print "bbb"
reg_read32b(RegAddr.REG_ODDEVEN)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 1)
#time.sleep(0.1)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 0)
time.sleep(timewait)
ret = reg_read32b(RegAddr.REG_RX_ALIGNMENT_DONE)
print "RX_LOCK is " + str(ret)
print "oddeven is " + str(oddeven)
print "topbot is " + str(topbot_final)
else:
print "bbb"
reg_write64b(RegAddr.REG_TX_CXP1_FORMAT, 0x00000000000000)
reg_write64b(RegAddr.REG_RX_CXP1_FORMAT, 0x00000000000000)
reg_write32b(RegAddr.REG_TXOPT_CXP1_LOW, 0x000000)
reg_write32b(RegAddr.REG_TXOPT_CXP2_LOW, 0x000000)
reg_write32b(RegAddr.REG_RXOPT_CXP1_LOW, 0x000000)
reg_write32b(RegAddr.REG_RXOPT_CXP2_LOW, 0x000000)
print "GBT TX reset..."
reg_write32b(RegAddr.REG_GBTTXRST, 0xFFF0FFF)
time.sleep(0.5)
reg_write32b(RegAddr.REG_GBTTXRST, 0)
time.sleep(1)
print "GBT RX reset..."
reg_write32b(RegAddr.REG_GBTRXRST, 0xFFF0FFF)
time.sleep(0.5)
reg_write32b(RegAddr.REG_GBTRXRST, 0)
time.sleep(1)
OUTSEL = reg_read32b(RegAddr.REG_OUTSEL_CALC)
print OUTSEL
reg_write32b(RegAddr.REG_OUT_SEL, int(OUTSEL, 16))
time.sleep(0.5)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 3)
time.sleep(0.5)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 0)
reg_write64b(RegAddr.REG_TX_CXP1_FORMAT,0x00000000000000)
reg_write64b(RegAddr.REG_RX_CXP1_FORMAT,0x00000000000000)
reg_write32b(RegAddr.REG_TXOPT_CXP1_LOW,0xFFFFFF)
reg_write32b(RegAddr.REG_TXOPT_CXP2_LOW,0xFFFFFF)
reg_write32b(RegAddr.REG_RXOPT_CXP1_LOW,0x000000)
reg_write32b(RegAddr.REG_RXOPT_CXP2_LOW,0x000000)
print "GBT TX reset..."
reg_write32b(RegAddr.REG_GBTTXRST,0xFFF0FFF)
time.sleep(0.5)
reg_write32b(RegAddr.REG_GBTTXRST,0)
time.sleep(1)
print "GBT RX reset..."
reg_write32b(RegAddr.REG_GBTRXRST,0xFFF0FFF)
time.sleep(0.5)
reg_write32b(RegAddr.REG_GBTRXRST,0)
time.sleep(1)
OUTSEL=reg_read32b(RegAddr.REG_OUTSEL_CALC)
print OUTSEL
reg_write32b(RegAddr.REG_OUT_SEL,int(OUTSEL,16))
time.sleep(0.5)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,3)
time.sleep(0.5)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,0)
for ch in range(4):
print ch
if np.mod(ch,4)==0:
os.system("python gbt_config_master.py " + str(ch))
else:
os.system("python gbt_config_slave.py " + str(ch))
print "GBT RX reset for all channels..."
reg_write32b(RegAddr.REG_GBTRXRST,0xFFF0FFF)
time.sleep(0.5)
reg_write32b(RegAddr.REG_GBTRXRST,0)
time.sleep(1)
print "Calculate the recommended selection for descrambler output multiplexer..."
OUTSEL=reg_read32b(RegAddr.REG_OUTSEL_CALC)
print "Calculated value for all channels " + OUTSEL
reg_write32b(RegAddr.REG_OUT_SEL,int(OUTSEL,16))
print "Recheck the RX alignment..."
time.sleep(0.5)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,1)
time.sleep(0.5)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST,0)
time.sleep(timewait)
ret=reg_read32b(RegAddr.REG_RX_ALIGNMENT_DONE)
'''
print "GBT RX alignment channel by channel..."
for ch in range(4):
print ch
os.system("python gbt_config.py " + str(ch))
'''
print "GBT RX reset for all channels..."
reg_write32b(RegAddr.REG_GBTRXRST, 0xFFF0FFF)
time.sleep(0.5)
reg_write32b(RegAddr.REG_GBTRXRST, 0)
time.sleep(1)
print "Calculate the recommended selection for descrambler output multiplexer..."
OUTSEL = reg_read32b(RegAddr.REG_OUTSEL_CALC)
print "Calculated value for all channels " + OUTSEL
reg_write32b(RegAddr.REG_OUT_SEL, int(OUTSEL, 16))
print "Recheck the RX alignment..."
time.sleep(0.5)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 1)
time.sleep(0.5)
reg_write32b(RegAddr.REG_RX_ALIGN_CHK_RST, 0)
time.sleep(timewait)
ret = reg_read32b(RegAddr.REG_RX_ALIGNMENT_DONE)
a = 1
