if args.cpu == "kvm":
cpu_type = CPUTypes.KVM
elif args.cpu == "atomic":
cpu_type = CPUTypes.ATOMIC
elif args.cpu == "timing":
cpu_type = CPUTypes.TIMING
elif args.cpu == "o3":
cpu_type = CPUTypes.O3
else:
raise NotImplementedError(
"CPU type '{}' is not supported in the boot tests.".format(args.cpu)
)
assert cpu_type != None
processor = SimpleProcessor(cpu_type=cpu_type, num_cores=args.num_cpus)
# Setup the motherboard.
motherboard = X86Board(
clk_freq="3GHz",
processor=processor,
memory=memory,
cache_hierarchy=cache_hierarchy,
)
kernal_args = motherboard.get_default_kernel_args()
if args.boot_type == "init":
kernal_args.append("init=/root/exit.sh")
# Set the Full System workload.
motherboard.set_kernel_disk_workload(
from gem5.components.cachehierarchies.classic.private_l1_private_l2_cache_hierarchy \
import (
PrivateL1PrivateL2CacheHierarchy,
)
# Setup the cache hierarchy. PrivateL1PrivateL2 and NoCache have been tested.
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(l1d_size="32KiB",
l1i_size="32KiB",
l2_size="512KiB")
# Setup the system memory.
memory = SingleChannelDDR3_1600()
# Setup a single core Processor.
processor = SimpleProcessor(cpu_type=cpu, num_cores=1)
# Setup the board.
board = RiscvBoard(clk_freq="1GHz",
processor=processor,
memory=memory,
cache_hierarchy=cache_hierarchy,
use_disk_image=False)
board.connect_things()
# Set the Full System workload.
board.set_workload(disk_image=None,
bootloader=bbl,
kernel_boot_params="console=ttyS0")
def input_to_cputype(input: str) -> CPUTypes:
if input == "kvm":
return CPUTypes.KVM
elif input == "timing":
return CPUTypes.TIMING
elif input == "atomic":
return CPUTypes.ATOMIC
elif input == "o3":
return CPUTypes.O3
else:
raise NotADirectoryError("Unknown CPU type '{}'.".format(input))
# Setup the system.
cache_hierarchy = NoCache()
memory = SingleChannelDDR3_1600()
processor = SimpleProcessor(cpu_type=input_to_cputype(args.cpu), num_cores=1)
motherboard = SimpleBoard(
clk_freq="3GHz",
processor=processor,
memory=memory,
cache_hierarchy=cache_hierarchy,
)
# Set the workload
binary = Resource(args.resource,
resource_directory=args.resource_directory)
motherboard.set_se_binary_workload(binary)
# Run the simulation
simulator = Simulator(board=motherboard, full_system=False)
PrivateL1PrivateL2CacheHierarchy,
)
# Here we setup the parameters of the l1 and l2 caches.
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(
l1d_size="16kB",
l1i_size="16kB",
l2_size="256kB",
)
# Memory: Dual Channel DDR4 2400 DRAM device.
memory = DualChannelDDR4_2400(size="3GB")
# Here we setup the processor. We use a simple processor.
processor = SimpleProcessor(
cpu_type=CPUTypes.TIMING,
num_cores=2,
)
# Here we setup the board. The RiscvBoard allows for Full-System RISCV
# simulations.
board = RiscvBoard(
clk_freq="3GHz",
processor=processor,
memory=memory,
cache_hierarchy=cache_hierarchy,
)
# Here we set the Full System workload.
# The `set_kernel_disk_workload` function for the RiscvBoard accepts a
# RISCV bootloader and a disk image. Once the system successfully boots, it
required=False,
default=m5.MaxTick,
help="The maximum number of ticks to simulate. Used for testing.",
)
args = parser.parse_args()
cache_hierarchy = PrivateL1PrivateL2CacheHierarchy(l1d_size="32KiB",
l1i_size="32KiB",
l2_size="512KiB")
# Setup the system memory.
memory = SingleChannelDDR3_1600(size="128MB")
# Setup a single core Processor.
if args.cpu_type == "atomic":
processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC,
num_cores=args.num_cpus)
elif args.cpu_type == "timing":
processor = SimpleProcessor(cpu_type=CPUTypes.TIMING,
num_cores=args.num_cpus)
# Setup the board.
board = LupvBoard(
clk_freq="1GHz",
processor=processor,
memory=memory,
cache_hierarchy=cache_hierarchy,
)
# Set the Full System workload.
board.set_kernel_disk_workload(
kernel=Resource("riscv-lupio-linux-kernel"),