def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Checking column mux port 0")
tx = factory.create(module_type="single_level_column_mux",
tx_size=8,
bitcell_bl="bl0",
bitcell_br="br0")
self.local_check(tx)
debug.info(2, "Checking column mux port 1")
tx = factory.create(module_type="single_level_column_mux",
tx_size=8,
bitcell_bl="bl1",
bitcell_br="br1")
self.local_check(tx)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check precharge array in multi-port
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
factory.reset()
debug.info(
2, "Checking 3 column precharge array for 1RW/1R bitcell (port 0)")
pc = factory.create(module_type="precharge_array",
columns=3,
bitcell_bl="bl0",
bitcell_br="br0")
self.local_check(pc)
debug.info(
2, "Checking 3 column precharge array for 1RW/1R bitcell (port 1)")
pc = factory.create(module_type="precharge_array",
columns=3,
bitcell_bl="bl0",
bitcell_br="br0",
column_offset=1)
self.local_check(pc)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.analytical_delay = False
OPTS.netlist_only = True
OPTS.trim_netlist = False
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
globals.setup_bitcell()
# This is a hack to reload the characterizer __init__ with the spice version
from importlib import reload
import characterizer
reload(characterizer)
from characterizer import functional
from sram_config import sram_config
c = sram_config(word_size=8, num_words=16, write_size=2, num_banks=1)
c.words_per_row = 1
c.recompute_sizes()
debug.info(
1,
"Functional test for sram with {} bit words, {} words, {} words per row, {} bit writes, {} banks"
.format(c.word_size, c.num_words, c.words_per_row, c.write_size,
c.num_banks))
s = factory.create(module_type="sram", sram_config=c)
tempspice = OPTS.openram_temp + "sram.sp"
s.sp_write(tempspice)
f = functional(s.s, tempspice)
(fail, error) = f.run()
self.assertTrue(fail, error)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
OPTS.bitcell = "pbitcell"
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 1
globals.setup_bitcell()
c = sram_config(word_size=4,
num_words=64,
num_banks=1)
c.num_words=64
c.words_per_row=4
c.recompute_sizes()
debug.info(1, "Layout test for {}rw,{}r,{}w psram "
"with {} bit words, {} words, {} words per "
"row, {} banks".format(OPTS.num_rw_ports,
OPTS.num_r_ports,
OPTS.num_w_ports,
c.word_size,
c.num_words,
c.words_per_row,
c.num_banks))
a = factory.create(module_type="sram", sram_config=c)
self.local_check(a, final_verification=True)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing replica column for 6t_cell")
a = factory.create(module_type="replica_column",
rows=4,
left_rbl=1,
right_rbl=0,
replica_bit=1)
self.local_check(a)
debug.info(2, "Testing replica column for 6t_cell")
a = factory.create(module_type="replica_column",
rows=4,
left_rbl=1,
right_rbl=1,
replica_bit=6)
self.local_check(a)
debug.info(2, "Testing replica column for 6t_cell")
a = factory.create(module_type="replica_column",
rows=4,
left_rbl=2,
right_rbl=0,
replica_bit=2)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2,
"Testing sense_amp_array for word_size=4, words_per_row=1")
a = factory.create(module_type="sense_amp_array",
word_size=4,
words_per_row=1)
self.local_check(a)
debug.info(2,
"Testing sense_amp_array for word_size=4, words_per_row=2")
a = factory.create(module_type="sense_amp_array",
word_size=4,
words_per_row=2)
self.local_check(a)
debug.info(2,
"Testing sense_amp_array for word_size=4, words_per_row=4")
a = factory.create(module_type="sense_amp_array",
word_size=4,
words_per_row=4)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(1, "Testing sample for 2-way column_mux_array port 0")
a = factory.create(module_type="column_mux_array",
columns=8,
word_size=4,
bitcell_bl="bl0",
bitcell_br="br0")
self.local_check(a)
debug.info(1, "Testing sample for 2-way column_mux_array port 1")
a = factory.create(module_type="column_mux_array",
columns=8,
word_size=4,
bitcell_bl="bl1",
bitcell_br="br1")
self.local_check(a)
debug.info(1, "Testing sample for 4-way column_mux_array port 0")
a = factory.create(module_type="column_mux_array",
columns=8,
word_size=2,
bitcell_bl="bl0",
bitcell_br="br0")
self.local_check(a)
debug.info(1, "Testing sample for 4-way column_mux_array port 1")
a = factory.create(module_type="column_mux_array",
columns=8,
word_size=2,
bitcell_bl="bl1",
bitcell_br="br1")
self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array port 0")
a = factory.create(module_type="column_mux_array",
columns=16,
word_size=2,
bitcell_bl="bl0",
bitcell_br="br0")
self.local_check(a)
debug.info(1, "Testing sample for 8-way column_mux_array port 1")
a = factory.create(module_type="column_mux_array",
columns=16,
word_size=2,
bitcell_bl="bl1",
bitcell_br="br1")
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(
2,
"Testing 4x4 local bitcell array for cell_1rw_1r without replica")
a = factory.create(module_type="local_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1])
self.local_check(a)
debug.info(
2,
"Testing 4x4 local bitcell array for cell_1rw_1r with replica column"
)
a = factory.create(module_type="local_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],
right_rbl=[1])
self.local_check(a)
debug.info(
2,
"Testing 4x4 local bitcell array for cell_1rw_1r with replica column"
)
a = factory.create(module_type="local_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],
left_rbl=[0])
self.local_check(a)
debug.info(
2,
"Testing 4x4 local bitcell array for cell_1rw_1r with replica column"
)
a = factory.create(module_type="local_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],
left_rbl=[0],
right_rbl=[1])
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
from sram_config import sram_config
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
c = sram_config(word_size=4, num_words=16)
c.words_per_row = 1
factory.reset()
c.recompute_sizes()
debug.info(1, "No column mux")
a = factory.create("port_data", sram_config=c, port=0)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
self.local_check(a)
c.num_words = 32
c.words_per_row = 2
factory.reset()
c.recompute_sizes()
debug.info(1, "Two way column mux")
a = factory.create("port_data", sram_config=c, port=0)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
self.local_check(a)
c.num_words = 64
c.words_per_row = 4
factory.reset()
c.recompute_sizes()
debug.info(1, "Four way column mux")
a = factory.create("port_data", sram_config=c, port=0)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
self.local_check(a)
c.word_size = 2
c.num_words = 128
c.words_per_row = 8
factory.reset()
c.recompute_sizes()
debug.info(1, "Eight way column mux")
a = factory.create("port_data", sram_config=c, port=0)
self.local_check(a)
a = factory.create("port_data", sram_config=c, port=1)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(1, "Testing sample for hierarchy_predecode2x4")
a = factory.create(module_type="hierarchical_predecode2x4")
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing 4x4 array for cell_1rw_1r")
a = factory.create(module_type="bitcell_array", cols=4, rows=4)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Checking 1x size decoder inverter")
tx = factory.create(module_type="pinv_dec", size=1)
self.local_check(tx)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
global verify
import verify
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing and2_dec gate")
a = factory.create(module_type="and2_dec")
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check hierarchical decoder for multi-port
OPTS.num_rw_ports = 1
OPTS.num_w_ports = 0
OPTS.num_r_ports = 0
globals.setup_bitcell()
factory.reset()
debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
self.local_check(a)
factory.reset()
debug.info(1, "Testing 17 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
self.local_check(a)
factory.reset()
debug.info(1, "Testing 23 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=23)
self.local_check(a)
debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
self.local_check(a)
factory.reset()
debug.info(1, "Testing 65 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=65)
self.local_check(a)
debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=128)
self.local_check(a)
factory.reset()
debug.info(1, "Testing 341 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=341)
self.local_check(a)
debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)")
a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing 4x4 non-replica array for cell_1rw_1r")
a = factory.create(module_type="replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1])
self.local_check(a)
debug.info(2, "Testing 4x4 left replica array for cell_1rw_1r")
a = factory.create(module_type="replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],
left_rbl=[0])
self.local_check(a)
debug.info(2,
"Testing 4x4 array left and right replica for cell_1rw_1r")
a = factory.create(module_type="replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],
left_rbl=[0],
right_rbl=[1])
self.local_check(a)
# Sky 130 has restrictions on the symmetries
if OPTS.tech_name != "sky130":
debug.info(2,
"Testing 4x4 array right only replica for cell_1rw_1r")
a = factory.create(module_type="replica_bitcell_array",
cols=4,
rows=4,
rbl=[1, 1],
right_rbl=[1])
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 0
OPTS.num_w_ports = 0
globals.setup_bitcell()
# Checks 2x4 and 2-input NAND decoder
debug.info(1, "Testing 16 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=16)
self.local_check(a)
# Checks 2x4 and 2-input NAND decoder with non-power-of-two
debug.info(1, "Testing 17 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=17)
self.local_check(a)
# Checks 2x4 with 3x8 and 2-input NAND decoder
debug.info(1, "Testing 32 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=32)
self.local_check(a)
# Checks 3 x 2x4 and 3-input NAND decoder
debug.info(1, "Testing 64 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=64)
self.local_check(a)
# Checks 2x4 and 2 x 3x8 and 3-input NAND with non-power-of-two
debug.info(1, "Testing 132 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=132)
self.local_check(a)
# Checks 3 x 3x8 and 3-input NAND decoder
debug.info(1, "Testing 512 row sample for hierarchical_decoder")
a = factory.create(module_type="hierarchical_decoder", num_outputs=512)
self.local_check(a)
# Checks 3 x 4x16 and 4-input NAND decoder
# debug.info(1, "Testing 4096 row sample for hierarchical_decoder")
# a = factory.create(module_type="hierarchical_decoder", num_outputs=4096)
# self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
a = factory.create(module_type="write_driver_array", columns=8, word_size=8)
self.local_check(a)
debug.info(2, "Testing write_driver_array for columns=16, word_size=8")
a = factory.create(module_type="write_driver_array", columns=16, word_size=8)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# Use the 2 port cell since it is usually bigger/easier
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
# check wordline driver for single port
debug.info(2, "Checking driver")
tx = factory.create(module_type="wordline_driver_array",
rows=8,
cols=32)
self.local_check(tx)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# Use the 2 port cell since it is usually bigger/easier
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(1, "Port address 16 rows")
a = factory.create("port_address", cols=16, rows=16)
self.local_check(a)
debug.info(1, "Port address 256 rows")
a = factory.create("port_address", cols=256, rows=256)
self.local_check(a)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
# check precharge array in multi-port
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Checking precharge for 1rw1r port 0")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl0", bitcell_br="br0")
self.local_check(tx)
factory.reset()
debug.info(2, "Checking precharge for 1rw1r port 1")
tx = factory.create(module_type="precharge", size=1, bitcell_bl="bl1", bitcell_br="br1")
self.local_check(tx)
globals.end_openram()
def runTest(self):
config_file = "{}/tests/configs/config".format(
os.getenv("OPENRAM_HOME"))
globals.init_openram(config_file)
OPTS.num_rw_ports = 1
OPTS.num_r_ports = 1
OPTS.num_w_ports = 0
globals.setup_bitcell()
debug.info(2, "Testing one left replica column for dual port")
a = factory.create(module_type="replica_column",
rows=4,
rbl=[1, 0],
replica_bit=1)
self.local_check(a)
debug.info(2, "Testing one right replica column for dual port")
a = factory.create(module_type="replica_column",
rows=4,
rbl=[0, 1],
replica_bit=5)
self.local_check(a)
debug.info(2,
"Testing two (left, right) replica columns for dual port")
a = factory.create(module_type="replica_column",
rows=4,
rbl=[1, 1],
replica_bit=1)
self.local_check(a)
debug.info(2,
"Testing two (left, right) replica columns for dual port")
a = factory.create(module_type="replica_column",
rows=4,
rbl=[1, 1],
replica_bit=6)
self.local_check(a)
globals.end_openram()
(OPTS, args) = g.parse_args()
# Check that we are left with a single configuration file as argument.
if len(args) != 1:
print(g.USAGE)
sys.exit(2)
# These depend on arguments, so don't load them until now.
import debug
# Parse config file and set up all the options
g.init_openram(config_file=args[0], is_unit_test=False)
# Ensure that the right bitcell exists or use the parameterised one
g.setup_bitcell()
# Only print banner here so it's not in unit tests
g.print_banner()
# Keep track of running stats
start_time = datetime.datetime.now()
g.print_time("Start", start_time)
# Output info about this run
g.report_status()
from sram_config import sram_config
# Configure the SRAM organization