def process(self, root='.'):
if not isfile(self.vcd):
raise HandlerError(
'Vcd2Pff: Could not find the target VCD file {}'.format(
realpath(self.vcd)))
if not isfile(self.iox):
raise HandlerError(
'Vcd2Pff: Could not find the target IOX file {}'.format(
realpath(self.iox)))
if not self.o:
self.o = self.vcd[:-4] + '.pff'
self.prec = Handler.getTime(self.prec)
self.period = self.tclk * self.nclk
self.prepareFile(self.o)
command = '{} {} {} {} -p {} -d {} -z /'.format(
self.BIN, self.vcd, self.iox, self.o, self.period, self.d)
if self.useTrig:
command += ' -u -t {}'.format(self.trig)
else:
command += ' -s {} -f {}'.format(
self.start, self.start + self.nFrames * self.period)
command += ' -N "{}"'.format(self.note)
update = {}
try:
message = check_output(command.split()).decode('utf-8')
except subprocess.CalledProcessError as e:
message = 'Command: ' + ' '.join(
e.cmd) + '\n Return code: {:02x}'.format(e.returncode)
message = self.handle + ': \n' + '\n'.join(
['\t+ ' + m for m in message.split('\n')])
return message, update
def process(self, root):
message = ''
update = {}
self.root = root
# prepare for output
vcdfile = join(self.root, self.vcd)
tclfile = join(self.root, self.tcl)
self.prepareFile(tclfile)
self.createFile(tclfile, '# ')
fp = open(tclfile, 'a')
fp.write('transcript off\n')
fp.write('\n')
fp.write('set root ' + self.root + '\n')
if self.stage != 'rtl':
fp.write('set lib_top ' + self.lib_top + '\n')
fp.write('\n')
lib = '{}_{}_lib'.format(self.design, self.stage)
fp.write('vlib {}\n'.format(lib))
# library resource
# todo
if self.stage != 'rtl':
for libsrc in self.lib:
if self.lang == 'verilog':
fp.write(
'vlog $lib_top/{} -work {} +time_mode_zero\n'.format(
libsrc, lib))
elif self.lang == 'vhdl':
fp.write('vcom $lib_top/{} -work {}\n'.format(libsrc, lib))
else:
raise HandlerError('Unknown HDL {}.'.format(self.lang))
# sources
fp.write('\n# sources\n')
for src in self.src:
srcfile = join(self.root, src)
if not isfile(srcfile):
print(
'Warning: Source file could not be found on disk!\n -> {}'.
format(realpath(src)))
if src[-2:] == '.v':
fp.write('vlog $root/{} -work {} +time_mode_zero\n'.format(
src, lib))
elif src[-4:] == '.vhd':
fp.write('vcom $root/{} -work {}\n'.format(src, lib))
# tbench
tbfile = join(self.root, self.tb)
if not isfile(tbfile):
print(
'Warning: Testbench file could not be found on disk!\n -> {}'.
format(tbfile))
if self.tb[-2:] == '.v':
fp.write('vlog $root/{} -work {}\n'.format(self.tb, lib))
elif self.tb[-4:] == '.vhd':
fp.write('vcom $root/{} -work {}\n'.format(self.tb, lib))
# print (Handler.getTime(self.cpath), self.tclk, self.nclk, Handler.getTime(self.prec))
if self.tclk * Handler.getTime(self.prec) < Handler.getTime(
self.cpath):
print(
'Warning: Simulation clock violates critical path of the design.'
)
ack = input('Set simulation:tclk to critical path? [yes/no] ')
if ack == 'yes':
self.tclk = int(
Handler.getTime(self.cpath) / Handler.getTime(self.prec))
update['simulation:tclk'] = self.tclk
print('Info: Simulation clock will be updated.')
else:
print('Info: Critical path will be violated.')
period = self.nclk * self.tclk
rstdelay = period
initdelay = period
start = rstdelay + initdelay
finish = start + self.nframes * period
if self.rstdelay != rstdelay:
self.rstdelay = rstdelay
update['test:rstdelay'] = self.rstdelay
if self.initdelay != initdelay:
self.initdelay = initdelay
update['test:initdelay'] = self.initdelay
if self.start != start:
self.start = start
update['test:start'] = self.start
if self.finish != finish:
self.finish = finish
update['test:finish'] = self.finish
# run and finish
fp.write('\n# simulation parameters\n')
fp.write('vsim {}.{}'.format(lib, self.tbmodule))
fp.write('\\\n -t {}'.format(self.prec))
fp.write('\\\n -gTCLK={}'.format(
self.tclk)) # see tbgen, these generics have fixed names
fp.write('\\\n -gPERIOD={}'.format(
period)) # see tbgen, these generics have fixed names
fp.write('\\\n -gN_FRAMES={}'.format(
self.nframes)) # see tbgen, these generics have fixed names
if self.rst:
fp.write('\\\n -gRST_DELAY={}'.format(
self.rstdelay)) # see tbgen, these generics have fixed names
fp.write('\\\n -gINIT_DELAY={}'.format(
self.initdelay)) # see tbgen, these generics have fixed names
if not self.novopt_off:
fp.write('\\\n -novopt')
if self.noglitch:
fp.write('\\\n -noglitch')
if self.stage not in ['rtl', 'zero']:
if self.sdfnoerror:
fp.write('\\\n -sdfnoerror')
fp.write('\\\n -sdf{} {}=$root/{}'.format(self.sdfcorner,
self.sdfstrip,
self.sdf))
fp.write('\n')
fp.write('\n')
fp.write('onerror {resume}\n')
fp.write('quietly WaveActivateNextPane {} 0\n')
fp.write('TreeUpdate [SetDefaultTree]\n')
fp.write('update\n')
fp.write('\n# simulation output\n')
fp.write('vcd file $root/{}\n'.format(self.vcd))
fp.write('vcd add {}\n'.format(self.tgt))
fp.write('vcd add {}\n'.format(self.tr))
fp.write('vcd add {}/*\n'.format(self.sdfstrip))
fp.write('\n# run and exit\n')
fp.write('run {}\n'.format(self.run))
fp.write('quit -sim\n')
fp.write('quit -f\n')
# end file
fp.close()
message = 'Script created at: ' + tclfile
if self.exe:
raise NotImplementedError('Take care of the pipe later')
# print('Info: Running QuestaSim found at: {}.'.format(QuestaSim.SOURCE))
# x = check_output('source {}; vsim -c -64 -do {}'.format(
# QuestaSim.SOURCE, self.tcl).split()).decode().strip()
# message = x
return message, update
