def test_verilog_pp_Language_is_bad(self):
with self.assertRaises(ValueError) as context:
c = HdlConvertor()
c.verilog_pp("", "badlang", [])
e = str(context.exception)
self.assertIn(
"'badlang' is not recognized (expected hdlConvertor.language.Language value)", e)
def test_verilog_pp_Language_is_bad(self):
with self.assertRaises(ValueError) as context:
c = HdlConvertor()
test_result = c.verilog_pp("", "", "badlang")
e = str(context.exception)
self.assertIn("badlang is not recognized (expected <enum 'Language'>)",
e)
def run_pp_by_methodname(self):
test_name = self.getTestName()
c = HdlConvertor()
f = path.join(path.dirname(__file__), 'sv_pp', 'raw', test_name + '.txt')
incdirs = [path.join('sv_pp', 'raw'), ]
res = c.verilog_pp(f, Language.SYSTEM_VERILOG, incdirs)
return res
def test_parser_Language_is_bad(self):
with self.assertRaises(ValueError) as context:
c = HdlConvertor()
c.parse(None, "bad", None)
e = str(context.exception)
self.assertIn(
"'bad' is not recognized (expected hdlConvertor.language.Language value)", e)
def run_pp_by_methodname(self):
test_name = self.getTestName()
c = HdlConvertor()
f = path.join(path.dirname(__file__), 'sv_pp', 'raw',
test_name + '.txt')
incdirs = ['.', '..', path.join('sv_pp', 'raw')]
return c.verilog_pp(f, incdirs, SV)
def _test_run(test_file, golden_file, golden_str):
c = HdlConvertor()
incdirs = [
path.join('sv_pp', 'src'),
]
with cd(TEST_DIR):
# cd to have nice paths in error messages
test_result = c.verilog_pp(test_file, Language.SYSTEM_VERILOG, incdirs)
# windows compatiblity
test_result = test_result.replace("sv_pp\\\\src\\\\", "sv_pp/src/")
# with open(os.path.join(TEST_DIR, golden_file), "w") as f:
# f.write(test_result)
if golden_file is not None:
assert golden_str is None
with open(os.path.join(TEST_DIR, golden_file)) as f:
test_golden = f.read()
else:
assert golden_str is not None
test_golden = golden_str
return test_result, test_golden
def assertPPError(self, file, err_msg, use_rel_path=False):
with self.assertRaises(ParseException) as context:
f = path.join(TEST_DIR, 'sv_pp', 'src', file)
c = HdlConvertor()
result = c.verilog_pp(
f, ['.', '..', path.join('sv_pp', 'src')], SV)
self.assertEqual(err_msg, context.exception.__str__())
def test_parser_Language_is_bad(self):
with self.assertRaises(ValueError) as context:
c = HdlConvertor()
test_result = c.parse(None, Language.SYSTEM_VERILOG_2012, None)
e = str(context.exception)
self.assertIn(
"Language.SYSTEM_VERILOG_2012 is not recognized (expected verilog, vhdl or systemVerilog",
e)
def _test_run(test_file, golden_file):
c = HdlConvertor()
test_result = c.verilog_pp(path.join(
TEST_DIR, test_file), ['.', '..', path.join('sv_pp', 'src')], SV)
with open(path.join(TEST_DIR, golden_file), 'r') as myfile:
test_golden = myfile.read()
myfile.close()
return test_result, test_golden
def parseFile(fname, language, input_dir=None):
input_dir = get_language_path(input_dir, language)
inc_dir = path.join(TEST_DIR, input_dir)
f = path.join(TEST_DIR, input_dir, fname)
c = HdlConvertor()
res = c.parse([
f,
], language, [inc_dir], debug=True)
return f, res
def test(self):
c = HdlConvertor()
incdirs = []
c.parse([
sv_file,
],
Language.SYSTEM_VERILOG_2017,
incdirs,
debug=False)
def parseFile(fname, language):
_language = language
if language == SV:
_language = VERILOG
inc_dir = path.join(TEST_DIR, _language.value)
f = path.join(BASE_DIR, "tests", _language.value, fname)
c = HdlConvertor()
res = c.parse([f, ], language, [inc_dir], debug=True)
return f, res
def test_multiple_files_at_once(self):
language = VERILOG
f = [path.join(TEST_DIR, language.value, f)
for f in ["fifo_rx.v", "define.v", "arbiter.v", "uart.v"]]
inc_dir = path.join(TEST_DIR, language.value)
c = HdlConvertor()
res = c.parse(f, language, [inc_dir], debug=True)
e = [ o for o in res.objs if isinstance(o, HdlModuleDef)]
self.assertSetEqual(set(_e.module_name for _e in e),
{'fifo_rx', 'test', 'arbiter', 'uart'})
str(res)
def test_FILE_LINE(self):
c = HdlConvertor()
test_result = c.verilog_pp(
path.join(path.dirname(__file__), 'sv_pp', 'src',
'test_FILE_LINE.sv'),
['.', '..', path.join('sv_pp', 'src')], SV)
test_golden = "module tb();\n\ninitial\n\t$display(\"Internal error: null handle at %s, line %d.\",\n"
test_golden += "\"" + path.join(
path.dirname(__file__), 'sv_pp', 'src',
'test_FILE_LINE.sv') + "\", 5);\n\n\nendmodule\n"
self.assertEqual(test_result, test_golden)
def _test_run(test_file, golden_file):
c = HdlConvertor()
incdirs = ['.', '..', path.join('sv_pp', 'src')]
test_result = c.verilog_pp(
test_file, incdirs, SV)
with open(golden_file) as myfile:
test_golden = myfile.read()
return test_result, test_golden
def test_FILE_LINE(self):
c = HdlConvertor()
f = path.join(path.dirname(__file__), 'sv_pp', 'src', 'test_FILE_LINE.sv')
incdirs = ['.', '..', path.join('sv_pp', 'src')]
test_result = c.verilog_pp(f, incdirs, SV)
expected_val = path.join(path.dirname(__file__),
'sv_pp', 'src', 'test_FILE_LINE.sv'
)
test_golden = ("module tb();\n\ninitial\n\t$display("
"\"Internal error: null handle at %s, line %d.\",\n")
test_golden += "\"" + expected_val + "\", 5);\n\n\nendmodule\n"
self.assertEqual(test_result, test_golden)
def run_test(self, file, incdirs):
c = HdlConvertor()
if not isinstance(file, list):
file = [
file,
]
f = path.join(SRC_DIR, *file)
res = c.verilog_pp(f, Language.VERILOG, incdirs)
ref_file = path.join(EXPECTED_DIR, *file)
with open(ref_file) as exp_f:
expected = exp_f.read()
self.assertEqual(res, expected)
def test_can_update(self):
c = HdlConvertor()
db = c.preproc_macro_db
db["SYMBOL0"] = "0"
db["SYMBOL1"] = "1"
db["SYMBOL2"] = "2"
keys = list(db.keys())
values = [(v.name, v.get_body()) for v in db.values()]
items = [(i[0], i[1].get_body()) for i in db.items()]
# [note] we know order as the std::map is ordered
self.assertEqual(keys, ["SYMBOL%d" % i for i in range(3)])
ref_values = [("SYMBOL%d" % i, "%d" % i) for i in range(3)]
self.assertEqual(values, ref_values )
self.assertEqual(items, ref_values )
# test_result = c.verilog_pp(
# test_file, Language.SYSTEM_VERILOG, incdirs)
del db["SYMBOL2"]
keys = list(db.keys())
self.assertEqual(keys, ["SYMBOL%d" % i for i in range(2)])
db.update({
"SYMBOL2": "2",
"SYMBOL3": "3",
})
keys = list(db.keys())
self.assertEqual(keys, ["SYMBOL%d" % i for i in range(4)])
self.assertIn("SYMBOL1", db)
self.assertNotIn("SYMBOL_9", db)
db.clear()
keys = list(db.keys())
self.assertEqual(keys, [])
def parseFile(fname, language):
if language.is_system_verilog():
lang_dir = os.path.join("sv_test", "others")
elif language.is_verilog():
lang_dir = "verilog"
elif language.is_vhdl():
lang_dir = "vhdl"
else:
raise ValueError(language)
inc_dir = path.join(TEST_DIR, lang_dir)
f = path.join(TEST_DIR, lang_dir, fname)
c = HdlConvertor()
res = c.parse([
f,
], language, [inc_dir], debug=True)
return f, res
def test(self):
c = HdlConvertor()
c.preproc_macro_db.update(test_spec.preproc_defs)
try:
c.parse([test_spec.main_file, ], test_spec.language,
test_spec.include_dirs, debug=test_spec.debug)
except Exception:
if test_spec.should_fail:
# [TODO] some expected erros in this test suite are not related to synatax
# need to check maually if the error really means syntax error and
# if this library is raising it correctly
pass
else:
raise
test_filter.mark_test_as_passed(self)
def assertPPError(self, file, err_msg, contains=False):
with self.assertRaises(ParseException) as context:
f = path.join(TEST_DIR, 'sv_pp', 'src', file)
c = HdlConvertor()
c.verilog_pp(f, [
path.join('sv_pp', 'src'),
], SV)
e = str(context.exception)
if contains:
self.assertIn(err_msg, e)
else:
self.assertGreaterEqual(len(e), len(err_msg))
_e = e[-len(err_msg):]
if err_msg != _e:
# print whole error if there is some problem
self.assertEqual(err_msg, e)
else:
self.assertEqual(err_msg, _e)
and o.module_name == last.name, (last, o)
self.print_module_body(o)
else:
raise NotImplementedError(o)
last = o
if __name__ == "__main__":
import os
import sys
BASE_DIR = os.path.join(os.path.dirname(__file__), "..")
TEST_DIR = os.path.join(BASE_DIR, 'tests', 'verilog')
from hdlConvertor.language import Language
from hdlConvertor import HdlConvertor
c = HdlConvertor()
filenames = [os.path.join(TEST_DIR, "arbiter_tb.v")]
#AES = os.path.join(BASE_DIR, "..", "aes")
#files = [
# # "aes_cipher_top.v",
# # "aes_key_expand_128.v",
# # "aes_inv_cipher_top.v", "aes_rcon.v",
# "test_bench_top.v",
# # "aes_inv_sbox.v", "aes_sbox.v",
#]
#
#filenames = [os.path.join(AES, f) for f in files]
d = c.parse(filenames, Language.VERILOG, [], False, True)
tv = ToVerilog(sys.stdout)
tv.print_context(d)
"""
:type context: HdlContext
"""
w = self.out.write
for o in context.objs:
if isinstance(o, HdlModuleDec):
w("\n")
self.print_module_header(o)
w("\n")
elif isinstance(o, HdlModuleDef):
self.print_module_body(o)
elif isinstance(o, HdlImport):
self.print_hdl_import(o)
else:
raise NotImplementedError(o)
if __name__ == "__main__":
import os
import sys
BASE_DIR = os.path.join(os.path.dirname(__file__), "..")
TEST_DIR = os.path.join(BASE_DIR, 'tests', 'vhdl')
from hdlConvertor.language import Language
from hdlConvertor import HdlConvertor
c = HdlConvertor()
filenames = [os.path.join(TEST_DIR, "mux.vhd")]
d = c.parse(filenames, Language.VHDL, [], False, False)
tv = ToVhdl(sys.stdout)
tv.print_context(d)
def test_can_recover_defines_from_verilog(self):
c = HdlConvertor()
c.verilog_pp_str("`define TEST_SYMBOL\n", Language.SYSTEM_VERILOG)
db = c.preproc_macro_db
self.assertIn("TEST_SYMBOL", db)
def test_define_and_use_in_preproc(self):
c = HdlConvertor()
db = c.preproc_macro_db
db["S0"] = "0"
res = c.verilog_pp_str("`S0", Language.SYSTEM_VERILOG)
self.assertEqual(res, "0")
import json
import re
import sys
import traceback
from collections import namedtuple
from hdlConvertor import HdlConvertor
from hdlConvertor.hdlAst import HdlModuleDef, HdlStmAssign, HdlCall
from hdlConvertor.language import Language
from hdlConvertor.toVhdl import ToVhdl
from circuits import DipCircuitLayoutSpec, BufferCircuitLayoutSpec, DFlipFlopCircuitLayoutSpec, CircuitSpec, SimCircuit, \
temp_name_generator
c = HdlConvertor()
filenames = ["vhdl/mux.vhd", ]
include_dirs = []
d = c.parse(filenames, Language.VHDL, include_dirs, hierarchyOnly=False, debug=True)
def flatten_visitor(node, name_gen, root_children):
assert isinstance(node, HdlStmAssign)
if isinstance(node.src, HdlCall):
for i, op in enumerate(node.src.ops):
if isinstance(op, HdlCall):
t = next(name_gen)
gen_assign = HdlStmAssign(op, t)
flatten_visitor(gen_assign, name_gen, root_children)
def main(std_ver, include_dirs, files):
c = HdlConvertor()
# c.preproc_macro_db.update(preproc_defs)
if include_dirs is None:
include_dirs = []
c.parse(files, std_ver, include_dirs)
