def visit_HdlStmCase(self, o):
"""
:type o: HdlStmCase
:return: True if requires ;\n after end
"""
self.visit_doc(o)
w = self.out.write
if o.type != HdlStmCaseType.CASE:
raise NotImplementedError()
w("switch(")
self.visit_iHdlExpr(o.switch_on)
w(") {\n")
cases = o.cases
for k, stms in cases:
w("case ")
self.visit_iHdlExpr(k)
w(":")
with Indent(self.out):
need_semi = self.visit_iHdlStatement_in_statement(stms)
if need_semi:
w(";\n")
else:
w("\n")
defal = o.default
if defal is not None:
w("default:")
with Indent(self.out):
need_semi = self.visit_iHdlStatement_in_statement(defal)
if need_semi:
w(";\n")
else:
w("\n")
w("}")
return False
def visit_HdlModuleDef(self, a):
"""
:type a: HdlModuleDef
"""
mod_dec = a.dec
assert mod_dec is not None, a
assert not mod_dec.objs, mod_dec
self.visit_doc(mod_dec)
w = self.out.write
w("module ")
w(mod_dec.name)
gs = mod_dec.params
if gs:
w(" #(\n")
with Indent(self.out):
for last, g in iter_with_last(gs):
self.visit_generic_declr(g)
if last:
w("\n")
else:
w(",\n")
w(")")
ps = mod_dec.ports
if ps:
w(" (\n")
with Indent(self.out):
for last, p in iter_with_last(ps):
self.visit_port_declr(p)
if last:
w("\n")
else:
w(",\n")
w(")")
w(";\n")
w = self.out.write
with Indent(self.out):
for o in a.objs:
if isinstance(o, HdlIdDef):
self.visit_HdlIdDef(o)
w(";\n")
elif isinstance(o, HdlCompInst):
self.visit_HdlCompInst(o)
w(";\n\n")
elif isinstance(o, iHdlStatement):
need_semi = self.visit_iHdlStatement(o)
if need_semi:
w(";\n")
else:
w("\n\n")
elif isinstance(o, HdlFunctionDef):
self.visit_HdlFunctionDef(o)
w("\n\n")
elif o is None:
w(";\n")
else:
raise NotImplementedError(o)
self.out.write("endmodule\n")
def visit_HdlStmCase(self, o):
"""
:type o: HdlStmCase
"""
self.visit_doc(o)
w = self.out.write
if o.type != HdlStmCaseType.CASE:
raise NotImplementedError()
w("Switch(")
self.visit_iHdlExpr(o.switch_on)
w(")")
with Indent(self.out):
for c, stm in o.cases:
w("\\\n")
w(".Case(")
self.visit_iHdlExpr(c)
w(",\n")
with Indent(self.out):
self.visit_iHdlStatement(stm)
w(")")
if o.default is not None:
w("\\\n")
w(".Default(\n")
with Indent(self.out):
self.visit_iHdlStatement(o.default)
w(")")
def visit_HdlFunctionDef(self, o):
"""
:type o: HdlFunctionDef
"""
self.visit_doc(o)
w = self.out.write
if o.is_task:
w("task ")
else:
w("function ")
if not o.is_static:
w("automatic ")
if not o.is_task:
self.visit_type_first_part(o.return_t)
self.visit_type_array_part(o.return_t)
if o.is_virtual or o.is_operator:
raise NotImplementedError(o)
w(" ")
w(o.name)
ps = o.params
if ps:
w(" (\n")
with Indent(self.out):
for last, p in iter_with_last(ps):
self.visit_port_declr(p)
if last:
w("\n")
else:
w(",\n")
w(")")
w(";\n")
with Indent(self.out):
for s in o.body:
if isinstance(s, HdlIdDef):
self.visit_HdlIdDef(s)
w(";\n")
elif isinstance(s, iHdlStatement):
need_semi = self.visit_iHdlStatement(s)
if need_semi:
w(";\n")
else:
w("\n")
else:
self.visit_iHdlExpr(s)
w(";\n")
if o.is_task:
w("endtask")
else:
w("endfunction")
def visit_HdlStmForIn(self, o):
"""
:type o: HdlStmForIn
"""
if o.in_preproc:
self.visit_doc(o)
w = self.out.write
if o.labels:
w(o.labels[0])
w(": ")
w("FOR ")
assert len(o.var_defs) == 1, o.var_defs
self.visit_iHdlExpr(o.var_defs[0])
w(" IN ")
self.visit_iHdlExpr(o.collection)
w(" GENERATE\n")
with Indent(self.out):
has_begin_end = self.visit_iHdlObj(o.body)
if has_begin_end:
w(" GENERATE;\n")
else:
w("\n")
w("END GENERATE;\n")
else:
raise TypeError("does not support HdlStmForIn", self, o)
def visit_HdlStmCase(self, o):
"""
:type o: HdlStmCase
"""
self.visit_doc(o)
w = self.out.write
if o.type != HdlStmCaseType.CASE:
raise NotImplementedError()
if o.uniq_constrain is not None:
raise NotImplementedError()
w("CASE ")
self.visit_iHdlExpr(o.switch_on)
w(" IS\n")
with Indent(self.out):
cases = o.cases
for k, stms in cases:
w("WHEN ")
self.visit_iHdlExpr(k)
w(" =>")
is_block = self.visit_HdlStmBlock(stms, begin_end=False)
if is_block:
w("\n")
defal = o.default
if defal is not None:
is_block = w("WHEN OTHERS =>")
self.visit_HdlStmBlock(defal, begin_end=False)
if is_block:
w("\n")
w("END CASE;\n")
def visit_iHdlExpr(self, expr):
w = self.out.write
if expr is HdlAll:
w("ALL")
elif expr is HdlOthers:
w("OTHERS")
elif self.in_typedef and expr is None:
w("<>")
elif is_str(expr):
self.visit_str(expr)
elif isinstance(expr, list):
with_nl = len(expr) > 3
if with_nl:
w("(\n")
else:
w("(")
with Indent(self.out):
for is_last, elem in iter_with_last(expr):
self.visit_iHdlExpr(elem)
if not is_last:
if with_nl:
w(",\n")
else:
w(", ")
w(")")
else:
ToHdlCommon.visit_iHdlExpr(self, expr)
def visit_HdlStmBlock(self, o):
"""
:type o: HdlStmBlock
"""
self.visit_doc(o)
w = self.out.write
if o.in_preproc:
w("generate ")
w("begin")
if o.labels:
w(": ")
w(o.labels[0])
w("\n")
with Indent(self.out):
for s in o.body:
need_semi = self.visit_iHdlStatement(s)
if need_semi:
w(";\n")
else:
w("\n")
w("end")
if o.in_preproc:
w(" endgenerate")
return False
def visit_HdlStmCase(self, o):
"""
:type o: HdlStmCase
:return: True if requires ;\n after end
"""
self.visit_doc(o)
w = self.out.write
w(o.type.name.lower())
w("(")
self.visit_iHdlExpr(o.switch_on)
w(")\n")
with Indent(self.out):
cases = o.cases
for k, stms in cases:
self.visit_iHdlExpr(k)
w(":")
need_semi = self.visit_iHdlStatement_in_statement(stms)
if need_semi:
w(";\n")
else:
w("\n")
defal = o.default
if defal is not None:
w("default:")
need_semi = self.visit_iHdlStatement_in_statement(defal)
if need_semi:
w(";\n")
else:
w("\n")
w("endcase")
return False
def visit_body_items(self, objs):
w = self.out.write
in_def_section = True
with Indent(self.out):
for o in objs:
if isinstance(o, HdlIdDef):
assert in_def_section, o
self.visit_HdlIdDef(o)
continue
elif isinstance(o, HdlModuleDec):
assert in_def_section, o
self.visit_component(o)
continue
elif isinstance(o, HdlFunctionDef):
assert in_def_section, o
self.visit_HdlFunctionDef(o)
continue
if in_def_section:
with UnIndent(self.out):
w("BEGIN\n")
in_def_section = False
if isinstance(o, HdlCompInst):
self.visit_HdlCompInst(o)
w("\n")
elif isinstance(o, iHdlStatement):
self.visit_iHdlStatement(o)
else:
raise NotImplementedError(o)
if in_def_section:
w("BEGIN\n")
def visit_HdlFunctionDef(self, o):
"""
:type o: HdlFunctionDef
"""
self.visit_doc(o)
w = self.out.write
is_procedure = o.return_t is None
if is_procedure:
w("PROCEDURE ")
else:
w("FUNCTION ")
w(o.name)
w(" (")
with Indent(self.out):
for is_last, par in iter_with_last(o.params):
self.visit_HdlIdDef(par, end="")
if not is_last:
w(";\n")
w(")")
if not is_procedure:
w(" RETURN ")
self.visit_type(o.return_t)
if o.is_declaration_only:
w(";\n")
else:
w("\n")
w("IS\n")
self.visit_body_items(o.body)
if is_procedure:
w("END PROCEDURE;\n")
else:
w("END FUNCTION;\n")
def visit_HdlIdDef(self, var):
"""
:type var: HdlIdDef
"""
self.visit_doc(var)
w = self.out.write
if var.is_const:
w("self.")
w(var.name)
w(" = ")
self.visit_iHdlExpr(var.value)
w("\n")
else:
w("self.io.")
w(var.name)
w(' = BasicRtlSimProxy(\n')
with Indent(self.out):
w('sim, self, "')
w(var.name)
w('",\n')
self.visit_type(var.type)
w(", ")
if var.value is None:
w("None)\n")
else:
self.visit_iHdlExpr(var.value)
w(")\n")
def visit_HdlStmBlock(self,
stms,
force_space_before=True,
begin_end=True,
force_begin_end=False):
"""
:type stms: Union[List[iHdlStatement], iHdlStatement, iHdlExpr]
:return: True if statements are wrapped in begin-end block
"""
w = self.out.write
in_preproc = False
if isinstance(stms, HdlStmBlock):
self.visit_doc(stms)
must_have_begin_end = True
in_preproc = stms.in_preproc
stms = stms.body
elif isinstance(stms, list):
must_have_begin_end = len(stms) != 1
else:
must_have_begin_end = False
stms = [
stms,
]
must_have_begin_end |= force_begin_end
non_declarative_seen = False
with Indent(self.out):
for s in stms:
if isinstance(s, iHdlStatement):
if not non_declarative_seen:
non_declarative_seen = True
with UnIndent(self.out):
self._write_begin(begin_end, must_have_begin_end,
force_space_before)
self.visit_iHdlStatement(s)
elif isinstance(s, HdlIdDef):
self.visit_HdlIdDef(s)
else:
if not non_declarative_seen:
non_declarative_seen = True
with UnIndent(self.out):
self._write_begin(begin_end, must_have_begin_end,
force_space_before)
if in_preproc:
self.visit_iHdlObj(s)
w("\n")
else:
self.visit_iHdlExpr(s)
w(";\n")
if not non_declarative_seen:
self._write_begin(begin_end, must_have_begin_end,
force_space_before)
if begin_end and must_have_begin_end:
w("END")
return True
return False
def visit_HdlPhysicalDef(self, o):
"""
:type o: HdlPhysicalDef
"""
w = self.out.write
self.visit_HdlOp(o.range)
w("\n")
with Indent(self.out):
w("UNITS\n")
with Indent(self.out):
for k, v in o.members:
w(k)
if v is not None:
w(" = ")
self.visit_HdlOp(v)
w(";\n")
w("END UNITS")
def visit_component_imports(self, components):
w = self.out.write
prefix = self.module_path_prefix
if prefix is not None:
for c in components:
n = c.module_name
with Indent(self.out):
w('from %s.%s import %s\n' % (prefix, n, n))
def visit_map(self, map_):
w = self.out.write
with Indent(self.out):
for last, m in iter_with_last(map_):
self.visit_map_item(m)
if last:
w("\n")
else:
w(",\n")
def add_module_exampe_serialization(self, module_name):
w = self.out.write
w('if __name__ == "__main__":\n')
with Indent(self.out):
w("from hwt.synthesizer.utils import to_rtl_str\n")
w("u = ")
w(module_name)
w("()\n")
w("print(to_rtl_str(u))\n")
def visit_HdlStmIf(self, o):
"""
:type stm: HdlStmIf
if cond:
...
else:
...
will become
c, cVld = sim_eval_cond(cond)
if not cVld:
# ivalidate outputs
elif c:
...
else:
...
"""
self.visit_doc(o)
w = self.out.write
w("If(")
self.visit_iHdlExpr(o.cond)
w(",\n")
with Indent(self.out):
self.visit_iHdlStatement(o.if_true)
w("\n")
w(")")
for (c, _stm) in o.elifs:
w(".Elif(")
self.visit_iHdlExpr(c)
w(",\n")
with Indent(self.out):
self.visit_iHdlStatement(_stm)
w("\n")
w(")")
ifFalse = o.if_false
if ifFalse is not None:
w(".Else(\n")
with Indent(self.out):
self.visit_iHdlStatement(ifFalse)
w("\n")
w(")")
def visit_HdlStmIf(self, stm):
"""
:type stm: HdlStmIf
if cond:
...
else:
...
will become
c, cVld = sim_eval_cond(cond)
if not cVld:
# ivalidate outputs
elif c:
...
else:
...
"""
w = self.out.write
c = stm.cond
ifTrue = stm.if_true
ifFalse = stm.if_false
w("if ")
self.visit_iHdlExpr(c)
w(":\n")
with Indent(self.out):
self.visit_iHdlStatement_in_statement(ifTrue)
w("\n")
for (c, _stm) in stm.elifs:
w("elif ")
self.visit_iHdlExpr(c)
w(":\n")
with Indent(self.out):
self.visit_iHdlStatement_in_statement(_stm)
w("\n")
w("else:\n")
with Indent(self.out):
if ifFalse is None:
w("pass")
else:
self.visit_iHdlStatement_in_statement(ifFalse)
def visit_HdlModuleDec(self, e, vhdl_obj_name="ENTITY"):
"""
:param e: Entity
:type e: HdlModuleDec
"""
self.visit_doc(e)
w = self.out.write
w(vhdl_obj_name)
w(" ")
w(e.name)
w(" IS\n")
gs = e.params
if gs:
with Indent(self.out):
w("GENERIC(\n")
with Indent(self.out):
for last, g in iter_with_last(gs):
self.visit_param_or_port_declr(g, True)
if last:
w("\n")
else:
w(";\n")
w(");\n")
ps = e.ports
if ps:
with Indent(self.out):
w("PORT(\n")
with Indent(self.out):
for last, p in iter_with_last(ps):
self.visit_param_or_port_declr(p, False)
if last:
w("\n")
else:
w(";\n")
w(");\n")
di = e.objs
if di:
with Indent(self.out):
for o in di:
self.visit_iHdlObj(o)
w("END ")
w(vhdl_obj_name)
w(";\n")
def visit_HdlClassDef(self, o):
"""
:type o: HdlClassDef
"""
w = self.out.write
assert o.type == HdlClassType.STRUCT, o.type
w("RECORD\n")
with Indent(self.out):
for m in o.members:
self.visit_HdlIdDef(m)
w("END RECORD")
def visit_iHdlExpr(self, o):
"""
:type o: iHdlExpr
"""
w = self.out.write
if isinstance(o, HdlValueId):
w(o.val)
return
elif is_str(o):
w('"%s"' % o)
return
elif isinstance(o, HdlValueInt):
self.visit_HdlValueInt(o)
return
elif isinstance(o, (list, tuple)):
with_nl = len(o) > 3
w("(")
for elem in o:
self.visit_iHdlExpr(elem)
if with_nl:
w(", \n")
else:
w(", ")
w(")")
return
elif isinstance(o, HdlOp):
self.visit_HdlOp(o)
return
elif o is None:
w("None")
return
elif isinstance(o, dict):
w("{")
with Indent(self.out):
for last, (k, v) in iter_with_last(
sorted(o.items(), key=lambda x: x[0])):
self.visit_iHdlExpr(k)
w(": ")
self.visit_iHdlExpr(v)
if not last:
w(",\n")
else:
w("\n")
w("}")
return
elif isinstance(o, float):
w("%f" % o)
return
raise NotImplementedError(o.__class__, o)
def visit_HdlValueIdspace(self, o):
"""
:type o: HdlValueIdspace
"""
self.visit_doc(o)
w = self.out.write
#TODO:: if o.declaration_only:
w("PACKAGE ")
w(o.name)
w(" IS\n")
with Indent(self.out):
for _o in o.objs:
self.visit_main_obj(_o)
w("END PACKAGE;\n")
def visit_HdlStmFor(self, o):
"""
:type o: HdlStmFor
"""
self.visit_doc(o)
w = self.out.write
w("FOR ")
self.visit_iHdlExpr(o.params[0])
w(" IN ")
self.visit_iHdlExpr(o.params[1])
w(" LOOP\n")
with Indent(self.out):
for b in o.body:
self.visit_iHdlStatement(b)
w("END FOR;\n")
def visit_iHdlStatement_in_statement(self, stm):
"""
Print statement which is body of other statement
e.g. body of process, branch of if-then-else or case of case stememnt
"""
w = self.out.write
if isinstance(stm, HdlStmBlock):
if len(stm.body) == 1 and not stm.labels:
stm = stm.body[0]
else:
w(" ")
return self.visit_HdlStmBlock(stm)
w("\n")
with Indent(self.out):
return self.visit_iHdlStatement(stm)
def visit_HdlStmBlock(self, o):
"""
:type o: HdlStmBlock
"""
self.visit_doc(o)
w = self.out.write
w("{")
w("\n")
with Indent(self.out):
for s in o.body:
need_semi = self.visit_iHdlStatement(s)
if need_semi:
w(";\n")
else:
w("\n")
w("}")
return False
def visit_HdlFunctionDef(self, o):
"""
:type o: HdlFunctionDef
"""
w = self.out.write
w("def ")
w(o.name)
w("(self")
for p in o.params:
w(", ")
w(p.name)
w("):\n")
with Indent(self.out):
self.visit_doc(o, doc_string=True)
for stm in o.body:
self.visit_iHdlStatement(stm)
w("\n")
w("\n")
def visit_HdlStmWhile(self, o):
"""
:type o: HdlStmWhile
:note: vhdl loop statement
"""
self.visit_doc(o)
w = self.out.write
if o.labels:
w(o.labels[0])
w(": ")
w("LOOP\n")
with Indent(self.out):
if not o.in_preproc and isinstance(o.body, HdlStmBlock):
for _stm in o.body.body:
self.visit_iHdlObj(_stm)
else:
self.visit_iHdlObj(o.body)
w("END LOOP;\n")
def visit_HdlStmAssign(self, o):
"""
:type o: HdlStmAssign
"""
w = self.out.write
if o.time_delay is not None:
raise NotImplementedError()
if o.event_delay is not None:
raise NotImplementedError()
self.visit_iHdlExpr(o.dst)
if o.is_blocking:
w(" := ")
else:
w(" <= ")
with Indent(self.out):
self.visit_iHdlExpr(o.src)
w(";\n")
def visit_HdlIdDef(self, var):
"""
:type var: HdlIdDef
"""
self.visit_doc(var)
w = self.out.write
t, arr_dims = collect_array_dims(var.type)
self.visit_type(t)
w(" ")
w(var.name)
for d in arr_dims:
w("[")
self.visit_iHdlExpr(d)
w("]")
if var.value is not None:
w(" = ")
with Indent(self.out):
self.visit_iHdlExpr(var.value)
return True
