def test_enum(self):
vhdl_ex = vhdl.VhdlExtractor()
with open("rdl_files/test_enum.vhd", "r") as fh:
code = fh.read()
vhdl_objs = vhdl_ex.extract_objects_from_source(code)
self.assertEqual(len(vhdl_objs), 1, "hdlparse should find one entity")
self.assertEqual(vhdl_objs[0].name, "mymodule", "entity name")
ports_enum = [
port for port in vhdl_objs[0].ports
if port.name == "mode_select_mode_o"
]
self.assertEqual(
len(ports_enum),
1,
'hdlparse should find one port named "mode_select_mode_o"',
)
port_enum = ports_enum[0]
self.assertEqual(port_enum.data_type, "ModeSelect_t")
# check also the package
vhdl_ex = vhdl.VhdlExtractor()
with open("rdl_files/test_enum_pkg.vhd", "r") as fh:
code = fh.read()
vhdl_objs = vhdl_ex.extract_objects_from_source(code)
self.assertEqual(
len(vhdl_objs),
2,
"hdlparse should find two entitties (package and type def)",
)
self.assertEqual(vhdl_objs[0].name, "mymodule_pkg", "package name")
self.assertEqual(vhdl_objs[1].name, "ModeSelect_t", "type name")
def test_sw_r_hw_rw(self):
vhdl_ex = vhdl.VhdlExtractor()
with open("rdl_files/sw-r_hw-rw.vhd", "r") as fh:
code = fh.read()
vhdl_objs = vhdl_ex.extract_objects_from_source(code)
self.assertEqual(len(vhdl_objs), 1, "hdlparse should find one entity")
self.assertEqual(vhdl_objs[0].name, "mymodule", "entity name")
ports_o = [
port for port in vhdl_objs[0].ports if port.name == "reg1_ready_o"
]
ports_i = [
port for port in vhdl_objs[0].ports if port.name == "reg1_ready_i"
]
self.assertEqual(
len(ports_o), 1,
"hdlparse should find one port for the output from the reg")
self.assertEqual(
len(ports_i), 1,
"hdlparse should find one port for the input to the reg")
port_o = ports_o[0]
self.assertEqual(port_o.name, "reg1_ready_o")
self.assertEqual(port_o.data_type, "std_logic")
self.assertEqual(port_o.mode, "out")
port_i = ports_i[0]
self.assertEqual(port_i.name, "reg1_ready_i")
self.assertEqual(port_i.data_type, "std_logic")
self.assertEqual(port_i.mode, "in")
def test1(self):
vhdl_ex = vhdl.VhdlExtractor()
with open("rdl_files/test1.vhd", "r") as fh:
code = fh.read()
vhdl_objs = vhdl_ex.extract_objects_from_source(code)
self.assertEqual(len(vhdl_objs), 1, "hdlparse should find one entity")
self.assertEqual(vhdl_objs[0].name, "mymodule", "entity name")
ports_swmod = [
port for port in vhdl_objs[0].ports
if port.name == "inc_dec_inc_dec_swmod"
]
self.assertEqual(len(ports_swmod), 1,
"hdlparse should find one port for the swmod signal")
def main():
'''Run symbolator'''
args = parse_args()
style = DrawStyle()
style.line_color = (0, 0, 0)
vhdl_ex = vhdl.VhdlExtractor()
vlog_ex = vlog.VerilogExtractor()
if os.path.isfile(args.lib_dirs[0]):
# This is a file containing previously parsed array type names
vhdl_ex.load_array_types(args.lib_dirs[0])
else: # args.lib_dirs is a path
# Find all library files
flist = []
for lib in args.lib_dirs:
print('Scanning library:', lib)
flist.extend(
file_search(lib,
extensions=('.vhdl', '.vhd', '.vlog',
'.v'))) # Get VHDL and Verilog files
if args.input and os.path.isfile(args.input):
flist.append(args.input)
# Find all of the array types
vhdl_ex.register_array_types_from_sources(flist)
#print('## ARRAYS:', vhdl_ex.array_types)
if args.save_lib:
print('Saving type defs to "{}".'.format(args.save_lib))
vhdl_ex.save_array_types(args.save_lib)
if args.input is None:
print("Error: Please provide a proper input file")
sys.exit(0)
if args.input == '-': # Read from stdin
code = ''.join(list(sys.stdin))
if is_verilog_code(code):
all_components = {
'<stdin>': [(c, vlog_ex)
for c in vlog_ex.extract_objects_from_source(code)]
}
else:
all_components = {
'<stdin>': [(c, vhdl_ex)
for c in vhdl_ex.extract_objects_from_source(
code, VhdlComponent)]
}
# Output is a named file
elif os.path.isfile(args.input):
if vhdl.is_vhdl(args.input):
all_components = {
args.input:
[(c, vhdl_ex)
for c in vhdl_ex.extract_objects(args.input, VhdlComponent)]
}
else:
all_components = {
args.input:
[(c, vlog_ex) for c in vlog_ex.extract_objects(args.input)]
}
# Output is a directory
elif os.path.isdir(args.input):
flist = set(
file_search(args.input,
extensions=('.vhdl', '.vhd', '.vlog', '.v', '.sv')))
# Separate file by extension
vhdl_files = set(f for f in flist if vhdl.is_vhdl(f))
vlog_files = flist - vhdl_files
all_components = {
f:
[(c, vhdl_ex) for c in vhdl_ex.extract_objects(f, VhdlComponent)]
for f in vhdl_files
}
vlog_components = {
f: [(c, vlog_ex) for c in vlog_ex.extract_objects(f)]
for f in vlog_files
}
all_components.update(vlog_components)
# Output is a directory
else:
print('Error: Invalid input source')
sys.exit(1)
if args.output:
create_directories(args.output)
if not args.markdown_only:
nc = NuCanvas(None)
# Set markers for all shapes
nc.add_marker(
'arrow_fwd',
PathShape(((0, -4), (2, -1, 2, 1, 0, 4), (8, 0), 'z'),
fill=(0, 0, 0),
weight=0), (3.2, 0), 'auto', None)
nc.add_marker(
'arrow_back',
PathShape(((0, -4), (-2, -1, -2, 1, 0, 4), (-8, 0), 'z'),
fill=(0, 0, 0),
weight=0), (-3.2, 0), 'auto', None)
nc.add_marker('bubble',
OvalShape(-3, -3, 3, 3, fill=(255, 255, 255), weight=1),
(0, 0), 'auto', None)
nc.add_marker(
'clock',
PathShape(((0, -7), (0, 7), (7, 0), 'z'),
fill=(255, 255, 255),
weight=1), (0, 0), 'auto', None)
# read default signal & params desc from file
if args.markdown_dict:
with open(args.markdown_dict, 'r') as stream:
global default_desc_dict
default_desc_dict = yaml.safe_load(stream)
# Render every component from every file into an image
for source, components in all_components.items():
for comp, extractor in components:
comp.name = comp.name.strip('_')
if args.component != "" and args.component != comp.name:
continue
reformat_array_params(comp)
if source == '<stdin>' or args.output_as_filename:
fname = args.output
else:
fname = '{}{}.{}'.format(
args.libname + "__" if args.libname is not None
or args.libname != "" else "", comp.name, args.format)
if args.output:
fname = os.path.join(args.output, fname)
# image output
if not args.markdown_only:
print('Creating symbol for {} "{}"\n\t-> {}'.format(
source, comp.name, fname))
if args.format == 'svg':
surf = SvgSurface(fname,
style,
padding=5,
scale=args.scale)
else:
surf = CairoSurface(fname,
style,
padding=5,
scale=args.scale)
nc.set_surface(surf)
nc.clear_shapes()
sym = make_symbol(comp, extractor, args.title, args.libname,
args.no_type)
sym.draw(0, 0, nc)
nc.render(args.transparent)
# doc (markdown) output
if args.markdown or args.markdown_only:
if args.output_as_filename or args.markdown_only:
fname_md = args.output
fname_img = re.sub('md$', args.format,
os.path.basename(fname_md))
else:
fname_md = re.sub(args.format + '$', 'md', fname)
fname_img = os.path.basename(fname)
print('Creating markdown for {} "{}"\n\t-> {}'.format(
source, comp.name, fname_md))
env = Environment(loader=PackageLoader("symbolator_templates",
''),
autoescape=select_autoescape())
template = env.get_template("template.md.jinjja2")
doc_txt = template.render(module=comp,
fname=fname_img,
get_description=get_description)
with open(fname_md, 'w') as doc_file:
doc_file.write(doc_txt)
def main():
'''Run symbolator'''
args = parse_args()
style = DrawStyle()
style.line_color = (0, 0, 0)
vhdl_ex = vhdl.VhdlExtractor()
vlog_ex = vlog.VerilogExtractor()
if args.input is None:
sys.exit(0)
if args.input == '-': # Read from stdin
code = ''.join(list(sys.stdin))
if is_verilog_code(code):
all_components = {
'<stdin>': [(c, vlog_ex)
for c in vlog_ex.extract_objects_from_source(code)]
}
else:
all_components = {
'<stdin>': [(c, vhdl_ex)
for c in vhdl_ex.extract_objects_from_source(
code, VhdlComponent)]
}
# Output is a named file
elif os.path.isfile(args.input):
if vhdl.is_vhdl(args.input):
all_components = {
args.input:
[(c, vhdl_ex)
for c in vhdl_ex.extract_objects(args.input, VhdlComponent)]
}
else:
all_components = {
args.input:
[(c, vlog_ex) for c in vlog_ex.extract_objects(args.input)]
}
# Output is a directory
else:
print('ERROR: Invalid input source')
sys.exit(1)
if args.output:
create_directories(args.output)
nc = NuCanvas(None)
# Set markers for all shapes
nc.add_marker(
'arrow_fwd',
PathShape(((0, -4), (2, -1, 2, 1, 0, 4), (8, 0), 'z'),
fill=(0, 0, 0),
weight=0), (3.2, 0), 'auto', None)
nc.add_marker(
'arrow_back',
PathShape(((0, -4), (-2, -1, -2, 1, 0, 4), (-8, 0), 'z'),
fill=(0, 0, 0),
weight=0), (-3.2, 0), 'auto', None)
nc.add_marker('bubble',
OvalShape(-3, -3, 3, 3, fill=(255, 255, 255), weight=1),
(0, 0), 'auto', None)
nc.add_marker(
'clock',
PathShape(((0, -7), (0, 7), (7, 0), 'z'),
fill=(255, 255, 255),
weight=1), (0, 0), 'auto', None)
# Render every component from every file into an image
for source, components in all_components.items():
for comp, extractor in components:
comp.name = comp.name.strip('_')
reformat_array_params(comp)
if source == '<stdin>':
fname = args.output
else:
fname = args.input.rsplit('.', 1)[0] + '.' + args.format
if args.output:
fname = os.path.join(args.output, fname)
assert not os.path.exists(fname), fname
print('Creating symbol for {} "{}" -> {}'.format(
source, comp.name, fname))
if args.format == 'svg':
surf = SvgSurface(fname, style, padding=5, scale=args.scale)
else:
surf = CairoSurface(fname, style, padding=5, scale=args.scale)
nc.set_surface(surf)
nc.clear_shapes()
sym = make_symbol(comp, extractor, args.title, args.libname,
args.no_type)
sym.draw(0, 0, nc)
nc.render()
def main():
'''Run symbolator'''
args = parse_args()
style = DrawStyle()
style.line_color = (0,0,0)
vhdl_ex = vhdl.VhdlExtractor()
vlog_ex = vlog.VerilogExtractor()
if os.path.isfile(args.lib_dirs[0]):
# This is a file containing previously parsed array type names
vhdl_ex.load_array_types(args.lib_dirs[0])
else: # args.lib_dirs is a path
# Find all library files
flist = []
for lib in args.lib_dirs:
print('Scanning library:', lib)
flist.extend(file_search(lib, extensions=('.vhdl', '.vhd', '.vlog', '.v'))) # Get VHDL and Verilog files
if args.input and os.path.isfile(args.input):
flist.append(args.input)
# Find all of the array types
vhdl_ex.register_array_types_from_sources(flist)
#print('## ARRAYS:', vhdl_ex.array_types)
if args.save_lib:
print('Saving type defs to "{}".'.format(args.save_lib))
vhdl_ex.save_array_types(args.save_lib)
if args.input is None:
print("Error: Please provide a proper input file")
sys.exit(0)
if args.input == '-': # Read from stdin
code = ''.join(list(sys.stdin))
if is_verilog_code(code):
all_components = {'<stdin>': [(c, vlog_ex) for c in vlog_ex.extract_objects_from_source(code)]}
else:
all_components = {'<stdin>': [(c, vhdl_ex) for c in vhdl_ex.extract_objects_from_source(code, VhdlComponent)]}
all_components['<stdin>'].extend((c, vhdl_ex) for c in vhdl_ex.extract_objects_from_source(code, VhdlEntity))
# Output is a named file
elif os.path.isfile(args.input):
if vhdl.is_vhdl(args.input):
all_components = {args.input: [(c, vhdl_ex) for c in vhdl_ex.extract_objects(args.input, VhdlComponent)]}
all_components[args.input].extend((c, vhdl_ex) for c in vhdl_ex.extract_objects(args.input, VhdlEntity))
else:
all_components = {args.input: [(c, vlog_ex) for c in vlog_ex.extract_objects(args.input)]}
# Output is a directory
elif os.path.isdir(args.input):
flist = set(file_search(args.input, extensions=('.vhdl', '.vhd', '.vlog', '.v')))
# Separate file by extension
vhdl_files = set(f for f in flist if vhdl.is_vhdl(f))
vlog_files = flist - vhdl_files
all_components = {f: [(c, vhdl_ex) for c in vhdl_ex.extract_objects(f, objtype)] for objtype in [VhdlComponent, VhdlEntity] for f in vhdl_files}
vlog_components = {f: [(c, vlog_ex) for c in vlog_ex.extract_objects(f)] for f in vlog_files}
all_components.update(vlog_components)
# Output is a directory
else:
print('Error: Invalid input source')
sys.exit(1)
if args.output:
create_directories(args.output)
nc = NuCanvas(None)
# Set markers for all shapes
nc.add_marker('arrow_fwd',
PathShape(((0,-4), (2,-1, 2,1, 0,4), (8,0), 'z'), fill=(0,0,0), weight=0),
(3.2,0), 'auto', None)
nc.add_marker('arrow_back',
PathShape(((0,-4), (-2,-1, -2,1, 0,4), (-8,0), 'z'), fill=(0,0,0), weight=0),
(-3.2,0), 'auto', None)
nc.add_marker('bubble',
OvalShape(-3,-3, 3,3, fill=(255,255,255), weight=1),
(0,0), 'auto', None)
nc.add_marker('clock',
PathShape(((0,-7), (0,7), (7,0), 'z'), fill=(255,255,255), weight=1),
(0,0), 'auto', None)
# Render every component from every file into an image
for source, components in all_components.items():
for comp, extractor in components:
comp.name = comp.name.strip('_')
reformat_array_params(comp)
if source == '<stdin>' or args.output_as_filename:
fname = args.output
else:
fname = '{}{}.{}'.format(
args.libname + "__" if args.libname is not None or args.libname != "" else "",
comp.name,
args.format)
if args.output:
fname = os.path.join(args.output, fname)
print('Creating symbol for {} "{}"\n\t-> {}'.format(source, comp.name, fname))
if args.format == 'svg':
surf = SvgSurface(fname, style, padding=5, scale=args.scale)
else:
surf = CairoSurface(fname, style, padding=5, scale=args.scale)
nc.set_surface(surf)
nc.clear_shapes()
sym = make_symbol(comp, extractor, args.title, args.libname, args.no_type)
sym.draw(0,0, nc)
nc.render(args.transparent)