def _create_combined(model_file_name, monitor_aiger_file_name) -> str:
rc, out, err = execute_shell('{combine} {spec_aiger} {model_aiger}'.format(
combine=COMBINEAIGER_PATH,
model_aiger=model_file_name,
spec_aiger=monitor_aiger_file_name))
assert_exec_strict(rc, out, err)
return create_unique_file(out, suffix='.aag')
def get_spec_type(spec_file_name) -> bool:
rc, out, err = execute_shell('{syfco} -g {spec_file_name}'.format(
syfco=SYFCO_PATH, spec_file_name=spec_file_name))
assert_exec_strict(rc, out, err)
out_stripped = out.strip().lower()
assert out_stripped in ['moore', 'mealy'], out_stripped
return out_stripped == 'moore'
def get_spec_type(spec_file_name) -> bool:
rc, out, err = execute_shell("{syfco} -g {spec_file_name}".format(syfco=SYFCO_PATH, spec_file_name=spec_file_name))
assert_exec_strict(rc, out, err)
out_stripped = out.strip().lower()
assert out_stripped in ["moore", "mealy"], out_stripped
is_moore = out_stripped == "moore"
return is_moore
def verilog_to_aiger(verilog:str) -> str:
verilog_file_name = create_unique_file(verilog, suffix='.v')
aiger_file_name = create_unique_file(suffix='.aag')
script = """
read_verilog {verilog_file}
synth -flatten -auto-top
abc -g AND
write_aiger -ascii -symbols -zinit {aiger_file}""".format(aiger_file=aiger_file_name,
verilog_file=verilog_file_name)
script_file_name = create_unique_file(text=script, suffix='.ys')
files_to_remove = (aiger_file_name,
verilog_file_name,
script_file_name) # tmp files stay if smth goes wrong
# on some examples yosys fails with a standard stack limit, so we raise it
hard_limit = resource.getrlimit(resource.RLIMIT_STACK)[1]
resource.setrlimit(resource.RLIMIT_STACK, (hard_limit, hard_limit))
rc, out, err = execute_shell('{yosys} -Q -s {script}'.format(
yosys=YOSYS_PATH, script=script_file_name))
assert_exec_strict(rc, out, err)
logging.debug('yosys stdout:\n' + out)
res = readfile(aiger_file_name)
[os.remove(f) for f in files_to_remove]
return res
def _create_monitor_file(tlsf_file_name) -> str:
rc, out, err = execute_shell('{syfco} -f smv {tlsf_file} -m fully'.format(
syfco=SYFCO_PATH, tlsf_file=tlsf_file_name))
assert_exec_strict(rc, out, err)
rc, out, err = execute_shell('{smvtoaig} -a -L "{ltl2smv}"'.format(
smvtoaig=SMVTOAIG_PATH, ltl2smv=LTL2SMV_PATH),
input=out)
assert rc == 0, rc_out_err_to_str(rc, out,
err) # it outputs the LTL into stderr
return create_unique_file(out, suffix='.aag')
def _create_combined(model_file_name, monitor_aiger_file_name) -> str:
rc, out, err = execute_shell('{combine} {spec_aiger} {model_aiger}'.format(
combine=COMBINEAIGER_PATH,
model_aiger=model_file_name,
spec_aiger=monitor_aiger_file_name))
assert_exec_strict(rc, out, err)
(fd, aag_file_name) = tempfile.mkstemp(text=True, suffix='.aag')
os.write(fd, bytes(out, encoding=sys.getdefaultencoding()))
os.close(fd)
return aag_file_name
def _create_monitor_file(tlsf_file_name) -> str:
rc, out, err = execute_shell('{syfco} -f smv {tlsf_file} -m fully'.format(syfco=SYFCO_PATH,
tlsf_file=tlsf_file_name))
assert_exec_strict(rc, out, err)
rc, out, err = execute_shell('{smvtoaig} -a'.format(smvtoaig=SMVTOAIG_PATH), input=out)
assert rc == 0, rc_out_err_to_str(rc, out, err) # it outputs the LTL into stderr
(fd, aag_file_name) = tempfile.mkstemp(text=True, suffix='.aag')
os.write(fd, bytes(out, encoding=sys.getdefaultencoding()))
os.close(fd)
return aag_file_name
def verilog_to_aiger(verilog:str) -> str:
input_verilog_file = create_tmp_file(verilog, suffix='v')
file_blif_mv = create_tmp_file(suffix='.mv')
file_aiger_tmp = create_tmp_file(suffix='.aag')
file_output_aiger = create_tmp_file(suffix='.aag')
files_to_remove = (input_verilog_file,
file_blif_mv,
file_aiger_tmp,
file_output_aiger) # tmp files stay if smth goes wrong
# vl2mv
# on some examples vl2mv fails with a standard stack limit, so we raise it
hard_limit = resource.getrlimit(resource.RLIMIT_STACK)[1]
resource.setrlimit(resource.RLIMIT_STACK, (hard_limit, hard_limit))
rc, out, err = execute_shell('{vl2mv} {file_input_verilog} -o {file_blif_mv}'.format(
vl2mv=VL2MV_PATH,
file_input_verilog=input_verilog_file,
file_blif_mv=file_blif_mv))
if rc == -11:
logging.warning('vl2mv caught SIGSEGV: ha-ha! Re-run me on this example, or manually convert into aiger')
logging.debug('verilog was: ' + readfile(input_verilog_file))
assert rc == 0, rc_out_err_to_str(rc, out, err) # no check that stderr='' because vl2mv outputs the input file name
# abc
rc, out, err = execute_shell('{abc} -c '
'"read_blif_mv {file_blif_mv}; '
'strash; refactor; rewrite; dfraig; rewrite; dfraig; '
'write_aiger -s {file_aiger_tmp}"'.format(
file_blif_mv=file_blif_mv,
abc=ABC_PATH,
file_aiger_tmp=file_aiger_tmp))
assert_exec_strict(rc, out, err)
# aigtoaig
rc, out, err = execute_shell('{aigtoaig} {file_aiger_tmp} {file_output_aiger}'.format(
aigtoaig=AIGTOAIG_PATH,
file_aiger_tmp=file_aiger_tmp,
file_output_aiger=file_output_aiger))
assert_exec_strict(rc, out, err)
res = readfile(file_output_aiger)
[os.remove(f) for f in files_to_remove]
return res
def convert_tlsf_or_acacia_to_acacia(spec_file_name: str,
is_moore_=None) -> (str, str, bool):
if spec_file_name.endswith('.ltl'):
ltl_text, part_text = readfile(spec_file_name), readfile(
spec_file_name.replace('.ltl', '.part'))
return ltl_text, part_text, is_moore_
rc, out, err = execute_shell('{syfco} -ins {spec_file_name}'.format(
syfco=SYFCO_PATH, spec_file_name=spec_file_name))
assert_exec_strict(rc, out, err)
part_text = '.inputs ' + ' '.join(_parse_tuple_str(
out.lower())) # syfco lowers all signal names in props
rc, out, err = execute_shell('{syfco} -outs {spec_file_name}'.format(
syfco=SYFCO_PATH, spec_file_name=spec_file_name))
assert_exec_strict(rc, out, err)
part_text += '\n.outputs ' + ' '.join(_parse_tuple_str(
out.lower())) # syfco lowers all signal names in props
# rc, out, err = execute_shell('{syfco} -f acacia -m fully -os Moore {spec_file_name}'
# .format(syfco=SYFCO_PATH, spec_file_name=spec_file_name))
# rc, out, err = execute_shell('{syfco} -f acacia -m fully {spec_file_name}'
# .format(syfco=SYFCO_PATH, spec_file_name=spec_file_name))
rc, out, err = execute_shell(
'{syfco} -f lily -m fully -nr {spec_file_name}'.format(
syfco=SYFCO_PATH, spec_file_name=spec_file_name))
assert_exec_strict(rc, out, err)
ltl_text = out
return ltl_text, part_text, get_spec_type(spec_file_name)
def convert_tlsf_to_acacia(spec_file_name) -> (str, str):
rc, out, err = execute_shell(
"{syfco} -ins {spec_file_name}".format(syfco=SYFCO_PATH, spec_file_name=spec_file_name)
)
assert_exec_strict(rc, out, err)
part_text = ".inputs " + " ".join(_parse_tuple_str(out.lower())) # syfco lowers all signal names in props
rc, out, err = execute_shell(
"{syfco} -outs {spec_file_name}".format(syfco=SYFCO_PATH, spec_file_name=spec_file_name)
)
assert_exec_strict(rc, out, err)
part_text += "\n.outputs " + " ".join(_parse_tuple_str(out.lower())) # syfco lowers all signal names in props
rc, out, err = execute_shell(
"{syfco} -f acacia -m fully {spec_file_name}".format(syfco=SYFCO_PATH, spec_file_name=spec_file_name)
)
assert_exec_strict(rc, out, err)
ltl_text = out
return ltl_text, part_text