def run(self):
data = []
#Read file and rounds
rawData = SetUp.import_data_file()
rounds = SetUp.get_rounds()
print("Will run"+" " + rounds + " " + "rounds")
#gets the data point count
splitData = SetUp.splitData(rawData)
preFillDataInRoute(rawData,splitData,data)
printAllRounds(rounds,data)
def flush(self):
# write all dirty entries into memory
for i in range( 0, 4 ):
for j in range( 0, 2 ):
# the record is valid and dirty
if self.cacheSets[i][j][0] == 1 and self.cacheSets[i][j][1] == 1:
# write to memory
wbAddr = self.cacheSets[i][j][2] #tag
wbAddr = (wbAddr << 5) + (i << 3)
# we will only have dirty cache pages for data mem, not instructions
if( wbAddr >= ( self.numInstructions *4) + 96 ):
self.dataval[SetUp.getIndexOfMemAddress(wbAddr, False, self.dataval, self.address, self.numInstructions)]= self.cacheSets[i][j][3]
#self.dataval[ self.getIndexOfMemAddress(wbAddr, False) ] = self.cacheSets[i][j][3]
if( wbAddr+4 >= (self.numInstructions *4) + 96 ):
self.dataval[SetUp.getIndexOfMemAddress(wbAddr+4, False, self.dataval, self.address, self.numInstructions)] = self.cacheSets[i][j][4]
#self.dataval[ self.getIndexOfMemAddress(wbAddr+4, False) ] = self.cacheSets[i][j][4]
# reset dirty bit
self.cacheSets[i][j][1] = 0
def __init__(self, instruction, opcodes, opcodeStr, dataval, address, arg1,
arg2, arg3, arg1Str, arg2Str, arg3Str, numInstructions,
destReg, src1Reg, src2Reg):
self.instruction = instruction
self.opcode = opcodes
self.dataval = dataval
self.address = address
self.numInstructions = numInstructions
self.arg1 = arg1
self.arg2 = arg2
self.arg3 = arg3
self.arg1Str = arg1Str
self.arg2Str = arg2Str
self.arg3Str = arg3Str
self.destReg = destReg
self.src1Reg = src1Reg
self.src2Reg = src2Reg
self.opcodeStr = opcodeStr
self.PC = 96
self.cycle = 1
self.R = [
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0
]
self.postMemBuff = [-1,
-1] # first number is value, second is instr index
self.postALUBuff = [-1,
-1] # first number is value, second is instr index
self.preMemBuff = [-1, -1]
self.preALUBuff = [-1, -1]
self.preIssueBuff = [-1, -1, -1, -1]
#uncomment these lines as the classes are developed :)
self.WB = writeBack.WriteBack(self.R, self.postMemBuff,
self.postALUBuff, destReg)
self.ALU = alu.ALU(self.R, self.postALUBuff, self.preALUBuff,
opcodeStr, arg1, arg2, arg3)
self.MEM = mem.MEM(self.R, self.postMemBuff, self.preMemBuff,
opcodeStr, arg1, arg2, arg3, dataval, address,
self.numInstructions)
self.cache = cache.Cache(self.numInstructions, self.instruction,
self.dataval, self.address)
self.issue = issue.Issue(instruction, opcodes, opcodeStr, dataval,
address, arg1, arg2, arg3,
self.numInstructions, destReg, src1Reg,
src2Reg, self.preIssueBuff, self.preALUBuff,
self.preMemBuff, self.postALUBuff,
self.postMemBuff)
self.fetch = fetch.Fetch(instruction, opcodeStr, dataval, address,
arg1, arg2, arg3, self.numInstructions,
destReg, src1Reg, src2Reg, self.preALUBuff,
self.postALUBuff, self.PC, cache,
self.preIssueBuff)
self.outputFileName = SetUp.get_output_filename()
def printState(self):
outputFileName = SetUp.get_output_filename()
with open(outputFileName + "_sim.txt", "a") as outFile:
i = self.getIndexOfMemAddress(self.PC)
outFile.write("====================\n")
outFile.write("cycle:" + str(self.cycle) + "\t" + str(self.PC) +
"\t" + self.opcodeStr[i] + "\t" + self.arg1Str[i] +
self.arg2Str[i] + self.arg3Str[i] + "\n")
outFile.write("\n")
outFile.write("registers:\n")
outStr = "r00:"
for i in range(0, 8):
outStr = outStr + "\t" + str(self.R[i])
outFile.write(outStr)
outFile.write("\n")
outStr = "r08:"
for i in range(8, 16):
outStr = outStr + "\t" + str(self.R[i])
outFile.write(outStr)
outFile.write("\n")
outStr = "r16:"
for i in range(16, 24):
outStr = outStr + "\t" + str(self.R[i])
outFile.write(outStr)
outFile.write("\n")
outStr = "r24:"
for i in range(24, 32):
outStr = outStr + "\t" + str(self.R[i])
outFile.write(outStr)
outFile.write("\n")
outFile.write("\ndata:\n")
outStr = "\n"
for i in range(len(self.dataval)):
if i % 8 == 0 and i != 0 or i == len(self.dataval):
outFile.write(outStr + "\n")
if i % 8 == 0:
outStr = str(
self.address[i + self.numInstructions]) + ":" + str(
self.dataval[i])
if i % 8 != 0:
outStr = outStr + "\t" + str(self.dataval[i])
outFile.write(outStr + "\n")
outFile.close()
def print(self):
# the following lines write the disassembly out to a file
outFile = open(SetUp.get_output_filename() + "_dis.txt", 'w')
for i in range(self.numInstructs):
outFile.write(str(self.instrSpaced[i]) + '\t' + str(self.address[i]) + '\t' + str(self.opcodeStr[i])
+ '\t' + str(self.arg1Str[i]) + str(self.arg2Str[i]) + str(self.arg3Str[i]) + "\n")
for i in range(len(self.dataval)):
outFile.write(str(self.rawdata[i]) + '\t'+str(self.addressdata[i])+ '\t' +str(self.dataval[i]) +"\n")
outFile.close()
def print(self):
# write to a file
outFile = open(SetUp.get_output_filename() + "_dis.txt", 'w')
for i in range(self.numInstructs):
outFile.write((self.instrSpaced[i] + '\t' + str(self.address[i]) +
'\t' + self.opcodeStr[i] + self.arg1Str[i] +
self.arg2Str[i] + self.arg3Str[i] + '\n'))
for i in range(len(self.dataval)):
outFile.write(self.rawdata[i] + '\t' +
str(self.address[self.numInstructs + i]) + '\t' +
str(self.dataval[i]) + '\n')
outFile.close()
def printDis(self):
outFile = open(SetUp.get_output_filename() + "_dis.txt", 'w')
#print("number of instructions " + str(self.numInstructions))
for i in range(self.numInstructions):
outFile.write(
str(self.instrSpaced[i]) + '\t' + str(self.address[i]) + '\t' +
str(self.opcodeStr[i]) + str(self.arg1Str[i]) +
str(self.arg2Str[i]) + str(self.arg3Str[i]) + '\n')
index = self.numInstructions
for index in range(len(self.dataVal)):
outFile.write(
str(self.rawData[index]) + '\t' +
str(self.address[index + self.numInstructions]) + '\t' +
str(self.dataVal[index]) + '\n')
outFile.close()
def printState(self):
outputFileName = SetUp.get_output_filename()
with open(outputFileName + "_sim.txt", 'a') as outFile:
i = self.getIndexOfMemAddress(self.PC)
outFile.write("====================\n")
""" """
outFile.write("cycle: " + str(self.cycle) + "\t" + str(self.PC) +
"\t" + str(self.opcodeStr[i]) + self.arg1Str[i] +
self.arg2Str[i] + self.arg3Str[i] + "\n")
outFile.write("\n" + "registers:")
regNumber = 0
while regNumber < len(self.R):
if (regNumber % 8) == 0:
outFile.write("\n" + "r" + str(int(regNumber)).zfill(2) +
":\t" + str(self.R[regNumber]) + "\t")
else:
outFile.write(str(self.R[regNumber]) + "\t")
regNumber += 1
outFile.write("\n\ndata: \n")
outStr = ""
a = self.address[self.numInstructs - 1] + 4
for i in range(len(self.dataval)):
if (i % 8) == 0 and i != 0 or i == len(self.dataval):
outFile.write(outStr + "\n")
if (i % 8) == 0:
outStr = str(a) + ":\t" + str(self.dataval[i])
a += (8 * 4)
if (i % 8) != 0:
outStr = outStr + "\t" + str(self.dataval[i])
outFile.write(outStr + "\n")
outFile.close()
def run(self):
numInPreIssueBuffer = 0
numIssued = 0
curr = self.preIssueBuff[0]
# if the instruction is load or store, it can't be issued until all prior stores
# instructions are issued.
# this variable will be set to True if there is a store instruction in the pre issue
# buffer that can't be issued for any reason.
storeInstructionSkippedThisCycle = False
# count how many entries in the preIssueBuff have instructions in them
for i in range(len(self.preIssueBuff)):
if i != -1:
numInPreIssueBuffer += 1
while (numIssued < 2 and numInPreIssueBuffer > 0 and curr < 4):
# if there is no room in the preALUBuff or preMemBuff then instructions
# of that type can't be issued this cycle to avoid a structural hazard
thereIsRoomInPreALUBuff = self.preALUBuff[1] == -1
thereIsRoomInPreMemBuff = self.preMemBuff[1] == -1
index = self.preIssueBuff[curr]
issueMe = False
if index != -1:
# if the instruction is a mem instruction and there is room in the pre mem buffer
if SetUp.isMemOp(
self.opcodeStr[index]) and thereIsRoomInPreMemBuff:
# RAWCheck method will check if there are any RAW hazards with the current instruction
# issueMe will equal True if there are no RAW hazards, false if there are
issueMe = self.RAWCheck(curr)
# if the instruction is an ALU instruction and there is room in the pre ALU buffer
if (not SetUp.isMemOp(
self.opcodeStr[index])) and thereIsRoomInPreALUBuff:
# RAWCheck method will check if there are any RAW hazards with the current instruction
# issueMe will equal True if there are no RAW hazards, false if there are
issueMe = self.RAWCheck(curr)
# if the instruction is a store instruction, and it isn't being issued,
# then no subsequent mem instructions may be issued for the rest of the cycle
if self.opcodeStr[index] == "STUR" and not issueMe:
storeInstructionSkippedThisCycle = True
# if the instruction is a mem instruction, check to see that all previous store
# instructions have been issued. If not, the instruction may not be issued this cycle
if SetUp.isMemOp(self.opcodeStr[index]
) and storeInstructionSkippedThisCycle:
issueMe = False
# if issueMe = True at this point, it has passed all of the tests and met all
# of the necessary criteria to be issued!
if issueMe:
numIssued += 1
# copy the instruction to the appropriate buffer
if SetUp.isMemOp(self.opcodeStr[index]):
self.preMemBuff[self.preMemBuff.index(-1)] = index
else:
self.preALUBuff[self.preALUBuff.index(-1)] = index
# move the instrs in the preIssueBuff down one level
self.preIssueBuff[0:curr] = self.preIssueBuff[0:curr]
self.preIssueBuff[curr:3] = self.preIssueBuff[
curr + 1:] # dropped 4, think will go to end always
self.preIssueBuff[3] = -1
numInPreIssueBuffer -= 1
else:
# move on to the next instruction in preIssueBuff
curr += 1
else:
# move on to the next instruction in preIssueBuff
curr += 1
def checkCache(self, dataIndex, instructionIndex, isWriteToMem,
dataToWrite):
# isWritetoMem is aligned with isSW in the mem unit! data to write also comes from there
# check the cache, if it is there, then we return true
# otherwise, return a false and set up for next cycle
# calculate the address from instruction index and base address
#################### instruction or data??? ######################
if (dataIndex == -1):
#it is an instruction we are getting the address for
addressLocal = 96 + (4 * instructionIndex) # correct
#if its a data location do this
else:
addressLocal = 96 + (4 * (self.numInstructions)) + (4 * dataIndex)
# We are double word aligning so we need to make sure that the address of block 0 is always 96 or 96 + n8
# 96, 104, 112 ......
# this is critical since everything else assumes that block 0 is address1
################################## ALIGNMENT CHECK - generate addres for both words ##################################
if addressLocal % 8 == 0:
dataWord = 0 # block 0 was the address
address1 = addressLocal
address2 = addressLocal + 4
#check for "alignment"
# this picks the second word as address so we need to fix it
# set address1 - block 1 address to address - 4
if addressLocal % 8 != 0:
dataWord = 1 # block 1 was the address
address1 = addressLocal - 4
address2 = addressLocal
############################ Deal with instruct/mem boundry ################################
# if address1 is an instruction go to instruction list and get it
if address1 < 96 + (
4 * self.numInstructions
): # cant use dataIndex because aligning might have bridged boundry!
data1 = self.instructions[SetUp.getIndexOfMemAddress(
address1, False, self.dataval, self.address,
self.numInstructions)]
#if data, go to the data memory and get the data
else:
data1 = self.dataval[SetUp.getIndexOfMemAddress(
address1, False, self.dataval, self.address,
self.numInstructions)]
# same process for address 2
if address2 < 96 + (4 * self.numInstructions):
data2 = self.instructions[SetUp.getIndexOfMemAddress(
address2, False, self.dataval, self.address,
self.numInstructions)]
else:
if address2 <= (96 + (4 * self.numInstructions) +
(4 * (len(self.dataval) - 1))):
data2 = self.dataval[SetUp.getIndexOfMemAddress(
address2, False, self.dataval, self.address,
self.numInstructions)]
else:
data2 = 0
########################### WRITING TO MEMORY only one word! ##########################
# if we are going to write to mem select which word it is. Don't write both
# we will only be writing data to memory - not instructions
# set the appropriate write element to the passed in data
if isWriteToMem and dataWord == 0:
data1 = dataToWrite
elif isWriteToMem and dataWord == 1:
data2 = dataToWrite
# Architecture of Cache Sets [0,1,2,3,4]
# [valid, dirty, tag, data, data]
################## Check Cache #############################
##### DECODE THE CACHE ADDRESS FROM THE address for WORD0
#####
# get the tag and the set number based on the mem address
#TODO make sure this binary op is working right !!!!!
setNum = (address1 & self.setMask) >> 3
tag = (address1 & self.tagMask) >> 5
hit = False # initialize hit
# look in the cache.
##################### check the valid bit AND check the tag #####################
#figure out which block has the info or not. It might not be there
if (self.cacheSets[setNum][0][0] == 1
and self.cacheSets[setNum][0][2] == tag):
# we have a hit
hit = True
assocblock = 0 # block zero is the hit
# look at the other associative block
elif self.cacheSets[setNum][1][0] == 1 and self.cacheSets[setNum][1][
2] == tag:
# we have a hit
hit = True
assocblock = 1 # block 1 is the hit
# if we have a hit, update the LRU and dirty bit if a data write
# and return
if (hit):
if hit and isWriteToMem:
# update the dirty bit if we are going to be writing to cache - should only be to data not to instructs
# TODO add check to make sure it is a data write and crash nice if some error occurs
self.cacheSets[setNum][assocblock][1] = 1 # dirty bit
# if the block hit in set was block zero, write the set LRU bit a 1, if block 1 write set lru bit to 0
# default for lru bit is zero so same as block 1 hit
self.lruBit[setNum] = (assocblock + 1) % 2 # lru bit -
self.cacheSets[setNum][assocblock][
dataWord +
3] = dataToWrite # +3 offsets to correct word element
#if was an instruction hit or a non write to data mem
elif hit:
self.lruBit[setNum] = (assocblock + 1) % 2
#returns a true we got a hit and the data or instruction in the specific dataword. Data word specifies
#either the first or second word in a block based on what the instruction was.
return [True, self.cacheSets[setNum][assocblock][dataWord + 3]
] # the +3 is to point to either [4] or [5]
# if we get here, we have a CACHE MISS
# First check to see if we had a miss for this address in the previous cycle so we can update the cache with
#the data in the requested mem address and allow the instruction to proceed
# if we tried to get this address in the previous cycle
# and had a cache miss, its address is in the JustMissedlist
# therefore, we have waited one cycle, and now need to
# perform the memory operation
if address1 in self.justMissedList:
# remove the address from the list - reset
while (self.justMissedList.count(address1) > 0):
self.justMissedList.remove(address1)
if isWriteToMem:
if dataWord == 0:
data = data1
else:
data = data2
# Architecture of Cache
# valid, dirty, tag, data, data
# 4 sets of two blocks with two words per block. Each block has valid, dirty, tag
#cacheSets = [[[0, 0, 0, 0, 0], [0, 0, 0, 0, 0]], [[0, 0, 0, 0, 0], [0, 0, 0, 0, 0]],[[0, 0, 0, 0, 0], [0, 0, 0, 0, 0]], [[0, 0, 0, 0, 0], [0, 0, 0, 0, 0]]]
# now add to the the cache
# check the set number, block number based on lru bit setting, and dirty bit for the block number: if dirty bit is 1 we got a data
# if the block in the set in cache we want to write to is dirty we will write data words in that block to memory
# if the lru bit for the set is zero, the set / blocks could be empty. If so then blocks dirty bit will certainly be 0
# if the dirty bit is 1 then fine, write back both words in block. But it is also possible that block 1 is dirty. SO write it back. If the lru bit is 1, then certainly the set/block is not empty and it is
# possible that block zero's dirty bit is 1. Then write back.
#NOTE: we are getting the tag associated with the block that is being written back and set but we will write both blocks
# back if both blocks are on the data side. Takes care of the case where you are across the boundry.
if self.cacheSets[setNum][self.lruBit[setNum]][1] == 1:
# write back the memory address asociated with the block
wbAddr = self.cacheSets[setNum][self.lruBit[setNum]][2] #tag
# modify tag to get back to the original address, remember all addresses are inherently word aligned
# lower 2 bits are zero !!!!
wbAddr = (wbAddr << 5) + (setNum << 3)
# we will, we better, only have dirty cache entries for data mem, not instructions
# update data mem locations!
# if the cache tag: set gives us a double word aligned value ie. 96,104,
# Lets say that word 0 is the last instruction and word one is the first data element
# we would only want to update the second word
# But if lets say we have two data elemeents, then the cache would have two data element and we would write
# back both even if one was dirty. This takes care of the boundry condition.
if (wbAddr >= (self.numInstructions * 4) + 96):
self.dataval[ SetUp.getIndexOfMemAddress(wbAddr,False, self.dataval, self.address, self.numInstructions) ] = \
self.cacheSets[setNum][ self.lruBit[setNum] ][3]
if (wbAddr + 4 >= (self.numInstructions * 4) + 96):
self.dataval[ SetUp.getIndexOfMemAddress(wbAddr+4,False, self.dataval, self.address, self.numInstructions) ] = \
self.cacheSets[setNum][ self.lruBit[setNum] ][4]
# now update the cache flag bits
self.cacheSets[setNum][
self.lruBit[setNum]][0] = 1 #valid we are writing a block
self.cacheSets[setNum][
self.lruBit[setNum]][1] = 0 #reset the dirty bit
if (isWriteToMem):
self.cacheSets[setNum][self.lruBit[setNum]][
1] = 1 #dirty if is data mem is dirty again, intruction mem never dirty
# update both words in the actual cache block in set
self.cacheSets[setNum][self.lruBit[setNum]][2] = tag #tag
self.cacheSets[setNum][self.lruBit[setNum]][3] = data1 #data
self.cacheSets[setNum][self.lruBit[setNum]][4] = data2 #nextData
self.lruBit[setNum] = (
self.lruBit[setNum] +
1) % 2 # set lru to show block is recently used
#finally
return [
True, self.cacheSets[setNum][(self.lruBit[setNum] + 1) %
2][dataWord + 3]
] # dataword was the actual word thatgenerated the hit
else:
#VALID MISS on cycle
# add the memory address to the just missed list if its not already there
if (self.justMissedList.count(address1) == 0):
self.justMissedList.append(address1)
return [False, 0]
def run(self):
instructions = []
instructions = SetUp.import_data_file()
outputFilename = SetUp.get_output_filename()
print("raw output filename is ", outputFilename)
# creates address list with appropriate length
for i in range(len(instructions)):
self.address.append(96 + (i * 4))
opcode = []
# creates an opcode list by selecting the 11 left most bits
for z in instructions:
opcode.append(int(z, base=2) >> 21)
for i in range(len(opcode)):
self.numInstructs = self.numInstructs + 1
""" # R-type """
if opcode[i] == 1112: # ADD OPCODE
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ADD")
self.arg1.append((int(instructions[i], base=2)
& MASKS.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKS.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1624: # SUB OPCODE
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("SUB")
self.arg1.append((int(instructions[i], base=2)
& MASKS.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKS.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1104: # AND OPCODE
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("AND")
self.arg1.append((int(instructions[i], base=2)
& MASKS.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKS.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1360: # ORR OPCODE
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ORR")
self.arg1.append((int(instructions[i], base=2)
& MASKS.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKS.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1690: # LSR OPCODE
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSR")
self.arg1.append((int(instructions[i], base=2)
& MASKS.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKS.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] == 1691: # LSL OPCODE
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSL")
self.arg1.append((int(instructions[i], base=2)
& MASKS.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKS.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] == 1692: # ASR OPCODE
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ASR")
self.arg1.append((int(instructions[i], base=2)
& MASKS.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKS.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1872: # EOR OPCODE
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("EOR")
self.arg1.append((int(instructions[i], base=2)
& MASKS.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKS.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
"""# B-Type"""
elif 160 <= opcode[i] <= 191: # B OPCODE
self.instrSpaced.append(
SetUp.bin2StringSpacedB(instructions[i]))
self.opcodeStr.append("B")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter(
(int(instructions[i], base=2) & MASKS.bMask), 26))
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("#" + str(self.arg1[i]))
self.arg2Str.append("")
self.arg3Str.append("")
"""# I-Type"""
elif 1160 <= opcode[i] <= 1161: # ADDI OPCODE RANGE
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("ADDI")
self.arg1.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg2.append((int(instructions[i], base=2)
& MASKS.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKS.imMask) >> 10)
self.arg1Str.append("R" + str(self.arg1[i]))
self.arg2Str.append(", R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg3[i]))
elif 1672 <= opcode[i] <= 1673: # SUBI OPCODE RANGE
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("SUBI")
self.arg1.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg2.append((int(instructions[i], base=2)
& MASKS.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKS.imMask) >> 10)
self.arg1Str.append("R" + str(self.arg1[i]))
self.arg2Str.append(", R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg3[i]))
""""# D-Type"""
elif opcode[i] == 1984: # STUR OPCODE
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("STUR")
self.arg1.append((int(instructions[i], base=2)
& MASKS.addrMask) >> 12)
self.arg2.append((int(instructions[i], base=2)
& MASKS.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", [R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]) + "]")
elif opcode[i] == 1986: # LDUR OPCODE
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("LDUR")
self.arg1.append((int(instructions[i], base=2)
& MASKS.addrMask) >> 12)
self.arg2.append((int(instructions[i], base=2)
& MASKS.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", [R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]) + "]")
""""# CB Type"""
elif 1440 <= opcode[i] <= 1447: # CBZ OPCODE RANGE
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBZ ")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter(
(int(instructions[i], base=2) & MASKS.addr2Mask) >> 5,
19))
self.arg2.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg3.append(0)
self.arg1Str.append("R" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
elif 1448 <= opcode[i] <= 1455: # CBNZ OPCODE RANGE
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBNZ")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter(
(int(instructions[i], base=2) & MASKS.addr2Mask) >> 5,
19))
self.arg2.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg3.append(0)
self.arg1Str.append("R" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
""""# IM Type"""
elif 1684 <= opcode[i] <= 1687: # MOVZ OPCODE RANGE
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVZ")
self.arg1.append(
((int(instructions[i], base=2) & MASKS.imsftMask) >> 21) *
16) # need to send to
self.arg2.append((int(instructions[i], base=2)
& MASKS.imdataMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", " + str(self.arg2[i]))
self.arg3Str.append(", LSL " + str(self.arg1[i]))
elif 1940 <= opcode[i] <= 1943: # MOVK OPCODE RANGE
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVK")
self.arg1.append(
((int(instructions[i], base=2) & MASKS.imsftMask) >> 21) *
16) # need to send to
self.arg2.append((int(instructions[i], base=2)
& MASKS.imdataMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKS.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", " + str(self.arg2[i]))
self.arg3Str.append(", LSL " + str(self.arg1[i]))
"""NOP"""
elif opcode[i] == 0: # NOP OPCODE
self.instrSpaced.append(SetUp.bin2StringSpaced(
instructions[i]))
self.opcodeStr.append("NOP")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
""""# Break"""
elif opcode[i] == 2038 and (
int(instructions[i], base=2)
& MASKS.specialMask) == 2031591: # BREAK OPCODE
self.instrSpaced.append(SetUp.bin2StringSpaced(
instructions[i]))
self.opcodeStr.append("BREAK")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
# print("breaking\n")
break
else:
self.opcodeStr.append("unknown")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
print("i =: " + str(i))
print("opcode =: " + str(opcode[i]))
sys.exit(
"You have found an unknown instruction, investigate NOW")
counter = 0
for j in range(self.numInstructs, len(instructions)):
self.rawdata.append(instructions[j])
self.dataval.append(
SetUp.imm_32_bit_unsigned_to_32_bit_signed_converter(
int(self.rawdata[counter], base=2)))
counter += 1
return {
"opcode": opcode,
"dataval": self.dataval,
"address": self.address,
"numInstructs": self.numInstructs,
"arg1": self.arg1,
"arg2": self.arg2,
"arg3": self.arg3,
"opcodeStr": self.opcodeStr,
"arg1Str": self.arg1Str,
"arg2Str": self.arg2Str,
"arg3Str": self.arg3Str
}
def run(self):
instructions = []
instructions = SetUp.import_data_file()
outputFileName = SetUp.get_output_filename()
print("raw output filename is ", outputFileName)
# Create an address list with appropriate length
for i in range(len(instructions)):
self.address.append(96 + (i * 4))
opcode = []
# Create an opcode list by selecting the left 11 bits
for z in instructions:
opcode.append(int(z, base=2) >> 21)
# Now the fun begins! Decode and dissect!
for i in range(len(opcode)):
self.numInstructs = self.numInstructs + 1
if opcode[i] == 1112:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ADD")
self.arg1.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& masks.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1624:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("SUB")
self.arg1.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& masks.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1160 or opcode[i] == 1161:
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("ADDI")
self.arg1.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg3.append((int(instructions[i], base=2)
& masks.imMask) >> 10)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg3[i]))
elif opcode[i] == 1360:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ORR")
self.arg1.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& masks.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1104:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("AND")
self.arg1.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& masks.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif 1440 <= opcode[i] <= 1447:
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBZ")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter((
(int(instructions[i], base=2) & masks.addr2Mask) >> 5),
19))
self.arg2.append((int(instructions[i], base=2) & masks.rdMask))
self.arg3.append(0)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
elif 1448 <= opcode[i] <= 1455:
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBNZ")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter((
(int(instructions[i], base=2) & masks.addr2Mask) >> 5),
19))
self.arg2.append(
(int(instructions[i], base=2) & masks.rdMask) >>
0) # We Need to treat the conditional as rd for mask
self.arg3.append(0)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
elif 1672 <= opcode[i] <= 1673:
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("SUBI")
self.arg1.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg3.append((int(instructions[i], base=2)
& masks.imMask) >> 10)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg3[i]))
elif 1684 <= opcode[i] <= 1687:
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVZ")
self.arg1.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg2.append((int(instructions[i], base=2)
& masks.imdataMask) >> 5)
self.arg3.append(
((int(instructions[i], base=2) & masks.imsftMask) >> 21) *
16)
self.arg1Str.append("\tR" + str(self.arg1[i]))
self.arg2Str.append(", " + str(self.arg2[i]))
self.arg3Str.append(", LSL " + str(self.arg3[i]))
elif 1940 <= opcode[i] <= 1943:
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVK")
self.arg1.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg2.append((int(instructions[i], base=2)
& masks.imdataMask) >> 5)
self.arg3.append(
((int(instructions[i], base=2) & masks.imsftMask) >> 21) *
16)
self.arg1Str.append("\tR" + str(self.arg1[i]))
self.arg2Str.append(", " + str(self.arg2[i]))
self.arg3Str.append(", LSL " + str(self.arg3[i]))
elif opcode[i] == 1690:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSR")
self.arg1.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg2.append(
SetUp.imm_bit_to_32_bit_converter((
(int(instructions[i], base=2) & masks.shmtMask) >> 10),
6))
self.arg3.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] == 1691:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSL")
self.arg1.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg2.append(
SetUp.imm_bit_to_32_bit_converter((
(int(instructions[i], base=2) & masks.shmtMask) >> 10),
6))
self.arg3.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] == 1984:
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("STUR")
self.arg1.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg2.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg3.append(
SetUp.imm_bit_to_32_bit_converter((
(int(instructions[i], base=2) & masks.addrMask) >> 12),
9))
self.arg1Str.append("\tR" + str(self.arg1[i]))
self.arg2Str.append(", [R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg3[i]) + "]")
elif opcode[i] == 1986:
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("LDUR")
self.arg1.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg2.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg3.append(
SetUp.imm_bit_to_32_bit_converter((
(int(instructions[i], base=2) & masks.addrMask) >> 12),
9))
self.arg1Str.append("\tR" + str(self.arg1[i]))
self.arg2Str.append(", [R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg3[i]) + "]")
elif opcode[i] == 1692:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ASR")
self.arg1.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg2.append(
SetUp.imm_bit_to_32_bit_converter((
(int(instructions[i], base=2) & masks.shmtMask) >> 10),
6))
self.arg3.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] == 1872:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("EOR")
self.arg1.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& masks.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1360:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ORR")
self.arg1.append((int(instructions[i], base=2)
& masks.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& masks.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& masks.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif 160 <= opcode[i] <= 191:
self.instrSpaced.append(
SetUp.bin2StringSpacedB(instructions[i]))
self.opcodeStr.append("B")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter(
(int(instructions[i], base=2) & masks.bMask) >> 0, 26))
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("\t#" + str(self.arg1[i]))
self.arg2Str.append("")
self.arg3Str.append("")
elif opcode[i] == 2038 and (int(instructions[i], base=2)
& masks.specialMask) == 2031591:
self.instrSpaced.append(SetUp.bin2StringSpaced(
instructions[i]))
self.opcodeStr.append("BREAK")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
print("breaking")
break
elif opcode[i] == 0:
self.instrSpaced.append(SetUp.bin2StringSpaced(
instructions[i]))
self.opcodeStr.append("NOP")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
else:
self.opcodeStr.append("unknown")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
print("i=: " + str(opcode[i]))
sys.exit(
"You have found an unknown instruction, investigate NOW")
# I created parser here because I needed to preserve/reference numInstructs as the beginning of the rawData at a later time
# Read in the 32 bit strings raw into this vector, will be used for printing and handing data to the converter
parser = self.numInstructs
while parser < len(opcode):
self.rawdata.append(int(instructions[parser]))
parser = parser + 1
# Convert the signed 32 bit strings into a signed int and store them in the dataval vector for printing later
for i in range(len(self.rawdata)):
self.dataval.append(
SetUp.imm_32_bit_unsigned_to_32_bit_signed_converter(
int(self.rawdata[i])))
def run(self):
instructions = []
instructions = SetUp.import_data_file()
outputFilename = SetUp.get_output_filename()
print("raw output filename is ", outputFilename)
# create an address list with appropriate length
for i in range(len(instructions)):
self.address.append(96 + (i * 4))
opcode = []
# create an opcode list by selecting the left 11 bits
for z in instructions:
opcode.append(int(z, base=2) >> 21)
# decode and dissect :) no bugs in this class
for i in range(len(opcode)):
self.numInstructs = self.numInstructs + 1
if opcode[i] == 1112:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ADD")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1104:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("AND")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1360:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ORR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1624:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("SUB")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1690:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1691:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSL")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1692:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ASR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1872:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("EOR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif 1684 <= opcode[i] <= 1687:
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVZ")
self.arg1.append(
((int(instructions[i], base=2) & self.imsftMask) >> 21) *
16)
self.arg2.append((int(instructions[i], base=2)
& self.addr2Mask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg2[i]))
self.arg3Str.append(", LSL " + str(self.arg1[i]))
elif 1940 <= opcode[i] <= 1943:
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVK")
self.arg1.append(
((int(instructions[i], base=2) & self.imsftMask) >> 21) *
16)
self.arg2.append((int(instructions[i], base=2)
& self.addr2Mask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg2[i]))
self.arg3Str.append(", LSL " + str(self.arg1[i]))
elif 1440 <= opcode[i] <= 1447:
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBZ")
self.arg1.append(
SetUp.immSignedToTwosConverter(
(int(instructions[i], base=2) & self.addr2Mask) >> 5))
self.arg2.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg3.append(0)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
elif 1448 <= opcode[i] <= 1455:
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBNZ")
self.arg1.append(
SetUp.immSignedToTwosConverter(
(int(instructions[i], base=2) & self.addr2Mask) >> 5))
self.arg2.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg3.append(0)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
elif 1160 <= opcode[i] <= 1161:
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("ADDI")
self.arg1.append((int(instructions[i], base=2)
& self.imMask) >> 10)
self.arg2.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg2[i]))
self.arg3Str.append(", R" + str(self.arg1[i]))
elif 1672 <= opcode[i] <= 1673:
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("SUBI")
self.arg1.append((int(instructions[i], base=2)
& self.imMask) >> 10)
self.arg2.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg2[i]))
self.arg3Str.append(", R" + str(self.arg1[i]))
elif opcode[i] == 1984:
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("STUR")
self.arg1.append((int(instructions[i], base=2)
& self.addrMask) >> 12)
self.arg2.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", [R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]) + "]")
elif opcode[i] == 1986:
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("LDUR")
self.arg1.append((int(instructions[i], base=2)
& self.addrMask) >> 12)
self.arg2.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", [R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]) + "]")
elif 160 <= opcode[i] <= 191:
self.instrSpaced.append(
SetUp.bin2StringSpacedB(instructions[i]))
self.opcodeStr.append("B")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter(
(int(instructions[i], base=2) & self.bMask), 26))
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("\t#" + str(self.arg1[i]))
self.arg2Str.append("")
self.arg3Str.append("")
elif opcode[i] == 0:
self.instrSpaced.append(0)
self.opcodeStr.append("NOP")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
elif opcode[i] == 2038:
self.instrSpaced.append(SetUp.bin2StringSpaced(
instructions[i]))
self.opcodeStr.append("BREAK")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
else:
self.instrSpaced.append(instructions[i])
self.opcodeStr.append(
SetUp.immSignedToTwosConverter(int(instructions[i],
base=2)))
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
def printState(self):
outputFileName = SetUp.get_output_filename()
with open(outputFileName + "_pipeline.txt", 'a') as outFile:
outFile.write("--------------------\n")
outFile.write("Cycle " + str(self.cycle) + ":\n\n")
outFile.write("Pre-Issue Buffer:\n")
if self.preIssueBuff[0] != -1:
outFile.write("\tEntry 0:\t" +
str(self.opcodeStr[self.preIssueBuff[0]]) +
str(self.arg1Str[self.preIssueBuff[0]]) +
str(self.arg2Str[self.preIssueBuff[0]]) +
str(self.arg3Str[self.preIssueBuff[0]]) + '\n')
else:
outFile.write("\tEntry 0:\t\n")
if self.preIssueBuff[1] != -1:
outFile.write("\tEntry 1:\t" +
str(self.opcodeStr[self.preIssueBuff[1]]) +
str(self.arg1Str[self.preIssueBuff[1]]) +
str(self.arg2Str[self.preIssueBuff[1]]) +
str(self.arg3Str[self.preIssueBuff[1]]) + '\n')
else:
outFile.write("\tEntry 1:\t\n")
if self.preIssueBuff[2] != -1:
outFile.write("\tEntry 2:\t" +
str(self.opcodeStr[self.preIssueBuff[2]]) +
str(self.arg1Str[self.preIssueBuff[2]]) +
str(self.arg2Str[self.preIssueBuff[2]]) +
str(self.arg3Str[self.preIssueBuff[2]]) + '\n')
else:
outFile.write("\tEntry 2:\t\n")
if self.preIssueBuff[3] != -1:
outFile.write("\tEntry 3:\t" +
str(self.opcodeStr[self.preIssueBuff[3]]) +
str(self.arg1Str[self.preIssueBuff[3]]) +
str(self.arg2Str[self.preIssueBuff[3]]) +
str(self.arg3Str[self.preIssueBuff[3]]) + '\n')
else:
outFile.write("\tEntry 3:\t\n")
outFile.write("Pre_ALU Queue:\n")
if self.preALUBuff[0] != -1:
outFile.write("\tEntry 0:\t" +
str(self.opcodeStr[self.preALUBuff[0]]) +
str(self.arg1Str[self.preALUBuff[0]]) +
str(self.arg2Str[self.preALUBuff[0]]) +
str(self.arg3Str[self.preALUBuff[0]]) + '\n')
else:
outFile.write("\tEntry 0:\t\n")
if self.preALUBuff[1] != -1:
outFile.write("\tEntry 1:\t" +
str(self.opcodeStr[self.preALUBuff[1]]) +
str(self.arg1Str[self.preALUBuff[1]]) +
str(self.arg2Str[self.preALUBuff[1]]) +
str(self.arg3Str[self.preALUBuff[1]]) + '\n')
else:
outFile.write("\tEntry 1:\t\n")
outFile.write("Post_ALU Queue:\n")
if self.postALUBuff[0] != -1:
outFile.write("\tEntry 0:\t" +
str(self.opcodeStr[self.postALUBuff[0]]) +
str(self.arg1Str[self.postALUBuff[0]]) +
str(self.arg2Str[self.postALUBuff[0]]) +
str(self.arg3Str[self.postALUBuff[0]]) + '\n')
else:
outFile.write("\tEntry 0:\t\n")
outFile.write("Pre_MEM Queue:\n")
if self.preMemBuff[0] != -1:
outFile.write("\tEntry 0:\t" +
str(self.opcodeStr[self.preMemBuff[0]]) +
str(self.arg1Str[self.preMemBuff[0]]) +
str(self.arg2Str[self.preMemBuff[0]]) +
str(self.arg3Str[self.preMemBuff[0]]) + '\n')
else:
outFile.write("\tEntry 0:\t\n")
if self.preMemBuff[1] != -1:
outFile.write("\tEntry 1:\t" +
str(self.opcodeStr[self.preMemBuff[1]]) +
str(self.arg1Str[self.preMemBuff[1]]) +
str(self.arg2Str[self.preMemBuff[1]]) +
str(self.arg3Str[self.preMemBuff[1]]) + '\n')
else:
outFile.write("\tEntry 1:\t\n")
outFile.write("Post_MEM Queue:\n")
if self.postMemBuff[0] != -1:
outFile.write("\tEntry 0:\t" +
str(self.opcodeStr[self.postMemBuff[0]]) +
str(self.arg1Str[self.postMemBuff[0]]) +
str(self.arg2Str[self.postMemBuff[0]]) +
str(self.arg3Str[self.postMemBuff[0]]) + '\n')
else:
outFile.write("\tEntry 0:\t\n")
outFile.write("\nRegisters\n")
outStr = "R00:"
for i in range(0, 8):
outStr = outStr + "\t" + str(self.R[i])
outFile.write(outStr + "\n")
outStr = "R08:"
for i in range(8, 16):
outStr = outStr + "\t" + str(self.R[i])
outFile.write(outStr + "\n")
outStr = "R16:"
for i in range(16, 24):
outStr = outStr + "\t" + str(self.R[i])
outFile.write(outStr + "\n")
outStr = "R24:"
for i in range(24, 32):
outStr = outStr + "\t" + str(self.R[i])
outFile.write(outStr + "\n\n")
outFile.write("Cache\n")
outFile.write("Set 0: LRU=" + str(self.cache.lruBit[0]) + "\n")
outFile.write("\tEntry 0: [(" +
str(self.cache.cacheSets[0][0][0]) + ", " +
str(self.cache.cacheSets[0][0][1]) + ", " +
str(self.cache.cacheSets[0][0][2]) + ")<" +
str(self.cache.cacheSets[0][0][3]) + ", " +
str(self.cache.cacheSets[0][0][4]) + ">]\n")
outFile.write("\tEntry 1: [(" +
str(self.cache.cacheSets[0][1][0]) + ", " +
str(self.cache.cacheSets[0][1][1]) + ", " +
str(self.cache.cacheSets[0][1][2]) + ")<" +
str(self.cache.cacheSets[0][1][3]) + ", " +
str(self.cache.cacheSets[0][1][4]) + ">]\n")
outFile.write("Set 1: LRU=" + str(self.cache.lruBit[1]) + "\n")
outFile.write("\tEntry 0: [(" +
str(self.cache.cacheSets[0][0][0]) + ", " +
str(self.cache.cacheSets[1][0][1]) + ", " +
str(self.cache.cacheSets[1][0][2]) + ")<" +
str(self.cache.cacheSets[1][0][3]) + ", " +
str(self.cache.cacheSets[1][0][4]) + ">]\n")
outFile.write("\tEntry 1: [(" +
str(self.cache.cacheSets[0][1][0]) + ", " +
str(self.cache.cacheSets[1][1][1]) + ", " +
str(self.cache.cacheSets[1][1][2]) + ")<" +
str(self.cache.cacheSets[1][1][3]) + ", " +
str(self.cache.cacheSets[1][1][4]) + ">]\n")
outFile.write("Set 2: LRU=" + str(self.cache.lruBit[2]) + "\n")
outFile.write("\tEntry 0: [(" +
str(self.cache.cacheSets[2][0][0]) + ", " +
str(self.cache.cacheSets[2][0][1]) + ", " +
str(self.cache.cacheSets[2][0][2]) + ")<" +
str(self.cache.cacheSets[2][0][3]) + ", " +
str(self.cache.cacheSets[2][0][4]) + ">]\n")
outFile.write("\tEntry 1: [(" +
str(self.cache.cacheSets[2][1][0]) + ", " +
str(self.cache.cacheSets[2][1][1]) + ", " +
str(self.cache.cacheSets[2][1][2]) + ")<" +
str(self.cache.cacheSets[2][1][3]) + ", " +
str(self.cache.cacheSets[2][1][4]) + ">]\n")
outFile.write("Set 3: LRU=" + str(self.cache.lruBit[3]) + "\n")
outFile.write("\tEntry 0: [(" +
str(self.cache.cacheSets[3][0][0]) + ", " +
str(self.cache.cacheSets[3][0][1]) + ", " +
str(self.cache.cacheSets[3][0][2]) + ")<" +
str(self.cache.cacheSets[3][0][3]) + ", " +
str(self.cache.cacheSets[3][0][4]) + ">]\n")
outFile.write("\tEntry 1: [(" +
str(self.cache.cacheSets[3][1][0]) + ", " +
str(self.cache.cacheSets[3][1][1]) + ", " +
str(self.cache.cacheSets[3][1][2]) + ")<" +
str(self.cache.cacheSets[3][1][3]) + ", " +
str(self.cache.cacheSets[3][1][4]) + ">]\n")
outFile.write("\nData\n")
outStr = "\n"
for i in range(len(self.dataval)):
if i % 8 == 0 and i != 0 or i == len(self.dataval):
outFile.write(outStr + "\n")
if i % 8 == 0:
outStr = str(
self.address[i + self.numInstructions]) + ":" + str(
self.dataval[i])
if (i % 8 != 0):
outStr = outStr + "\t" + str(self.dataval[i])
outFile.write(outStr + "\n")
outFile.close()
def run(self):
instructions = []
instructions = SetUp.import_data_file()
for i in instructions:
print(i)
outputFilename = SetUp.get_output_filename()
print("raw output filename is ", outputFilename)
print(hex(MASKs.bMask))
print(bin(MASKs.bMask))
print(f'{MASKs.bMask:032b}')
for i in range(len(instructions)):
self.address.append(96 + (i * 4))
opcode = []
for z in instructions:
opcode.append(int(z, base=2) >> 21)
for i in range(len(opcode)):
self.numInstructs = self.numInstructs + 1
if opcode[i] == 1112:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ADD")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1624:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("SUB")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1104:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("AND")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1360:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ORR")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] >= 160 and opcode[i] <= 191:
self.instrSpaced.append(
SetUp.bin2StringSpacedB(instructions[i]))
self.opcodeStr.append("B")
bImm = int(instructions[i], base=2) & MASKs.bMask
self.arg1.append(SetUp.imm_bit_to_32_bit_converter(bImm, 26))
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("\t#" + str(self.arg1[i]))
self.arg2Str.append("")
self.arg3Str.append("")
elif opcode[i] >= 1160 and opcode[i] <= 1161:
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("ADDI")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.imMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] >= 1672 and opcode[i] <= 1673:
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("SUBI")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.imMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] == 1986:
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("LDUR")
self.arg1.append((int(instructions[i], base=2)
& MASKs.addrMask) >> 12)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", [R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]) + "]")
elif opcode[i] == 1984:
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("STUR")
self.arg1.append((int(instructions[i], base=2)
& MASKs.addrMask) >> 12)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", [R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]) + "]")
elif opcode[i] >= 1440 and opcode[i] <= 1447:
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBZ")
cbAddr = (int(instructions[i], base=2) & MASKs.addr2Mask) >> 5
self.arg1.append(SetUp.imm_bit_to_32_bit_converter(cbAddr, 19))
self.arg2.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg3.append(0)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
elif opcode[i] >= 1448 and opcode[i] <= 1455:
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBNZ")
cbnzAddr = (int(instructions[i], base=2)
& MASKs.addr2Mask) >> 5
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter(cbnzAddr, 19))
self.arg2.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg3.append(0)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
elif opcode[i] >= 1684 and opcode[i] <= 1687:
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVZ")
self.arg1.append((int(instructions[i], base=2)
& MASKs.imsftMask) >> 21)
self.arg1[i] = self.arg1[i] * 16
self.arg2.append((int(instructions[i], base=2)
& MASKs.imdataMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(" ," + str(self.arg2[i]) + ", LSL")
self.arg3Str.append(" " + str(self.arg1[i]))
elif opcode[i] >= 1940 and opcode[i] <= 1943:
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVK")
self.arg1.append((int(instructions[i], base=2)
& MASKs.imsftMask) >> 21)
self.arg1[i] = self.arg1[i] * 16
self.arg2.append((int(instructions[i], base=2)
& MASKs.imdataMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(" ," + str(self.arg2[i]) + ", LSL")
self.arg3Str.append(" " + str(self.arg1[i]))
elif opcode[i] == 1690:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSR")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] == 1691:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSL")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] == 1692:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ASR")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] == 1872:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("EOR")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 0:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("NOP")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
elif opcode[i] == 2038 and (int(instructions[i], base=2)
& MASKs.specialMask) == 2031591:
self.instrSpaced.append(SetUp.bin2StringSpaced(
instructions[i]))
self.opcodeStr.append("BREAK")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
print("breaking")
break
else:
self.opcodeStr.append("unknown")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
print("i =: " + str(i))
print("opcode =: " + str(opcode[i]))
sys.exit(
"You have found an unknown instruction, investigate NOW")
#Reading Raw Data
k = self.numInstructs
while k < len(opcode):
self.rawdata.append(instructions[k])
k = k + 1
for i in range(len(self.rawdata)):
self.dataval.append(
SetUp.immSignedToTwosConverter(int(self.rawdata[i], base=2)))
return {
"opcode": opcode,
"opcodeStr": self.opcodeStr,
"arg1": self.arg1,
"arg1Str": self.arg1Str,
"arg2": self.arg2,
"arg2Str": self.arg2Str,
"arg3": self.arg3,
"arg3Str": self.arg3Str,
"dataval": self.dataval,
"address": self.address,
"numInstructs": self.numInstructs
}
def printState(self):
outputFileName = SetUp.get_output_filename()
with open(outputFileName + "_pipeline.txt", 'a') as outFile:
outFile.write("--------------------\n")
outFile.write("Cycle: " + str(self.cycle) + "\n\n")
# print the pre issue buffer
outFile.write("Pre-Issue Buffer:\n")
for i in range(0, len(self.preIssueBuff)):
outFile.write("\tEntry " + str(i) + ":\t")
if self.preIssueBuff[i] != -1:
outFile.write("[" +
str(self.opcodeStr[self.preIssueBuff[i]]) +
self.arg1Str[self.preIssueBuff[i]] +
self.arg2Str[self.preIssueBuff[i]] +
self.arg3Str[self.preIssueBuff[i]] + "]\n")
else:
outFile.write("\n")
# print the pre alu buffer
outFile.write("Pre-ALU Queue:\n")
for i in range(0, len(self.preALUbuff)):
outFile.write("\tEntry " + str(i) + ":\t")
if self.preALUbuff[i] != -1:
outFile.write("[" + self.opcodeStr[self.preALUbuff[i]] +
self.arg1Str[self.preALUbuff[i]] +
self.arg2Str[self.preALUbuff[i]] +
self.arg3Str[self.preALUbuff[i]] + "]\n")
else:
outFile.write("\n")
# print the post alu buffer
outFile.write("Post-ALU Queue:\n")
outFile.write("\tEntry 0:\t")
if self.postALUbuff[0] != -1:
outFile.write("[" + self.opcodeStr[self.postALUbuff[1]] +
self.arg1Str[self.postALUbuff[1]] +
self.arg2Str[self.postALUbuff[1]] +
self.arg3Str[self.postALUbuff[1]] + "]\n")
else:
outFile.write("\n")
# print the pre mem buff
outFile.write("Pre-MEM Queue:\n")
for i in range(0, len(self.preMEMbuff)):
outFile.write("\tEntry " + str(i) + ":\t")
if self.preMEMbuff[i] != -1:
outFile.write("[" + self.opcodeStr[self.preMEMbuff[i]] +
self.arg1Str[self.preMEMbuff[i]] +
self.arg2Str[self.preMEMbuff[i]] +
self.arg3Str[self.preMEMbuff[i]] + "]\n")
else:
outFile.write("\n")
# print the post mem buff
outFile.write("Post-MEM Queue:\n")
outFile.write("\tEntry 0:\t")
if self.postMEMbuff[0] != -1:
outFile.write("[" + self.opcodeStr[self.postMEMbuff[0]] +
self.arg1Str[self.postMEMbuff[0]] +
self.arg2Str[self.postMEMbuff[0]] +
self.arg3Str[self.postMEMbuff[0]] + "]\n\n")
else:
outFile.write("\n\n")
# print the Register list
outFile.write("Registers:\n")
regNumber = 0
while regNumber < len(self.R):
if (regNumber % 8) == 0:
outFile.write("\n" + "r" + str(int(regNumber)).zfill(2) +
":\t" + str(self.R[regNumber]) + "\t")
else:
outFile.write(str(self.R[regNumber]) + "\t")
regNumber += 1
# print the cache list
outFile.write("\n\nCache:\n")
for i in range(0, len(self.cache.cacheSets)):
outFile.write("Set " + str(i) + ":\tLRU=" +
str(self.cache.lruBit[i]) + "\n")
for j in range(0, len(self.cache.cacheSets[i])):
outFile.write("\tEntry " + str(j) + ":[(")
for k in range(3):
if k != 2:
outFile.write(
str(self.cache.cacheSets[i][j][k]) + ",")
else:
outFile.write(
str(self.cache.cacheSets[i][j][k]) + ")<")
outFile.write(
str(self.cache.cacheSets[i][j][3]) + "," +
str(self.cache.cacheSets[i][j][4]) + ">]")
outFile.write("\n")
# print the data list
outFile.write("\nData\n")
if len(self.dataval) != 0:
outStr = ""
a = self.address[self.numInstructs - 1] + 4
for i in range(len(self.dataval)):
if (i % 8) == 0 and i != 0 or i == len(self.dataval):
outFile.write(outStr + "\n")
if (i % 8) == 0:
outStr = str(a) + ":\t" + str(self.dataval[i])
a += (8 * 4)
if (i % 8) != 0:
outStr = outStr + "\t" + str(self.dataval[i])
outFile.write(outStr + "\n")
outFile.write("\n\n\n")
outFile.close()
def run(self):
instructions = []
inputfile = SetUp.get_input_filename()
instructions = SetUp.import_data_file()
outputFilename = SetUp.get_output_filename()
print("raw output filename is ", outputFilename)
# create an address list with appropriate length
for i in range(len(instructions)):
self.address.append(96 + (i * 4))
opcode = []
# create an opcode list by selecting the left 11 bits
for z in instructions:
opcode.append(int(z, base=2) >> 21)
# decode and dissect :) no bugs in this class
for i in range(len(opcode)):
self.numInstructs = self.numInstructs + 1
if opcode[i] == 1112:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ADD")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif opcode[i] == 1104:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("AND")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif opcode[i] == 1360:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ORR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif opcode[i] == 1624:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("SUB")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif opcode[i] == 1690:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(-1)
elif opcode[i] == 1691:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSL")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(-2)
elif opcode[i] == 1692:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ASR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif opcode[i] == 1872:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("EOR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif 1684 <= opcode[i] <= 1687:
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVZ")
self.arg1.append(
((int(instructions[i], base=2) & self.imsftMask) >> 21) *
16)
self.arg2.append((int(instructions[i], base=2)
& self.imdataMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", " + str(self.arg2[i]))
self.arg3Str.append(", LSL " + str(self.arg1[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(-3)
self.src2Reg.append(-4)
elif 1940 <= opcode[i] <= 1943:
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVK")
self.arg1.append(
((int(instructions[i], base=2) & self.imsftMask) >> 21) *
16)
self.arg2.append((int(instructions[i], base=2)
& self.imdataMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", " + str(self.arg2[i]))
self.arg3Str.append(", LSL " + str(self.arg1[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(-5)
self.src2Reg.append(-6)
elif 1440 <= opcode[i] <= 1447:
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBZ")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter(
(int(instructions[i], base=2) & self.addr2Mask) >> 5,
19))
self.arg2.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg3.append(0)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
self.destReg.append(-7)
self.src1Reg.append(-8)
self.src2Reg.append(-9)
elif 1448 <= opcode[i] <= 1455:
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBNZ")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter(
(int(instructions[i], base=2) & self.addr2Mask) >> 5,
19))
self.arg2.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg3.append(0)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
self.destReg.append(-10)
self.src1Reg.append(-11)
self.src2Reg.append(-12)
elif 1160 <= opcode[i] <= 1161:
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("ADDI")
self.arg1.append((int(instructions[i], base=2)
& self.imMask) >> 10)
self.arg2.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(-13)
self.src2Reg.append(self.arg2[i])
elif 1672 <= opcode[i] <= 1673:
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("SUBI")
self.arg1.append((int(instructions[i], base=2)
& self.imMask) >> 10)
self.arg2.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(-14)
self.src2Reg.append(self.arg2[i])
elif opcode[i] == 1984:
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("STUR")
self.arg1.append((int(instructions[i], base=2)
& self.addrMask) >> 12)
self.arg2.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", [R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]) + "]")
self.destReg.append(-15)
self.src1Reg.append(-16)
self.src2Reg.append(-17)
elif opcode[i] == 1986:
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("LDUR")
self.arg1.append((int(instructions[i], base=2)
& self.addrMask) >> 12)
self.arg2.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", [R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]) + "]")
self.destReg.append(-18)
self.src1Reg.append(-18)
self.src2Reg.append(-19)
elif 160 <= opcode[i] <= 191:
self.instrSpaced.append(
SetUp.bin2StringSpacedB(instructions[i]))
self.opcodeStr.append("B")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter(
int(instructions[i], base=2) & self.bMask, 26))
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("\t#" + str(self.arg1[i]))
self.arg2Str.append("")
self.arg3Str.append("")
self.destReg.append(-20)
self.src1Reg.append(-21)
self.src2Reg.append(-22)
elif opcode[i] == 0:
if int(instructions[i], base=2) == 0:
self.instrSpaced.append(
SetUp.bin2StringSpaced(instructions[i]))
self.opcodeStr.append("NOP")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
self.destReg.append(-23)
self.src1Reg.append(-24)
self.src2Reg.append(-25)
else:
self.instrSpaced.append(instructions[i])
self.opcodeStr.append(
SetUp.immSignedToTwosConverter(
int(instructions[i], base=2)))
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
self.dataval.append(int(instructions[i], base=2))
self.numInstructs -= 1
elif opcode[i] == 2038:
self.instrSpaced.append(SetUp.bin2StringSpaced(
instructions[i]))
self.opcodeStr.append("BREAK")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
self.destReg.append(-26)
self.src1Reg.append(-27)
self.src2Reg.append(-28)
else:
self.instrSpaced.append(instructions[i])
self.opcodeStr.append(
SetUp.immSignedToTwosConverter(int(instructions[i],
base=2)))
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
self.dataval.append(int(instructions[i], base=2))
self.numInstructs -= 1
return {
"instructions": instructions,
"opcode": opcode,
"opcodeStr": self.opcodeStr,
"arg1": self.arg1,
"arg1Str": self.arg1Str,
"arg2": self.arg2,
"arg2Str": self.arg2Str,
"arg3": self.arg3,
"arg3Str": self.arg3Str,
"destReg": self.destReg,
"src1Reg": self.src1Reg,
"src2Reg": self.src2Reg,
"dataval": self.dataval,
"address": self.address,
"numInstructs": self.numInstructs
}
def run(self):
pass
instructions = []
instructions = SetUp.import_data_file()
outputFilename = SetUp.get_output_filename()
# print(hex(MASKs.bMask))
# print(bin(MASKs.bMask))
# print(f'{MASKs.bMask:32b}')
# create an address list
for i in range(len(instructions)):
self.address.append(96 + (i * 4))
opcode = []
# create an opcode list
for z in instructions:
opcode.append(int(z, base=2) >> 21)
# decode and dissect
for i in range(len(opcode)):
self.numInstructions = self.numInstructions + 1
# NOP type
if opcode[i] == 0:
self.instrSpaced.append(SetUp.bin2StringSpaced(
instructions[i]))
self.opcodeStr.append("NOP")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
# B type
elif 160 <= opcode[i] <= 191: # B type
self.instrSpaced.append(
SetUp.bin2StringSpacedB(instructions[i]))
self.opcodeStr.append("B")
self.arg1.append((int(instructions[i], base=2)
& self.bMask) >> 0)
self.tempArg = self.arg1[i]
self.tempArg = str(SetUp.decimalToBinary(self.tempArg))
self.tempArg = SetUp.imm_bit_to_32_bit_converter(self.tempArg)
self.tempArg = SetUp.imm_32_bit_unsigned_to_32_bit_signed_converter(
self.tempArg)
self.arg1[i] = self.tempArg
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("\t#" + str(self.arg1[i]))
self.arg2Str.append("")
self.arg3Str.append("")
# AND type
elif opcode[i] == 1104:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("AND")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
# ADD
elif opcode[i] == 1112:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ADD")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
# ADDI
elif 1160 <= opcode[i] <= 1161:
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("ADDI")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.imMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
# ORR
elif opcode[i] == 1360:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ORR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
# CBZ signed
elif 1440 <= opcode[i] <= 1447:
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBZ")
self.arg1.append((int(instructions[i], base=2)
& self.addr2Mask) >> 5)
self.tempArg = self.arg1[i]
self.tempArg = str(SetUp.decimalToBinary(self.tempArg))
self.tempArg = SetUp.imm_bit_to_32_bit_converter(self.tempArg)
self.tempArg = SetUp.imm_32_bit_unsigned_to_32_bit_signed_converter(
self.tempArg)
self.arg1[i] = self.tempArg
self.arg2.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg3.append(0)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
# CBNZ signed
elif 1448 <= opcode[i] <= 1455:
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBNZ")
self.arg1.append((int(instructions[i], base=2)
& self.addr2Mask) >> 5)
self.tempArg = self.arg1[i]
self.tempArg = str(SetUp.decimalToBinary(self.tempArg))
self.tempArg = SetUp.imm_bit_to_32_bit_converter(self.tempArg)
self.tempArg = SetUp.imm_32_bit_unsigned_to_32_bit_signed_converter(
self.tempArg)
self.arg1[i] = self.tempArg
self.arg2.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg3.append(0)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
# SUB
elif opcode[i] == 1624:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("SUB")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
# SUBI
elif 1672 <= opcode[i] <= 1673:
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("SUBI")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.imMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
# MOVZ
elif 1684 <= opcode[i] <= 1687:
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVZ")
self.arg1.append((int(instructions[i], base=2)
& self.imdataMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.imsftMask) >> 17)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", " + str(self.arg1[i]))
self.arg3Str.append(", LSL " + str(self.arg2[i]))
# LSR
elif opcode[i] == 1690:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
# LSL
elif opcode[i] == 1691:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSL")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
# ASR
elif opcode[i] == 1692:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ASR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
# EOR
elif opcode[i] == 1872:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("EOR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
# MOVK
elif 1940 <= opcode[i] <= 1943:
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVK")
self.arg1.append((int(instructions[i], base=2)
& self.imdataMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.imsftMask) >> 17)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", " + str(self.arg1[i]))
self.arg3Str.append(", LSL " + str(self.arg2[i]))
# STUR
elif opcode[i] == 1984:
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("STUR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.addrMask) >> 12)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", [R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]) + "]")
# LDUR
elif opcode[i] == 1986:
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("LDUR")
self.arg1.append((int(instructions[i], base=2)
& self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& self.addrMask) >> 12)
self.arg3.append((int(instructions[i], base=2)
& self.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", [R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]) + "]")
# BREAK
elif opcode[i] == 2038 and (int(instructions[i], base=2)
& self.specialMask) == 2031591:
self.instrSpaced.append(SetUp.bin2StringSpaced(
instructions[i]))
self.opcodeStr.append("BREAK")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
print
"breaking"
break
# NOT A TYPE
else:
self.opcodeStr.append("unkown")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
print("i=: " + str(i))
print("opcode =: " + str(opcode[i]))
sys.exit(
"You have found an unknown instruction, investigate NOW")
# Now read the memory lines
#index = 15 #self.numInstructions
for index in range(self.numInstructions, len(instructions)):
self.rawData.append(instructions[index])
self.dataVal.append(
SetUp.imm_32_bit_unsigned_to_32_bit_signed_converter(
self.rawData[index - self.numInstructions]))
return { #"intructions":instructions
"opcode": opcode,
"opcodeStr": self.opcodeStr,
"arg1": self.arg1,
"arg1Str": self.arg1Str,
"arg2": self.arg2,
"arg2Str": self.arg2Str,
"arg3": self.arg3,
"arg3Str": self.arg3Str,
"dataVal": self.dataVal,
"address": self.address,
"numInstructions": self.numInstructions
}
def run(self):
curr = 0 # integer holding the next instruction to be looked at
numIssued = 0
try:
numInPreIssueBuff = self.sim.preIssueBuff.index(-1)
except ValueError:
numInPreIssueBuff = 4
numInIssueAtClockCycleBegin = numInPreIssueBuff
# check preISSbuff for each instruction and check for RAW hazards
# RAW check - later instruction tries to read an operand before earlier instruction writes it - extremely
# common hazard We will check each preIssueBuff entry against other preIssueBuff entries that are "leftover"
# during processing and against preMEM and preALU. If either source of the current instruction is equal to
# the destination of the previous instructions this is a hazard. This is like a LW issue with a stall and
# forward so we check post buffer too
while numIssued < 2 and numInPreIssueBuff > 0 and curr < 4:
issueMe = True
index = self.sim.preIssueBuff[curr]
if index == -1:
break
if curr > 0:
for i in range(0, curr):
if self.sim.src1Reg[index] == self.sim.destReg[
self.sim.preIssueBuff[i]] or self.sim.src2Reg[
index] == self.sim.destReg[
self.sim.preIssueBuff[i]]:
# found RAW in pre issue buff
issueMe = False
break
# see if there is a RAW in the preMEMbuff
for i in range(0, len(self.sim.preMEMbuff)):
if self.sim.preMEMbuff[i] != -1:
if self.sim.src1Reg[index] == self.sim.destReg[self.sim.preMEMbuff[i]] or self.sim.src2Reg[
index] == \
self.sim.destReg[self.sim.preMEMbuff[i]]:
# found RAW in pre issue buff
issueMe = False
break
# see if there is a RAW in the preALUbuff
for i in range(0, len(self.sim.preALUbuff)):
if self.sim.preALUbuff[i] != -1:
if self.sim.src1Reg[index] == self.sim.destReg[self.sim.preALUbuff[i]] or self.sim.src2Reg[
index] == \
self.sim.destReg[self.sim.preALUbuff[i]]:
# found RAW in pre issue buff
issueMe = False
break
# see if there is a RAW in the post buffs too
if self.sim.postALUbuff[1] != -1:
if self.sim.src1Reg[index] == self.sim.destReg[
self.sim.postALUbuff[1]] or self.sim.src2Reg[
index] == self.sim.destReg[
self.sim.postALUbuff[1]]:
# found RAW in post ALU buff
issueMe = False
if self.sim.postMEMbuff[1] != -1:
if self.sim.src1Reg[index] == self.sim.destReg[
self.sim.postMEMbuff[1]] or self.sim.src2Reg[
index] == self.sim.destReg[
self.sim.postALUbuff[1]]:
# found RAW in post MEM buff
issueMe = False
if issueMe:
numIssued += 1
# copy the instruction to the appropriate buffer
# the assumption here is that we will have a -1 in the right spot! Think we will.
if SetUp.isMemOp(index, self.sim.opcodeStr):
self.sim.preMEMbuff[self.sim.preMEMbuff.index(-1)] = index
else:
self.sim.preALUbuff[self.sim.preALUbuff.index(-1)] = index
# move the instr in the pre issue buff down one level
self.sim.preIssueBuff[0:curr] = self.sim.preIssueBuff[0:curr]
# print"pre" + str(self.preIssueBuff[curr+1])
self.sim.preIssueBuff[curr:3] = self.sim.preIssueBuff[
curr + 1:] # dropped 4, think will go to end always
self.sim.preIssueBuff[3] = -1
numInPreIssueBuff -= 1
curr += 1
def run(self):
instructions = []
instructions = SetUp.import_data_file()
outputFilename = SetUp.get_output_filename()
print("raw output filename is", outputFilename)
for i in range(len(instructions)):
self.address.append(96 + (i * 4))
opcode = []
for z in instructions:
opcode.append(int(z, base=2) >> 21)
for i in range(len(opcode)):
self.numInstructs = self.numInstructs + 1
if opcode[i] == 1112: #ADD
self.instrSpaced.append(SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ADD")
self.arg1.append((int(instructions[i], base=2) & self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2) & self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif opcode[i] == 1624: #SUB
self.instrSpaced.append(SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("SUB")
self.arg1.append((int(instructions[i], base=2) & self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2) & self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif opcode[i] == 1104: #AND
self.instrSpaced.append(SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("AND")
self.arg1.append((int(instructions[i], base=2) & self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2) & self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif opcode[i] == 1360: #ORR
self.instrSpaced.append(SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ORR")
self.arg1.append((int(instructions[i], base=2) & self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2) & self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif opcode[i] == 1690: #LSR
self.instrSpaced.append(SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSR")
self.arg1.append((int(instructions[i], base=2) & self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2) & self.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]) + ", ")
self.arg2Str.append("R" + str(self.arg1[i]) + ", ")
self.arg3Str.append("#" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif opcode[i] == 1691: #LSL
self.instrSpaced.append(SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSL")
self.arg1.append((int(instructions[i], base=2) & self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2) & self.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]) + ", ")
self.arg2Str.append("R" + str(self.arg1[i]) + ", ")
self.arg3Str.append("#" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif opcode[i] == 1872: #EOR
self.instrSpaced.append(SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("EOR")
self.arg1.append((int(instructions[i], base=2) & self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2) & self.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg1[i])
self.src2Reg.append(self.arg2[i])
elif 160 <= opcode[i] <= 191: #B
self.instrSpaced.append(SetUp.bin2StringSpacedB(instructions[i]))
self.opcodeStr.append("B")
self.arg1.append(SetUp.imm_bit_to_32_bit_converter((int(instructions[i], base=2) & self.bMask), 26))
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("#" + str(self.arg1[i]))
self.arg2Str.append("")
self.arg3Str.append("")
self.destReg.append(-2)
self.src1Reg.append(-3)
self.src2Reg.append(-4)
elif opcode[i] == 1160 or opcode[i] == 1161: #ADDI
self.instrSpaced.append(SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("ADDI")
self.arg1.append((int(instructions[i], base=2) & self.imMask) >> 10)
self.arg2.append((int(instructions[i], base=2) & self.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]) + "")
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg2[i])
self.src2Reg.append(-5)
elif opcode[i] == 1672 or opcode[i] == 1673: #SUBI
self.instrSpaced.append(SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("SUBI")
self.arg1.append((int(instructions[i], base=2) & self.imMask) >> 10)
self.arg2.append((int(instructions[i], base=2) & self.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]) + "")
self.destReg.append(self.arg3[i])
self.src1Reg.append(self.arg2[i])
self.src2Reg.append(-6)
elif 1440 <= opcode[i] <= 1447: #CBZ
self.instrSpaced.append(SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBZ")
self.arg1.append(SetUp.imm_bit_to_32_bit_converter(((int(instructions[i], base=2) & self.addr2Mask) >> 5), 19))
self.arg2.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg3.append('')
self.arg1Str.append("R" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
self.src1Reg.append(arg2[i])
self.src2Reg.append(-7)
self.destReg.append(-8)
elif 1448 <= opcode[i] <= 1455: #CBNZ
# CBNZ offsetArg, conditionArg
self.instrSpaced.append(SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBNZ")
self.arg1.append(SetUp.imm_bit_to_32_bit_converter(((int(instructions[i], base=2) & self.addr2Mask) >> 5), 19))
self.arg2.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg3.append('')
self.arg1Str.append("R" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
self.src1Reg.append(arg2[i])
self.src2Reg.append(-9)
self.destReg.append(-10)
elif 1684 <= opcode[i] <= 1687: #MOVZ
self.instrSpaced.append(SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVZ")
self.arg1.append((int(instructions[i], base=2) & self.imsftMask) >> 17)
self.arg2.append((int(instructions[i], base=2) & self.imdataMask) >> 5)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", " + str(self.arg2[i]))
self.arg3Str.append(", LSL " + str(self.arg1[i]))
self.destReg.append(arg3[i])
self.src1Reg.append(-11)
self.src2Reg.append(-12)
elif 1940 <= opcode[i] <= 1943: #MOVK
self.instrSpaced.append(SetUp.bin2StringSpacedIM(instructions[i]))
self.opcodeStr.append("MOVK")
self.arg1.append((int(instructions[i], base=2) & self.imsftMask) >> 17)
self.arg2.append((int(instructions[i], base=2) & self.imdataMask) >> 5)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", " + str(self.arg2[i]))
self.arg3Str.append(", LSL " + str(self.arg1[i]))
self.destReg.append(arg3[i])
self.src1Reg.append(-13)
self.src2Reg.append(-14)
elif opcode[i] == 1984: #STUR
self.instrSpaced.append(SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("STUR")
self.arg1.append((int(instructions[i], base=2) & self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2) & self.imMask) >> 12)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]) + ", ")
self.arg2Str.append("[R" + str(self.arg1[i]) + ", ")
self.arg3Str.append("#" + str(self.arg2[i]) + "]")
self.src1Reg.append(arg1[i])
self.src2Reg.append(-15)
self.destReg.append(arg3[i])
elif opcode[i] == 1986: #LDUR
self.instrSpaced.append(SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("LDUR")
self.arg1.append((int(instructions[i], base=2) & self.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2) & self.imMask) >> 12)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]) + ", ")
self.arg2Str.append("[R" + str(self.arg1[i]) + ", ")
self.arg3Str.append("#" + str(self.arg2[i]) + "]")
self.src1Reg.append(arg1[i])
self.src2Reg.append(-16)
self.destReg.append(arg3[i])
elif opcode[i] == 1692: #ASR
self.instrSpaced.append(SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ASR")
self.arg1.append((int(instructions[i], base=2) & self.shmtMask) >> 10)
self.arg2.append((int(instructions[i], base=2) & self.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2) & self.rdMask) >> 0)
self.arg1Str.append("R" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]))
self.src1Reg.append(arg2[i])
self.src2Reg.append(-17)
self.destReg.append(arg3[i])
elif opcode[i] == 0:
self.instrSpaced.append(SetUp.bin2StringSpaced(instructions[i]))
self.opcodeStr.append("NOP")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
self.src1Reg.append(-18)
self.src2Reg.append(-19)
self.destReg.append(-20)
elif opcode[i] == 2038 and (int(instructions[i], base=2) & self.specialMask) == 2031591:
self.instrSpaced.append(SetUp.bin2StringSpaced(instructions[i]))
self.opcodeStr.append("BREAK")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
self.src1Reg.append(-21)
self.src2Reg.append(-22)
self.destReg.append(-23)
print("breaking")
break
else:
self.opcodeStr.append("unknown")
self.arg2.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
self.src1Reg.append(-24)
self.src2Reg.append(-25)
self.destReg.append(-26)
print("i =: " + str(i))
print("opcode =: " + str(opcode[i]))
sys.exit("You have found an unknown instruction, investigate NOW")
# now read the memory lines
k = 0 #used to calculate how far from the B instruct
for i in range ((self.numInstructs), (len(instructions))):
#reads lines from break instruction to end of input file
self.rawdata.append(instructions[i]) #adds the binary to rawdata list
self.dataval.append(SetUp.imm_32_bit_unsigned_to_32_bit_signed_converter(int(instructions[i], base=2))) #converts to 2comp
self.addressdata.append(str(int(self.address[i])))
return {#"instructions": instructions,
"opcode":opcode,
"opcodeStr":self.opcodeStr,
"arg1":self.arg1,
"arg1Str":self.arg1Str,
"arg2":self.arg2,
"arg2Str":self.arg2Str,
"arg3":self.arg3,
"arg3Str":self.arg3Str,
"dataval":self.dataval,
"address":self.address,
"numInstructs":self.numInstructs,
"instructions":instructions,
"destReg":self.destReg,
"src1Reg":self.src1Reg,
"src2Reg":self.src2Reg}
def run(self):
instructions = []
instructions = SetUp.import_data_file()
# for i in instructions:
# print(i)
outputFilename = SetUp.get_output_filename()
print("raw output filename is ", outputFilename)
# print(hex(MASKs.bMask))
# print(bin(MASKs.bMask))
# print(f'{MASKs.bMask:032b}')
# create an address list with appropriate length
for i in range(len(instructions)):
self.address.append(96 + (i * 4))
opcode = []
# create an opcode list by selecting the left 11 bits
for z in instructions:
opcode.append(int(z, base=2) >> 21)
for i in range(len(opcode)):
self.numInstructs = self.numInstructs + 1
# REGISTER OPCODES
if opcode[i] == 1112:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ADD")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1624:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("SUB")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1690:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSR")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] == 1691:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("LSL")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] == 1692:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ASR")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.shmtMask) >> 10)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg2[i]))
elif opcode[i] == 1104:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("AND")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1360:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("ORR")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
elif opcode[i] == 1872:
self.instrSpaced.append(
SetUp.bin2StringSpacedR(instructions[i]))
self.opcodeStr.append("EOR")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rmMask) >> 16)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", R" + str(self.arg2[i]))
# IMMEDIATE OPCODES
elif opcode[i] == 1160 or opcode[i] == 1161:
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("ADDI")
self.arg1.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg3.append(
SetUp.imm_bit_to_32_bit_converter(
(int(instructions[i], base=2) & MASKs.imMask) >> 10,
12))
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", R" + str(self.arg1[i]))
self.arg3Str.append(", #" + str(self.arg3[i]))
elif opcode[i] == 1672 or opcode[i] == 1673:
self.instrSpaced.append(
SetUp.bin2StringSpacedI(instructions[i]))
self.opcodeStr.append("SUBI")
self.arg1.append((int(instructions[i], base=2) & MASKs.rdMask))
self.arg2.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKs.imMask) >> 10)
self.arg1Str.append("\tR" + str(self.arg1[i]))
self.arg2Str.append(", R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg3[i]))
# BRANCH OPCODES
elif 160 <= opcode[i] <= 191:
self.instrSpaced.append(
SetUp.bin2StringSpacedB(instructions[i]))
self.opcodeStr.append("B")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter(
(int(instructions[i], base=2) & MASKs.bMask), 26))
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("\t#" + str(self.arg1[i]))
self.arg2Str.append("")
self.arg3Str.append("")
# MEMORY OPCODES
elif opcode[i] == 1984:
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("STUR")
self.arg1.append((int(instructions[i], base=2)
& MASKs.addrMask) >> 12)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", [R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]) + "]")
elif opcode[i] == 1986:
self.instrSpaced.append(
SetUp.bin2StringSpacedD(instructions[i]))
self.opcodeStr.append("LDUR")
self.arg1.append((int(instructions[i], base=2)
& MASKs.addrMask) >> 12)
self.arg2.append((int(instructions[i], base=2)
& MASKs.rnMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", [R" + str(self.arg2[i]))
self.arg3Str.append(", #" + str(self.arg1[i]) + "]")
# CB INSTRUCTIONS
elif 1440 <= opcode[i] <= 1447:
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBZ")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter((
(int(instructions[i], base=2) & MASKs.addr2Mask) >> 5),
19))
self.arg2.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg3.append(0)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
elif 1448 <= opcode[i] <= 1455:
self.instrSpaced.append(
SetUp.bin2StringSpacedCB(instructions[i]))
self.opcodeStr.append("CBNZ")
self.arg1.append(
SetUp.imm_bit_to_32_bit_converter((
(int(instructions[i], base=2) & MASKs.addr2Mask) >> 5),
19))
self.arg2.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg3.append(0)
self.arg1Str.append("\tR" + str(self.arg2[i]))
self.arg2Str.append(", #" + str(self.arg1[i]))
self.arg3Str.append("")
# IM INSTRUCTIONS
elif 1684 <= opcode[i] <= 1687:
self.opcodeStr.append("MOVZ")
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.arg1.append((int(instructions[i], base=2)
& MASKs.imsftMask) >> 21)
self.arg2.append((int(instructions[i], base=2)
& MASKs.imdataMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", " + str(self.arg2[i]) + ", LSL ")
self.arg3Str.append(str(self.arg1[i] * 16))
elif 1940 <= opcode[i] <= 1943:
self.opcodeStr.append("MOVK")
self.instrSpaced.append(
SetUp.bin2StringSpacedIM(instructions[i]))
self.arg1.append((int(instructions[i], base=2)
& MASKs.imsftMask) >> 21)
self.arg2.append((int(instructions[i], base=2)
& MASKs.imdataMask) >> 5)
self.arg3.append((int(instructions[i], base=2)
& MASKs.rdMask) >> 0)
self.arg1Str.append("\tR" + str(self.arg3[i]))
self.arg2Str.append(", " + str(self.arg2[i]) + ", LSL ")
self.arg3Str.append(str(self.arg1[i] * 16))
# NOP INSTRUCTION
elif instructions[
i] == '00000000000000000000000000000000': # this might still be wrong need to test more
self.instrSpaced.append(SetUp.bin2StringSpaced(
instructions[i]))
self.opcodeStr.append("NOP")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
# Finding the BREAK instruction
elif opcode[i] == 2038 and (int(instructions[i], base=2)
& MASKs.specialMask) == 2031591:
self.instrSpaced.append(SetUp.bin2StringSpaced(
instructions[i]))
self.opcodeStr.append("BREAK")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
print("breaking")
break
else:
self.opcodeStr.append("unknown")
self.arg1.append(0)
self.arg2.append(0)
self.arg3.append(0)
self.arg1Str.append("")
self.arg2Str.append("")
self.arg3Str.append("")
print("i =: " + str(i))
print("opcode =: " + str(opcode[i]))
sys.exit(
"You have found an unknown instruction, investigate NOW")
# Now read the memory lines .... .... ....
for addri in range(self.numInstructs, len(opcode)):
self.rawdata.append(str(instructions[addri]))
self.dataval.append(
SetUp.imm_32_bit_unsigned_to_32_bit_signed_converter(
int(instructions[addri], base=2)))
return { #"instructions": instructions,
"opcode": opcode,
"opcodeStr": self.opcodeStr,
"arg1": self.arg1,
"arg1Str": self.arg1Str,
"arg2": self.arg2,
"arg2Str": self.arg2Str,
"arg3": self.arg3,
"arg3Str": self.arg3Str,
"dataval": self.dataval,
"address": self.address,
"numInstructs": self.numInstructs
}
