c.configureSi5338("RegisterMap.txt") # configure and lock PLL # (not needed for external clock) #h.setBiasPLL(12) # CP current #h.writeRegister(16,0x00b6) # C1 #h.writeRegister(17,0x0001) # C2 #h.setBitInRegister(18,6) # R1 bit 2 #h.clearBitInRegister(18,5) # R1 bit 1 #h.setBitInRegister(18,4) # R1 bit 0 #if (verbose): print "Locking PLL" #h.lockPLL() # external clock h.setBitInRegister(19,1) # power up all transmitter h.powerUpAllTXs() # set JESD testmode to Send /K/ h.setBitInRegister(27,0) # take HIPSTER out of reset h.setBitInRegister(27,7) # disable /K/ test mode h.clearBitInRegister(27,0) # enable ramp test patten h.setBitInRegister(27,5) if (verbose): print "Done"
# power down internal BGR #h.setBitInRegister(22,6) # configure SI5338 clock chip if (verbose): print "Configuring Si5338 Clock Chip" c.configureSi5338("RegisterMap_ADC.txt") # configure and lock PLL h.setBiasPLL(12) # CP current h.writeRegister(16,0x00b6) # C1 h.writeRegister(17,0x0001) # C2 h.setBitInRegister(18,6) # R1 bit 2 h.clearBitInRegister(18,5) # R1 bit 1 h.setBitInRegister(18,4) # R1 bit 0 if (verbose): print "Locking PLL" #h.lockPLL() # deassert out of reset # (need to figure out why we need to do this!) h.setBitInRegister(27,7) if (verbose): print "Configuring ADC" #configure SSO h.enableSSO() h.configureSSO(0)