def __init__(self, design, width='2x', length='1x'):
Component.__init__(self, design)
self.length = design.length(length)
assert self.length >= design.min_feat_size
self.width = design.width(width)
assert self.width >= design.min_gate_width
design.connect(self.body, design.vdd)
def __init__(self, design, length, layer="M1", segments=2):
Component.__init__(self, design)
self.length = length
self.layer = layer
self.segments = segments
self.coupled = []
self.resistance = design.__dict__[self.layer +
"ResPerM"] * length / segments
self.inductance = design.__dict__[self.layer +
"IndPerM"] * length / segments
self.groundcap = design.__dict__[self.layer +
"GndCapPerM"] * length / segments
self.couplecap = design.__dict__[self.layer +
"CoupCapPerM"] * length / segments
def __init__(self, design, fanout=4, vsrc=None,
invSize="1x", allowOdd=False):
self.design = design
self.vsrc = vsrc
self.invSize = invSize
self.fanout = fanout
self.allowOdd = allowOdd
self.input = Component.Terminal(self)
self.inverter_count = 0
def __init__(self,
design,
v2,
period,
duty_cycle=0.5,
td=0,
tr=0,
tf=0,
v1=0):
Component.__init__(self, design)
if v2 is None:
v2 = design.nominal_vdd
self.v2 = v2
self.period = period
self.pw = period * duty_cycle
self.td = td
self.tr = tr
self.tf = tf
self.v1 = v1
def __init__(self, vdd_voltage=None, process_library="45nm_HP"):
Circuit.__init__(self, None)
self.headers = set()
self.subckts = dict()
self.process_library = process_library
for (k, v) in LIBRARIES[process_library].items():
self.__dict__[k] = v
if vdd_voltage is None:
vdd_voltage = self.nominal_vdd
self.vss = Component.Terminal(self)
self.vpwr = Voltage(self, vdd_voltage)
self.name({self.vpwr: "vdd"})
self.vdd = self.vpwr.plus
self.allow_disconnect(self.vdd)
self.vdd.net.id = "vdd"
self.allow_disconnect(self.vss)
self.vss.net.id = "0"
self.init_conds = []
def __init__(self, design, resistance):
Component.__init__(self, design)
self.resistance = resistance
def __init__(self, design, vpairs):
Component.__init__(self, design)
vpairs = map(
lambda (t, v): (t, design.nominal_vdd if v is None else v), vpairs)
self.v_pairs = " ".join(map(lambda p: "%s %s" % p, vpairs))
def __init__(self, design, voltage):
Component.__init__(self, design)
if voltage is None:
voltage = design.nominal_vdd
self.voltage = voltage
design.connect(self.minus, design.vss)
def __init__(self, design, capacitance):
Component.__init__(self, design)
self.capacitance = capacitance