def test_endstrb(self):
u = self.u
_id = 0
# MAGIC = self._rand.getrandbits(16)
req = u.driver._ag.req
r = u.r._ag
ar = u.a._ag.data
rout = u.driver.r._ag.data
expected = []
for i in range(self.DATA_WIDTH // 8):
req.data.append(mkReq(i * (self.DATA_WIDTH // 8), 0, rem=i))
_len = 1
for i2 in range(_len):
isLast = int(i2 == _len - 1)
r.data.append((_id, i2 + 1, RESP_OKAY, isLast))
if not isLast or i == 0:
m = mask(self.DATA_WIDTH // 8)
else:
m = mask(i)
expected.append((_id, i2 + 1, m, isLast))
self.runSim((len(expected) * 2 * 10) * Time.ns)
self.assertEmpty(req.data)
_id = 0
_len = 0
self.assertValSequenceEqual(ar, [
self.mkDefaultAddrReq(_id, i * (self.DATA_WIDTH // 8), 0)
for i in range(self.DATA_WIDTH // 8)
])
self.assertValSequenceEqual(rout, expected)
def bitsArithOp__val(self, other, op):
v = self.clone()
self_vld = self._isFullVld()
other_vld = other._isFullVld()
v.val = op._evalFn(self.val, other.val)
w = v._dtype.bit_length()
if self._dtype.signed:
_v = v.val
_max = mask(w - 1)
_min = -_max - 1
if _v > _max:
_v = _min + (_v - _max - 1)
elif _v < _min:
_v = _max - (_v - _min + 1)
v.val = _v
else:
v.val &= mask(w)
if self_vld and other_vld:
v.vldMask = mask(w)
else:
v.vldMask = 0
v.updateTime = max(self.updateTime, other.updateTime)
return v
def test_pass(self):
u = self.u
u.a._ag.data.extend([(11, mask(u.a.strb._dtype.bit_length()), 1), NOP,
(12, mask(u.a.strb._dtype.bit_length()), 1)])
self.runSim(200 * Time.ns)
self.assertEqual(len(u.b._ag.data), 2)
def test_noLast(self):
u = self.u
u.dataIn._ag.data.append(
(it(16, 1, 2, 3, 4), it(2, mask(2), mask(2), mask(2), mask(2)), 0))
self.runSim(200 * Time.ns)
self.assertValSequenceEqual(u.dataOut._ag.data,
[(i + 1, mask(2), 0) for i in range(4)])
def test_onlyPartOfMask(self):
u = self.u
u.dataIn._ag.data.append((it(16, 1, 2, 3, 4), it(2, mask(2), 0, 0,
0), 1))
self.runSim(200 * Time.ns)
self.assertValSequenceEqual(u.dataOut._ag.data, [
(1, mask(2), 1),
])
def remSizeToStrb(self, remSize, strb):
strbBytes = 2**self.getSizeAlignBits()
return Switch(remSize)\
.Case(0,
strb(mask(strbBytes))
).addCases(
[(i + 1, strb(mask(i + 1)))
for i in range(strbBytes - 1)]
)
def remSizeToStrb(self, remSize, strb):
strbBytes = 2 ** self.getSizeAlignBits()
return Switch(remSize)\
.Case(0,
strb(mask(strbBytes))
).addCases(
[(i + 1, strb(mask(i + 1)))
for i in range(strbBytes - 1)]
)
def test_withLast(self):
u = self.u
u.dataIn._ag.data.append((it(16, 1, 2, 3, 4),
it(2, mask(2), mask(2), mask(2), mask(2)),
1))
self.runSim(200 * Time.ns)
self.assertValSequenceEqual(u.dataOut._ag.data,
[(i + 1, mask(2), i == 3) for i in range(4)])
def test_simple(self):
u = self.u
# (data, strb, user, last)
d = [(13, mask(8), 0b01, 0), (14, mask(1), 0b10, 1)]
u.dataIn._ag.data.extend(d)
self.runSim(200 * Time.ns)
self.assertValSequenceEqual(u.dataOut._ag.data, d)
def test_pass(self):
u = self.u
u.a._ag.data.extend([(11, mask(u.a.strb._dtype.bit_length()), 1),
NOP,
(12, mask(u.a.strb._dtype.bit_length()), 1)
])
self.runSim(200 * Time.ns)
self.assertEqual(len(u.b._ag.data), 2)
def test_singleWordPacket(self):
u = self.u
u.dataIn._ag.data.extend([
(2, mask(8), 1),
])
self.runSim(200 * Time.ns)
self.assertValSequenceEqual(u.sizes._ag.data, [8, ])
self.assertValSequenceEqual(u.dataOut._ag.data, [(2, mask(8), 1), ])
def generateRequests(self, baseAddress, spaceValues):
"""
generate reference requests and data
data words are containing it's indexes, baseAddresses are multiplies baseAddress
:param spaceValues: is iterable of space values
"""
requests = []
responses = []
wordCntr = 0
inBlockRem = self.ITEMS_IN_BLOCK
_baseAddress = baseAddress
for space in spaceValues:
while space != 0:
constraingSpace = min(inBlockRem, space)
reqId = self.ID
if constraingSpace > self.MAX_LEN + 1:
reqLen = self.MAX_LEN
elif inBlockRem == 0:
reqLen = 0
reqId = self.ID_LAST
else:
if constraingSpace <= self.MAX_LEN + 1 and inBlockRem < self.MAX_LEN + 1:
# we will download next* as well
reqLen = constraingSpace
reqId = self.ID_LAST
else:
# if constraingSpace == inBlockRem:
# reqId = self.ID_LAST
# reqLen = constraingSpace
# else:
reqLen = constraingSpace - 1
inBlockIndex = self.ITEMS_IN_BLOCK - inBlockRem
req = (reqId, _baseAddress + inBlockIndex * 8, reqLen, 0)
requests.append(req)
for i in range(reqLen + 1):
if i == reqLen and reqId == self.ID_LAST:
r = (reqId, baseAddress, mask(8), True)
_baseAddress += baseAddress
else:
r = (reqId, wordCntr + i, mask(8), i == reqLen)
responses.append(r)
if reqId == self.ID_LAST:
inBlockRem = self.ITEMS_IN_BLOCK
wordCntr += reqLen
space -= reqLen
else:
inBlockRem -= reqLen + 1
wordCntr += reqLen + 1
space -= reqLen + 1
return requests, responses
def _impl(self):
propagateClkRstn(self)
dIn = AxiSBuilder(self, self.dataIn).buff().end
sb = self.sizesBuff
db = self.dataBuff
wordCntr = self._reg("wordCntr",
Bits(log2ceil(self.MAX_LEN) + 1),
defVal=0)
overflow = wordCntr._eq(self.MAX_LEN)
last = dIn.last | overflow
If(
StreamNode(masters=[dIn], slaves=[sb.dataIn, db.dataIn]).ack(),
If(last, wordCntr(0)).Else(wordCntr(wordCntr + 1)))
length = self._sig("length", wordCntr._dtype)
BYTE_CNT = dIn.data._dtype.bit_length() // 8
if dIn.USE_STRB:
# compress strb mask as binary number
rem = self._sig("rem", Bits(log2ceil(BYTE_CNT)))
SwitchLogic(cases=[(dIn.strb[i],
rem(0 if i == BYTE_CNT - 1 else i + 1))
for i in reversed(range(BYTE_CNT))],
default=[
rem(0),
])
if self.EXPORT_ALIGNMENT_ERROR:
errorAlignment = self._reg("errorAlignment_reg", defVal=0)
self.errorAlignment(errorAlignment)
If(dIn.valid & (dIn.strb != mask(BYTE_CNT)) & ~dIn.last,
errorAlignment(1))
If(last & (dIn.strb != mask(BYTE_CNT)),
length(wordCntr)).Else(length(wordCntr + 1))
else:
length(wordCntr + 1)
rem = vec(0, log2ceil(BYTE_CNT))
sb.dataIn.data(Concat(length, rem))
connect(dIn, db.dataIn, exclude=[dIn.valid, dIn.ready, dIn.last])
db.dataIn.last(last)
StreamNode(masters=[dIn],
slaves=[sb.dataIn, db.dataIn],
extraConds={
sb.dataIn: last
}).sync()
self.sizes(sb.dataOut)
connect(db.dataOut, self.dataOut)
def test_8b_cast(self, t=int8_t):
w = t.bit_length()
ut = Bits(w)
self.assertEqual(int(t.fromPy(-1)._auto_cast(ut)), mask(w))
self.assertEqual(int(t.fromPy(-1)._unsigned()), mask(w))
self.assertEqual(int(t.fromPy(-1)._vec()), mask(w))
self.assertEqual(int(t.fromPy(1)._auto_cast(ut)), 1)
self.assertEqual(int(t.fromPy(0)._auto_cast(ut)), 0)
self.assertEqual(int(ut.fromPy(1)._auto_cast(t)), 1)
self.assertEqual(int(ut.fromPy(mask(w))._auto_cast(t)), -1)
self.assertEqual(int(ut.fromPy(mask(w))._signed()), -1)
def test_8b_cast(self, t=int8_t):
w = t.bit_length()
ut = Bits(w)
self.assertEqual(int(t.fromPy(-1)._auto_cast(ut)), mask(w))
self.assertEqual(int(t.fromPy(-1)._unsigned()), mask(w))
self.assertEqual(int(t.fromPy(-1)._vec()), mask(w))
self.assertEqual(int(t.fromPy(1)._auto_cast(ut)), 1)
self.assertEqual(int(t.fromPy(0)._auto_cast(ut)), 0)
self.assertEqual(int(ut.fromPy(1)._auto_cast(t)), 1)
self.assertEqual(int(ut.fromPy(mask(w))._auto_cast(t)), -1)
self.assertEqual(int(ut.fromPy(mask(w))._signed()), -1)
def test_onlyPartOfMask(self):
u = self.u
u.dataIn._ag.data.append((
it(16, 1, 2, 3, 4),
it(2, mask(2), 0, 0, 0),
1)
)
self.runSim(200 * Time.ns)
self.assertValSequenceEqual(u.dataOut._ag.data,
[(1, mask(2), 1),
])
def test_crc32(self):
for i, inp in enumerate([b"abcd", b"0001"]):
u = self.setUpCrc(CRC_32,
refin=True,
refout=True,
initval=mask(32),
finxor=mask(32))
u.dataIn._ag.data.append(stoi(inp), )
self.runSim(20 * Time.ns, name="tmp/test_crc32_%i.vcd" % i)
out = int(u.dataOut._ag.data[-1])
ref = crc32(inp) & 0xffffffff
self.assertEqual(out, ref, "0x{:08X} 0x{:08X}".format(out, ref))
def test_crc32_64b(self):
inp = "abcdefgh"
u = self.setUpCrc(CRC_32,
dataWidth=64,
refin=True,
refout=True,
initval=mask(32),
finxor=mask(32))
u.dataIn._ag.data.append(stoi(inp))
self.runSim(20 * Time.ns)
out = int(u.dataOut._ag.data[-1])
ref = crc32(inp.encode()) & 0xffffffff
self.assertEqual(out, ref, "0x{:08X} 0x{:08X}".format(out, ref))
def test_doubleWordPacket(self):
u = self.u
sizes = u.sizes._ag.data
data = u.dataOut._ag.data
goldenData = [(1, mask(8), 0),
(2, mask(8), 1)
]
u.dataIn._ag.data.extend(goldenData)
self.runSim(200 * Time.ns)
self.assertValSequenceEqual(data, goldenData)
self.assertValSequenceEqual(sizes, (16,))
def test_8b_mul(self, t=int8_t):
w = t.bit_length()
low, up, _, _ = self.getMinMaxVal(t)
ut = Bits(w)
self.assertEqual(int(t.fromPy(-1) * t.fromPy(-1)), 1)
self.assertEqual(int(t.fromPy(0) * t.fromPy(-1)), 0)
self.assertEqual(int(ut.fromPy(0) * ut.fromPy(1)), 0)
self.assertEqual(int(ut.fromPy(mask(w)) * ut.fromPy(2)), (mask(w) << 1) & mask(w))
self.assertEqual(int(t.fromPy(-1) * ut.fromPy(2)), -2)
self.assertEqual(low * t.fromPy(2), 0)
self.assertEqual(up * t.fromPy(2), -2)
m = up * t.fromPy(None)
self.assertEqual(valToInt(m), None)
def test_multiplePackets(self):
u = self.u
sizes = u.sizes._ag.data
data = u.dataOut._ag.data
goldenData = [(1, mask(8), 1),
(2, mask(8), 1),
(3, mask(8), 1)
]
u.dataIn._ag.data.extend(goldenData)
self.runSim(200 * Time.ns)
self.assertValSequenceEqual(data, goldenData)
self.assertValSequenceEqual(sizes, [8, 8, 8])
def mySetUp(self, read_latency=0, write_latency=0):
SimTestCase.setUp(self)
RW = ACCESS_RW
AUTO = AUTO_ADDR
u = IpifInterconnectMatrix(
masters=[(0x0, RW)],
slaves=[
(0x0000, 0x0100, RW),
(0x0100, 0x0100, RW),
(AUTO, 0x0100, RW),
(AUTO, 0x1000, RW),
]
)
self.DW = 32
self.wordSize = self.DW // 8
u.DATA_WIDTH.set(self.DW)
u.ADDR_WIDTH.set(u.getOptimalAddrSize())
self.m = mask(self.wordSize)
self.u = u
self.prepareUnit(u)
for s in u.m:
s._ag.READ_LATENCY = read_latency
s._ag.WRITE_LATENCY = write_latency
def test_randomized2(self):
u = self.u
m = DenseMemory(self.DATA_WIDTH, u.clk, u.rDatapump)
N = 17
for d in u.drivers:
self.randomize(d.req)
self.randomize(d.r)
self.randomize(u.rDatapump.req)
self.randomize(u.rDatapump.r)
_mask = mask(self.DATA_WIDTH // 8)
expected = [[] for _ in u.drivers]
for _id, d in enumerate(u.drivers):
for i in range(N):
size = self._rand.getrandbits(3) + 1
magic = self._rand.getrandbits(16)
values = [i + magic for i in range(size)]
addr = m.calloc(size, 8, initValues=values)
d.req._ag.data.append((_id, addr, size - 1, 0))
for i2, v in enumerate(values):
data = (_id, v, _mask, int(i2 == size - 1))
expected[_id].append(data)
self.runSim(self.DRIVERS_CNT * N * 200 * Time.ns)
for expect, driver in zip(expected, u.drivers):
self.assertValSequenceEqual(driver.r._ag.data, expect)
def instantiateFrameForge(self, structT,
DATA_WIDTH=64,
maxFrameLen=inf,
maxPaddingWords=inf,
trimPaddingWordsOnStart=False,
trimPaddingWordsOnEnd=False,
randomized=True):
tmpl = TransTmpl(structT)
frames = list(FrameTmpl.framesFromTransTmpl(
tmpl,
DATA_WIDTH,
maxFrameLen=maxFrameLen,
maxPaddingWords=maxPaddingWords,
trimPaddingWordsOnStart=trimPaddingWordsOnStart,
trimPaddingWordsOnEnd=trimPaddingWordsOnEnd))
u = self.u = AxiS_frameForge(structT,
tmpl, frames)
self.DATA_WIDTH = DATA_WIDTH
self.m = mask(self.DATA_WIDTH // 8)
u.DATA_WIDTH.set(self.DATA_WIDTH)
self.prepareUnit(self.u)
if randomized:
self.randomize(u.dataOut)
for intf in u.dataIn._fieldsToInterfaces.values():
self.randomize(intf)
def _impl(self):
propagateClkRstn(self)
cntr = self._reg("wordCntr", Bits(log2ceil(self.MAX_LEN)), defVal=0)
en = self._reg("enable", defVal=0)
_len = self._reg("wordCntr", Bits(log2ceil(self.MAX_LEN)), defVal=0)
self.conv.bus(self.cntrl)
cEn = self.conv.decoded.enable
If(cEn.dout.vld, connect(cEn.dout.data, en, fit=True))
connect(en, cEn.din, fit=True)
cLen = self.conv.decoded.len
If(cLen.dout.vld, connect(cLen.dout.data, _len, fit=True))
connect(_len, cLen.din, fit=True)
out = self.axis_out
connect(cntr, out.data, fit=True)
if self.USE_STRB:
out.strb(mask(self.axis_out.strb._dtype.bit_length()))
out.last(cntr._eq(0))
out.valid(en)
If(cLen.dout.vld, connect(cLen.dout.data, cntr, fit=True)).Else(
If(out.ready & en,
If(cntr._eq(0), cntr(_len)).Else(cntr(cntr - 1))))
def test_write(self):
u = self.mySetUp(32)
MAGIC = 100
MAGIC2 = 300
m = mask(32 // 8)
N = 4
a = self.aTrans
u.bus.aw._ag.data.extend([a(i * 0x4) for i in range(N * 2 + 1)])
expected = [
[(MAGIC + i + 1, m) for i in range(N)],
[(MAGIC2 + i + 1, m) for i in range(N)]
]
u.bus.w._ag.data.extend(flatten(zip(expected[0], expected[1]), level=1))
u.bus.w._ag.data.append((123, m))
self.randomizeAll()
self.runSim(800 * Time.ns)
for i, a in enumerate(u.decoded.arr):
# [index of field][index in arr][data index]
self.assertValSequenceEqual(a.field0._ag.dout, [expected[0][i][0]])
self.assertValSequenceEqual(a.field1._ag.dout, [expected[1][i][0]])
self.assertValSequenceEqual(u.bus.b._ag.data,
[RESP_OKAY for _ in range(2 * N)] + [RESP_SLVERR])
def doWrite(self, s, data):
w = s.write
intf = self.intf
if data is None:
w(None, intf.address)
w(None, intf.byteEnable)
# w(None, intf.burstCount)
w(0, intf.read)
w(0, intf.write)
else:
rw, address, burstCount = data
if rw is READ:
rd, wr = 1, 0
be = mask(intf.readData._dtype.bit_length() // 8)
elif rw is WRITE:
rd, wr = 0, 1
rw, address, burstCount = data
d, be = self.wData.popleft()
w(d, intf.writeData)
else:
raise TypeError("rw is in invalid format %r" % (rw,))
w(address, intf.address)
w(be, intf.byteEnable)
assert int(burstCount) >= 1, burstCount
# w(burstCount, intf.burstCount)
w(rd, intf.read)
w(wr, intf.write)
def test_write(self):
u = self.mySetUp(32)
MAGIC = 100
m = mask(32 // 8)
A = self.FIELD_ADDR
u.bus._ag.req.extend(
map(self.awTrans,
[A[0],
A[1],
A[0],
A[1],
A[1] + 0x4]))
u.bus._ag.wData.extend(
[(MAGIC, m),
(MAGIC + 1, m),
(MAGIC + 2, m),
(MAGIC + 3, m),
(MAGIC + 4, m)])
self.randomizeAll()
self.runSim(50 * self.CLK)
self.assertValSequenceEqual(
u.decoded.field0._ag.dout,
[MAGIC,
MAGIC + 2
])
self.assertValSequenceEqual(
u.decoded.field1._ag.dout,
[MAGIC + 1,
MAGIC + 3
])
self.assertValSequenceEqual(
u.bus._ag.wResp,
[RESP_OKAY for _ in range(4)] + [RESP_SLAVEERROR])
def test_maxNotSplitedReqWithData(self):
u = self.u
LEN_MAX = self.LEN_MAX
req = u.driver.req._ag
r = u.r._ag
rout = u.driver.r._ag.data
# download 256 words from addr 0xff
req.data.append(mkReq(0xff, LEN_MAX))
for i in range(LEN_MAX + 1):
addData(r, i + 77, last=(i == LEN_MAX))
# dummy data
addData(r, 11)
addData(r, 12)
self.runSim(((LEN_MAX + 6) * 10) * Time.ns)
self.assertEmpty(req.data)
self.assertEqual(len(u.a._ag.data), 1)
# self.assertEqual(valuesToInts(u.driver._ag.r.data[0]),
# [77, mask(64 // 8), 0, 1])
self.assertEqual(len(r.data), 2 - 1) # no more data was taken
self.assertValSequenceEqual(rout,
[(0, 77 + i, mask(64 // 8),
int(i == LEN_MAX))
for i in range(LEN_MAX + 1)])
self.assertEqual(len(r.data), 2 - 1) # 2. is now sended
def test_maxNotSplitedReqWithData(self):
u = self.u
LEN_MAX = self.LEN_MAX
req = u.driver.req._ag
r = u.r._ag
rout = u.driver.r._ag.data
# download 256 words from addr 0xff
req.data.append(mkReq(0xff, LEN_MAX))
for i in range(LEN_MAX + 1):
addData(r, i + 77, last=(i == LEN_MAX))
# dummy data
addData(r, 11)
addData(r, 12)
self.runSim(((LEN_MAX + 6) * 10) * Time.ns)
self.assertEmpty(req.data)
self.assertEqual(len(u.a._ag.data), 1)
# self.assertEqual(valuesToInts(u.driver._ag.r.data[0]),
# [77, mask(64 // 8), 0, 1])
self.assertEqual(len(r.data), 2 - 1) # no more data was taken
self.assertValSequenceEqual(
rout, [(0, 77 + i, mask(64 // 8), int(i == LEN_MAX))
for i in range(LEN_MAX + 1)])
self.assertEqual(len(r.data), 2 - 1) # 2. is now sended
def __init__(self, intf, allowNoReset=False):
AgentBase.__init__(self, intf)
self.txData = deque()
self.rxData = deque()
self.chipSelects = deque()
self._txBitBuff = deque()
self._rxBitBuff = deque()
self.csMask = mask(intf.cs._dtype.bit_length())
self.slaveEn = False
# resolve clk and rstn
self.clk = self.intf._getAssociatedClk()._sigInside
self._discoverReset(allowNoReset=allowNoReset)
# read on rising edge write on falling
self.monitorRx = OnRisingCallbackLoop(self.clk,
self.monitorRx,
self.getEnable)
self.monitorTx = OnFallingCallbackLoop(self.clk,
self.monitorTx,
self.getEnable)
self.driverRx = OnFallingCallbackLoop(self.clk,
self.driverRx,
self.getEnable)
self.driverTx = OnRisingCallbackLoop(self.clk,
self.driverTx,
self.getEnable)
def test_3Fields_outOccupiedAtStart(self):
u = self.u = AxiS_frameForge(s3field)
self.DATA_WIDTH = 64
u.DATA_WIDTH.set(self.DATA_WIDTH)
m = mask(self.DATA_WIDTH // 8)
self.prepareUnit(self.u)
def enDataOut(s):
u.dataOut._ag.enable = False
yield s.wait(50 * Time.ns)
u.dataOut._ag.enable = True
self.procs.append(enDataOut)
MAGIC = 468
u.dataIn.item0._ag.data.append(MAGIC)
u.dataIn.item1._ag.data.append(MAGIC + 1)
u.dataIn.item2._ag.data.append(MAGIC + 2)
t = 200
self.runSim(t * Time.ns)
self.assertValSequenceEqual(u.dataOut._ag.data,
[(MAGIC, m, 0),
(MAGIC + 1, m, 0),
(MAGIC + 2, m, 1),
])
def test_s2Pading_normal(self):
u = self.u = AxiS_frameForge(s2Pading)
self.DATA_WIDTH = 64
u.DATA_WIDTH.set(self.DATA_WIDTH)
m = mask(self.DATA_WIDTH // 8)
self.prepareUnit(self.u)
def enDataOut(s):
u.dataOut._ag.enable = False
yield s.wait(50 * Time.ns)
u.dataOut._ag.enable = True
self.procs.append(enDataOut)
MAGIC = 468
u.dataIn.item0_0._ag.data.append(MAGIC)
u.dataIn.item0_1._ag.data.append(MAGIC + 1)
u.dataIn.item1_0._ag.data.append(MAGIC + 2)
u.dataIn.item1_1._ag.data.append(MAGIC + 3)
t = 200
self.runSim(t * Time.ns)
self.assertValSequenceEqual(u.dataOut._ag.data,
[(MAGIC, m, 0),
(MAGIC + 1, m, 0),
(None, m, 0),
(MAGIC + 2, m, 0),
(MAGIC + 3, m, 0),
(None, m, 1),
])
def test_tailHeadPrincipe(self):
BITS = 16
MASK = mask(BITS)
tail = 0
head = 0
def normalize(n):
if n < 0:
return MASK + n
elif n > MASK:
return n - MASK
else:
return n
def size():
return normalize(head - tail)
self.assertEqual(size(), 0)
head = MASK
self.assertEqual(size(), MASK)
tail = 10
self.assertEqual(size(), MASK - 10)
head = normalize(head + 5)
self.assertEqual(size(), MASK - 5)
def test_noPass(self):
u = self.u
u.dataIn._ag.data.extend([(1, mask(2), 0) for _ in range(2)])
self.runSim(200 * Time.ns)
self.assertEmpty(u.dataOut._ag.data)
def convertBits(self, sigOrVal, toType):
isVal = isinstance(sigOrVal, Value)
if isinstance(toType, Boolean):
if isVal:
return sigOrVal._eq(self.getValueCls().fromPy(1, self))
elif self.bit_length() == 1:
v = 0 if sigOrVal.negated else 1
return sigOrVal._eq(self.getValueCls().fromPy(v, self))
elif isinstance(toType, Bits):
if self.bit_length() == toType.bit_length():
return sigOrVal._convSign(toType.signed)
elif toType == INT:
if isVal:
if self.signed:
raise NotImplementedError()
else:
fullMask = mask(self.bit_length())
return INT.getValueCls()(sigOrVal.val, INT,
sigOrVal.vldMask == fullMask,
sigOrVal.updateTime)
else:
return Operator.withRes(AllOps.BitsToInt, [sigOrVal], toType)
return HdlType.defaultConvert(self, sigOrVal, toType)
def test_randomized10(self):
u = self.u
sizes = u.sizes._ag.data
data = u.dataOut._ag.data
N = 10
expectedData = []
expectedLen = []
for i in range(N):
_l = int(self._rand.random() * (self.MAX_LEN + 1 + 1))
d = [(i + 1, mask(8), int(i == (_l - 1))) for i in range(_l)]
u.dataIn._ag.data.extend(d)
expectedData.extend(d)
expectedLen.append(_l * 8)
self.randomize(u.dataIn)
self.randomize(u.dataOut)
self.randomize(u.sizes)
self.runSim(len(expectedData) * 30 * Time.ns)
self.assertEqual(len(sizes), N)
self.assertEqual(len(data), len(expectedData))
for exp, d in zip(expectedData, data):
self.assertValSequenceEqual(d, exp)
for el, l in zip(expectedLen, sizes):
self.assertValEqual(l, el)
def test_passData(self):
u = self.u
expectedW = []
for i, driver in enumerate(u.drivers):
_id = i + 1
_len = i + 1
driver.req._ag.data.append((_id, i + 1, _len, 0))
strb = mask(self.DATA_WIDTH // 8)
for i2 in range(_len + 1):
_data = i + i2 + 1
last = int(i2 == _len)
d = (_data, strb, last)
driver.w._ag.data.append(d)
expectedW.append(d)
self.runSim(80 * Time.ns)
req = u.wDatapump.req._ag.data
wData = u.wDatapump.w._ag.data
for i, _req in enumerate(req):
self.assertValSequenceEqual(_req,
(i + 1, i + 1, i + 1, 0))
self.assertEqual(len(req), self.DRIVER_CNT)
for w, expW in zip(wData, expectedW):
self.assertValSequenceEqual(w, expW)
def _impl(self):
self.DATA_WIDTH = int(self.DATA_WIDTH)
vldAll = mask(self.DATA_WIDTH // 8)
dout = self.dataOut
DATA_LEN = len(self.DATA)
wordIndex_w = int(math.log2(DATA_LEN) + 1)
wordIndex = self._reg("wordIndex", Bits(wordIndex_w), defVal=0)
Switch(wordIndex)\
.addCases([(i, dout.data(d))
for i, d in enumerate(self.DATA)])\
.Default(dout.data(None))
dout.last(wordIndex._eq(DATA_LEN - 1))
If(wordIndex < DATA_LEN,
dout.strb(vldAll),
dout.valid(1)
).Else(
dout.strb(None),
dout.valid(0)
)
If(self.dataRd(),
self.nextWordIndexLogic(wordIndex)
)
def test_multiple_randomized(self):
u = self.u
req = u.driver._ag.req
aw = u.a._ag.data
wIn = u.driver.w._ag
w = u.w._ag.data
b = u.b._ag.data
N = 50
# download one word from addr 0xff
for i in range(N):
req.data.append(mkReq((i * 8) + 0xff, 0))
wIn.data.append((77, mask(64 // 8 - 1), 1))
b.append((0, RESP_OKAY))
ra = self.randomize
ra(u.a)
ra(u.b)
ra(u.driver.req)
ra(u.driver.ack)
ra(u.w)
ra(u.driver.w)
self.runSim(N * 8 * 10 * Time.ns)
self.assertValSequenceEqual(aw, [
self.aTrans(id_=0, addr=0xff + (8 * i), len_=0) for i in range(N)
])
self.assertEqual(len(w), N)
self.assertEmpty(b)
self.assertEqual(len(u.driver._ag.ack.data), N)
def test_8b_mul(self, t=int8_t):
w = t.bit_length()
low, up, _, _ = self.getMinMaxVal(t)
ut = Bits(w)
self.assertEqual(int(t.fromPy(-1) * t.fromPy(-1)), 1)
self.assertEqual(int(t.fromPy(0) * t.fromPy(-1)), 0)
self.assertEqual(int(ut.fromPy(0) * ut.fromPy(1)), 0)
self.assertEqual(int(ut.fromPy(mask(w)) * ut.fromPy(2)),
(mask(w) << 1) & mask(w))
self.assertEqual(int(t.fromPy(-1) * ut.fromPy(2)), -2)
self.assertEqual(low * t.fromPy(2), 0)
self.assertEqual(up * t.fromPy(2), -2)
m = up * t.fromPy(None)
self.assertEqual(valToInt(m), None)
def test_noPass(self):
u = self.u
u.dataIn._ag.data.extend([(1, mask(2), 0) for _ in range(2)])
self.runSim(200 * Time.ns)
self.assertEmpty(u.dataOut._ag.data)
def fromPy(cls, val, typeObj):
if not isinstance(val, (int, bool)) and val is not None:
raise TypeError(val, type(val))
vld = 0 if val is None else mask(typeObj.bit_length())
if not vld:
val = 0
return cls(int(val), typeObj, vld)
def prepareRequest(_id, addr, data):
req.data.append(mkReq(addr, len(data) - 1, _id=_id))
expected = [
(_id, d, mask(8), i == len(data) - 1)
for i, d in enumerate(data)
]
return expected
def test_singleLong(self):
u = self.u
req = u.driver._ag.req
aw = u.a._ag.data
wIn = u.driver.w._ag
w = u.w._ag.data
b = u.b._ag.data
# download one word from addr 0xff
req.data.append(mkReq(0xff, self.LEN_MAX))
for i in range(self.LEN_MAX + 1 + 10):
wIn.data.append((100 + 1, mask(8), i == self.LEN_MAX))
b.append((0, RESP_OKAY))
self.runSim((10 + self.LEN_MAX) * 10 * Time.ns)
self.assertValSequenceEqual(aw,
[
self.aTrans(
id_=0, addr=0xff, len_=self.LEN_MAX)
])
self.assertEqual(len(w), self.LEN_MAX + 1)
self.assertEmpty(b)
self.assertEqual(len(u.driver._ag.ack.data), 1)
def test_multiple_randomized(self):
u = self.u
req = u.driver._ag.req
aw = u.a._ag.data
wIn = u.driver.w._ag
w = u.w._ag.data
b = u.b._ag.data
N = 50
# download one word from addr 0xff
for i in range(N):
req.data.append(mkReq((i * 8) + 0xff, 0))
wIn.data.append((77, mask(64 // 8 - 1), 1))
b.append((0, RESP_OKAY))
ra = self.randomize
ra(u.a)
ra(u.b)
ra(u.driver.req)
ra(u.driver.ack)
ra(u.w)
ra(u.driver.w)
self.runSim(N * 8 * 10 * Time.ns)
self.assertValSequenceEqual(aw,
[
self.aTrans(
id_=0, addr=0xff + (8 * i), len_=0)
for i in range(N)
])
self.assertEqual(len(w), N)
self.assertEmpty(b)
self.assertEqual(len(u.driver._ag.ack.data), N)
def reshapedInitItems(actualCellSize, requestedCellSize, values):
"""
Convert array item size and items cnt while size of array remains unchanged
:param actualCellSize: actual size of item in array
:param requestedCellSize: requested size of item in array
:param values: input array
:return: generator of new items of specified characteristik
"""
if actualCellSize < requestedCellSize and requestedCellSize % actualCellSize == 0:
itemsInCell = requestedCellSize // actualCellSize
itemAlign = len(values) % itemsInCell
if itemAlign != 0:
values = chain(values, [0 for _ in range(itemsInCell - itemAlign)])
for itemsInWord in zip(*[iter(values)] * itemsInCell):
item = 0
for iIndx, i2 in enumerate(itemsInWord):
subIndx = itemsInCell - iIndx - 1
_i2 = (mask(actualCellSize * 8) & i2) << (subIndx *
actualCellSize * 8)
item |= _i2
yield item
else:
raise NotImplementedError(
"Reshaping of array from cell size %d to %d" %
(actualCellSize, requestedCellSize))
def dataHandler(self, rmSizeOut):
r = self.r
rOut = self.driver.r
rErrFlag = self._reg("rErrFlag", defVal=0)
If(r.valid & rOut.ready & (r.resp != RESP_OKAY),
rErrFlag(1)
)
self.errorRead(rErrFlag)
rOut.id(r.id)
rOut.data(r.data)
If(r.valid & r.last & rmSizeOut.propagateLast,
self.remSizeToStrb(rmSizeOut.rem, rOut.strb)
).Else(
rOut.strb(mask(2 ** self.getSizeAlignBits()))
)
rOut.last(r.last & rmSizeOut.propagateLast)
StreamNode(masters=[r, rmSizeOut],
slaves=[rOut],
extraConds={rmSizeOut: r.last,
rOut: ~rErrFlag}).sync()
return rErrFlag
def _impl(self):
assert(int(self.USER_WIDTH) == 2) # this is how is protocol specified
In = self.dataIn
Out = self.dataOut
propagateClkRstn(self)
lastSeenLast = self._reg("lastSeenLast", defVal=1)
sof = lastSeenLast
Out.data(In.data)
Out.src_rdy_n(~In.valid)
outRd = ~Out.dst_rdy_n
If(In.valid & outRd,
lastSeenLast(In.last)
)
In.ready(outRd)
Out.eof_n(~In.last)
# AXI_USER(0) -> FL_SOP_N
# Always set FL_SOP_N when FL_SOF_N - added for compatibility with xilinx
# axi components. Otherwise FL_SOP_N would never been set and LocalLink
# protocol would be broken.
sop = In.user[0]
If(sof,
Out.sop_n(0)
).Else(
Out.sop_n( ~sop)
)
# AXI_USER(1) -> FL_EOP_N
# Always set FL_EOP_N when FL_EOF_N - added for compatibility with xilinx
# axi components. Otherwise FL_EOP_N would never been set and LocalLink
# protocol would be broken.
eop = In.user[1]
If(In.last,
Out.eop_n(0)
).Else(
Out.eop_n(~eop)
)
remMap = []
remBits = Out.rem._dtype.bit_length()
strbBits = In.strb._dtype.bit_length()
for strb, rem in strbToRem(strbBits, remBits):
remMap.append((strb, Out.rem(rem)))
end_of_part_or_transaction = In.last | eop
If(end_of_part_or_transaction,
Switch(In.strb)\
.addCases(remMap)
).Else(
Out.rem(mask(remBits))
)
Out.sof_n(~sof)
