def _m(self):
"""
Note that this interface will be master
:return: self
"""
assert not hasattr(self, "_interfaces") or not self._interfaces, \
"Too late to change direction of interface"
self._direction = DIRECTION.asIntfDirection(DIRECTION.opposite(self._masterDir))
return self
def _setDirectionsLikeIn(self, intfDir):
assert intfDir in [INTF_DIRECTION.MASTER,
INTF_DIRECTION.SLAVE,
INTF_DIRECTION.TRISTATE], intfDir
d = DIRECTION.asIntfDirection(self._masterDir)
if intfDir == INTF_DIRECTION.MASTER or d == INTF_DIRECTION.TRISTATE:
pass
else:
d = INTF_DIRECTION.opposite(d)
self._direction = d
for i in self._interfaces:
i._setDirectionsLikeIn(d)
def packIntf(intf, masterDirEqTo=DIRECTION.OUT, exclude=None):
"""
Concatenate all signals to one big signal, recursively
(LSB of first interface is LSB of result)
:param masterDirEqTo: only signals with this direction are packed
:param exclude: sequence of signals/interfaces to exclude
"""
if not intf._interfaces:
if intf._masterDir == masterDirEqTo:
return intf._sig
return None
res = None
for i in intf._interfaces:
if exclude is not None and i in exclude:
continue
if i._interfaces:
if i._masterDir == DIRECTION.IN:
d = DIRECTION.opposite(masterDirEqTo)
else:
d = masterDirEqTo
s = packIntf(i, masterDirEqTo=d, exclude=exclude)
else:
if i._masterDir == masterDirEqTo:
s = i._sig
else:
s = None
if s is not None:
if res is None:
res = s
else:
res = s._concat(res)
return res
def _signalsForInterface(self,
ctx: RtlNetlist,
res: Optional[Dict[RtlSignal, DIRECTION]],
name_scope: Optional[NameScope],
prefix='',
typeTransform=None,
reverse_dir=False):
"""
Generate RtlSignal _sig and HdlPortInstance _hdl_port
for each interface which has no subinterface
:note: if already has _sig return use it instead
:param ctx: instance of RtlNetlist where signals should be created
:param res: output dictionary where result should be stored
:param prefix: name prefix for created signals
:param name_scope: name scope used to check colisions on port names
if this a current top (every component is checked
when it is seen first time)
:param typeTransform: optional function (type) returns modified type
for signal
"""
if self._interfaces:
for intf in self._interfaces:
intf._signalsForInterface(ctx,
res,
name_scope,
prefix=prefix,
typeTransform=typeTransform,
reverse_dir=reverse_dir)
else:
assert self._sig is None, self
t = self._dtype
if typeTransform is not None:
t = typeTransform(t)
s = ctx.sig(prefix + self._getPhysicalName(), t)
s._interface = self
self._sig = s
if self._isExtern:
d = INTF_DIRECTION.asDirection(self._direction)
u = ctx.parent
if reverse_dir:
d = DIRECTION.opposite(d)
assert self._hdl_port is None, (
"Now creating a hdl interface for top"
" it but seems that it was already created")
if res is not None:
res[s] = d
if reverse_dir:
pi = portItemfromSignal(s, u, d)
# port of current top component
s.name = name_scope.checked_name(s.name, s)
pi.connectInternSig(s)
ctx.ent.ports.append(pi)
else:
pi = self._hdl_port
# port of some subcomponent which names were already checked
pi.connectOuterSig(s)
self._hdl_port = pi
