def _impl(self):
assert int(self.DRIVER_CNT
) > 1, "It makes no sense to use interconnect in this case"
propagateClkRstn(self)
self.reqHandler(self.rDatapump.req, self.orderInfoFifo.dataIn)
fifoOut = self.orderInfoFifo.dataOut
r = self.rDatapump.r
driversR = [d.r for d in self.drivers]
selectedDriverReady = self._sig("selectedDriverReady")
selectedDriverReady(
Or(*[
fifoOut.data._eq(di) & d.ready for di, d in enumerate(driversR)
]))
# extra enable signals based on selected driver from orderInfoFifo
# extraHsEnableConds = {
# r : fifoOut.vld # on end of frame pop new item
# }
for i, d in enumerate(driversR):
# extraHsEnableConds[d]
d.valid(r.valid & fifoOut.vld & fifoOut.data._eq(i))
d(r, exclude=[d.valid, d.ready])
r.ready(fifoOut.vld & selectedDriverReady)
fifoOut.rd(r.valid & r.last & selectedDriverReady)
def _impl(self):
propagateClkRstn(self)
addr_crossbar = self.addr_crossbar
data_crossbar = self.data_crossbar
master_addr_channels = HObjList([m.ar for m in self.s])
slave_addr_channels = HObjList([s.ar for s in self.m])
addr_crossbar.s(master_addr_channels)
slave_addr_channels(addr_crossbar.m)
master_r_channels = HObjList([m.r for m in self.s])
master_r_channels(data_crossbar.dataOut)
slave_r_channels = HObjList([s.r for s in self.m])
data_crossbar.dataIn(slave_r_channels)
for m_i, f in enumerate(self.order_s_index_for_m_data):
if f is None:
continue
f.dataIn(addr_crossbar.order_s_index_for_m_data_out[m_i])
data_crossbar.order_din_index_for_dout_in[m_i](f.dataOut)
for s_i, f in enumerate(self.order_m_index_for_s_data):
if f is None:
continue
f.dataIn(addr_crossbar.order_m_index_for_s_data_out[s_i])
data_crossbar.order_dout_index_for_din_in[s_i](f.dataOut)
def _impl(self):
propagateClkRstn(self)
table = self.tableConnector
self.table.a(table.ram)
self.lookupLogic(table.r)
self.insertLogic(table.w)
def _impl(self):
propagateClkRstn(self)
self.regsConventor.bus(self.cntrlBus)
axi = self.axi
# disable read channel
c(0, *where(axi.ar._interfaces, lambda x: x is not axi.ar.ready))
axi.r.ready(0)
axi.b.ready(1) # we do ignore write confirmations
st_t = HEnum("state_type",
["fullIdle", "writeAddr", "writeData", "writeDataLast"])
onoff = self._reg("on_off_reg", defVal=0)
baseAddr = self._reg("baseAddr_reg", Bits(self.ADDR_WIDTH), 0)
st = self._reg("state_reg", st_t, st_t.fullIdle)
actualAddr = self._reg("actualAddr_reg", Bits(self.ADDR_WIDTH))
lenRem = self._reg("lenRem_reg",
Bits(int(self.DATA_LEN).bit_length() + 1),
self.DATA_LEN)
actualLenRem = self._reg("actualLenRem_reg", axi.aw.len._dtype)
self.connectRegisters(st, onoff, baseAddr)
self.axiWAddrHandler(st, baseAddr, actualAddr, lenRem)
self.mainFsm(st, onoff, lenRem, actualLenRem)
self.dataWFeed(st, lenRem, actualLenRem)
def _impl(self) -> None:
regs = self.regs = HObjList(
HandshakedReg(HandshakeSync) for _ in range(2))
regs[0].dataIn(self.dataIn)
regs[1].dataIn(regs[0].dataOut)
self.dataOut(regs[1].dataOut)
propagateClkRstn(self)
def _impl(self):
propagateClkRstn(self)
self.regsConventor.bus(self.cntrlBus)
axi = self.axi
# disable read channel
c(0, *where(axi.ar._interfaces, lambda x: x is not axi.ar.ready))
axi.r.ready(0)
axi.b.ready(1) # we do ignore write confirmations
st_t = HEnum("state_type", ["fullIdle", "writeAddr", "writeData",
"writeDataLast"])
onoff = self._reg("on_off_reg", defVal=0)
baseAddr = self._reg("baseAddr_reg", Bits(self.ADDR_WIDTH), 0)
st = self._reg("state_reg", st_t, st_t.fullIdle)
actualAddr = self._reg("actualAddr_reg", Bits(self.ADDR_WIDTH))
lenRem = self._reg("lenRem_reg",
Bits(int(self.DATA_LEN).bit_length() + 1),
self.DATA_LEN)
actualLenRem = self._reg("actualLenRem_reg", axi.aw.len._dtype)
self.connectRegisters(st, onoff, baseAddr)
self.axiWAddrHandler(st, baseAddr, actualAddr, lenRem)
self.mainFsm(st, onoff, lenRem, actualLenRem)
self.dataWFeed(st, lenRem, actualLenRem)
def _impl(self):
self.signalLoop.din(self.signalIn)
self.regCntrlOut(self.regCntrlLoop.dout)
self.vldSyncedOut(self.vldSyncedLoop.dout)
self.bramOut(self.bramLoop.dout)
def configEp(ep):
ep._updateParamsFrom(self)
rltSig10 = self._sig("sig", Bits(self.DATA_WIDTH), def_val=10)
interfaceMap = IntfMap([
(rltSig10, "rltSig10"),
(self.signalLoop.dout, "signal"),
(self.regCntrlLoop.din, "regCntrl"),
(self.vldSyncedLoop.din, "vldSynced"),
(self.bramLoop.din, "bram"),
(Bits(self.DATA_WIDTH), None),
])
axiLiteConv = AxiLiteEndpoint.fromInterfaceMap(interfaceMap)
axiLiteConv._updateParamsFrom(self)
self.conv = axiLiteConv
axiLiteConv.connectByInterfaceMap(interfaceMap)
axiLiteConv.bus(self.bus)
axiLiteConv.decoded.vldSynced.din(None)
propagateClkRstn(self)
def _impl(self):
propagateClkRstn(self)
r = self._reg
START_BIT = hBit(0)
STOP_BIT = hBit(1)
BITS_TO_SEND = 1 + 8 + 1
BIT_RATE = self.FREQ // self.BAUD
assert BIT_RATE >= 1
din = self.dataIn
data = r("data", Bits(BITS_TO_SEND)) # data + start bit + stop bit
en = r("en", defVal=False)
tick, last = ClkBuilder(self, self.clk).timers(
[BIT_RATE, BIT_RATE * BITS_TO_SEND], en)
If(~en & din.vld, data(Concat(STOP_BIT, din.data, START_BIT)),
en(1)).Elif(
tick & en,
# srl where 1 is shifted from left
data(hBit(1)._concat(data[:1])),
If(
last,
en(0),
))
din.rd(~en)
txd = r("reg_txd", defVal=1)
If(tick & en, txd(data[0]))
self.txd(txd)
def _impl(self):
propagateClkRstn(self)
cntr = self._reg("wordCntr", Bits(log2ceil(self.MAX_LEN)), defVal=0)
en = self._reg("enable", defVal=0)
_len = self._reg("wordCntr", Bits(log2ceil(self.MAX_LEN)), defVal=0)
self.conv.bus(self.cntrl)
cEn = self.conv.decoded.enable
If(cEn.dout.vld, connect(cEn.dout.data, en, fit=True))
connect(en, cEn.din, fit=True)
cLen = self.conv.decoded.len
If(cLen.dout.vld, connect(cLen.dout.data, _len, fit=True))
connect(_len, cLen.din, fit=True)
out = self.axis_out
connect(cntr, out.data, fit=True)
if self.USE_STRB:
out.strb(mask(self.axis_out.strb._dtype.bit_length()))
out.last(cntr._eq(0))
out.valid(en)
If(cLen.dout.vld, connect(cLen.dout.data, cntr, fit=True)).Else(
If(out.ready & en,
If(cntr._eq(0), cntr(_len)).Else(cntr(cntr - 1))))
def _impl(self):
assert int(self.DRIVER_CNT) > 1, "It makes no sense to use interconnect in this case"
propagateClkRstn(self)
self.reqHandler(self.rDatapump.req, self.orderInfoFifo.dataIn)
fifoOut = self.orderInfoFifo.dataOut
r = self.rDatapump.r
driversR = list(map(lambda d: d.r,
self.drivers))
selectedDriverReady = self._sig("selectedDriverReady")
selectedDriverReady(Or(*map(lambda d: fifoOut.data._eq(d[0]) & d[1].ready,
enumerate(driversR))
))
# extra enable signals based on selected driver from orderInfoFifo
# extraHsEnableConds = {
# r : fifoOut.vld # on end of frame pop new item
# }
for i, d in enumerate(driversR):
# extraHsEnableConds[d]
d.valid(r.valid & fifoOut.vld & fifoOut.data._eq(i))
connect(r, d, exclude=[d.valid, d.ready])
r.ready(fifoOut.vld & selectedDriverReady)
fifoOut.rd(r.valid & r.last & selectedDriverReady)
def _impl(self):
dma = AxiVirtualDma(self.axi_m, alignas=self.ALIGNAS)
rxGet, rxR = dma.read(frameHeader)
txSet, txW, wAck = dma.write(frameHeader)
dma.build()
# send address to an engine which reads and writes the packet header
HsBuilder(self, self.packetAddr)\
.split_copy_to(rxGet, txSet)
# ignore write ack
wAck.rd(1)
def withFifo(interface):
return HsBuilder(self, interface)\
.buff(items=4)\
.end
# swap dst/src in IP and Ethernet MAC, use fifo to compensate for
# a diferent arrival times of the data
txW.eth.dst(withFifo(rxR.eth.src))
txW.eth.src(withFifo(rxR.eth.dst))
txW.ipv4.dst(withFifo(rxR.ipv4.src))
txW.ipv4.src(withFifo(rxR.ipv4.dst))
propagateClkRstn(self)
def _impl(self):
propagateClkRstn(self)
self.axi_ep.bus(self.cntrl)
ep = self.axi_ep.decoded
doClr = ep.control.dout.vld
ep.control.din(1)
self.master(self.slave)
s, m = self.slave, self.master
for dir_, name in [(1, "ar"), (1, "aw"), (1, "w"), (0, "r"), (0, "b")]:
sCh = getattr(s, name)
mCh = getattr(m, name)
if not dir_:
sCh, mCh = mCh, sCh
cntrl = getattr(ep, name)
ack = StreamNode(masters={sCh}, slaves={mCh}).ack()
cntr = self._reg("cntr_" + name, Bits(self.CNTR_WIDTH), defVal=0)
If(doClr,
cntr(0)
).Elif(ack,
cntr(cntr + 1)
)
connect(cntr, cntrl.din, fit=True)
def _impl(self):
self.signalLoop.din(self.signalIn)
self.regCntrlOut(self.regCntrlLoop.dout)
self.vldSyncedOut(self.vldSyncedLoop.dout)
self.bramOut(self.bramLoop.dout)
def configEp(ep):
ep._updateParamsFrom(self)
rltSig10 = self._sig("sig", Bits(self.DATA_WIDTH), defVal=10)
interfaceMap = IntfMap([
(rltSig10, "rltSig10"),
(self.signalLoop.dout, "signal"),
(self.regCntrlLoop.din, "regCntrl"),
(self.vldSyncedLoop.din, "vldSynced"),
(self.bramLoop.din, "bram"),
(Bits(self.DATA_WIDTH), None),
])
axiLiteConv = AxiLiteEndpoint.fromInterfaceMap(interfaceMap)
axiLiteConv._updateParamsFrom(self)
self.conv = axiLiteConv
axiLiteConv.connectByInterfaceMap(interfaceMap)
axiLiteConv.bus(self.bus)
axiLiteConv.decoded.vldSynced.din(None)
propagateClkRstn(self)
def _impl(self):
propagateClkRstn(self)
addr_crossbar = self.addr_crossbar
data_crossbar = self.data_crossbar
b_crossbar = self.b_crossbar
master_addr_channels = HObjList([m.aw for m in self.s])
slave_addr_channels = HObjList([s.aw for s in self.m])
addr_crossbar.s(master_addr_channels)
slave_addr_channels(addr_crossbar.m)
master_w_channels = HObjList([m.w for m in self.s])
data_crossbar.dataIn(master_w_channels)
slave_w_channels = HObjList([s.w for s in self.m])
slave_w_channels(data_crossbar.dataOut)
master_b_channels = HObjList([m.b for m in self.s])
master_b_channels(b_crossbar.dataOut)
slave_b_channels = HObjList([s.b for s in self.m])
b_crossbar.dataIn(slave_b_channels)
for addr_crossbar_s_index_out, f_w, f_b in zip(
addr_crossbar.order_s_index_for_m_data_out,
self.order_s_index_for_m_data, self.order_s_index_for_m_b):
if f_w is None:
assert f_b is None
continue
HsBuilder(self, addr_crossbar_s_index_out)\
.split_copy_to(f_w.dataIn, f_b.dataIn)
for f_w, f_b, data_dout_for_din, b_din_for_dout in zip(
self.order_s_index_for_m_data, self.order_s_index_for_m_b,
data_crossbar.order_dout_index_for_din_in,
b_crossbar.order_din_index_for_dout_in):
if f_w is None:
assert f_b is None
continue
data_dout_for_din(f_w.dataOut)
b_din_for_dout(f_b.dataOut)
for addr_crossbar_m_index_out, f_w, f_b in zip(
addr_crossbar.order_m_index_for_s_data_out,
self.order_m_index_for_s_data, self.order_m_index_for_s_b):
if f_w is None:
assert f_b is None
assert addr_crossbar_m_index_out is None
continue
HsBuilder(self, addr_crossbar_m_index_out)\
.split_copy_to(f_w.dataIn, f_b.dataIn)
for f_w, f_b, data_din_for_dout, b_dout_for_din in zip(
self.order_m_index_for_s_data, self.order_m_index_for_s_b,
data_crossbar.order_din_index_for_dout_in,
b_crossbar.order_dout_index_for_din_in):
if f_w is None:
assert f_b is None
assert data_din_for_dout is None
continue
data_din_for_dout(f_w.dataOut)
b_dout_for_din(f_b.dataOut)
def _impl(self):
propagateClkRstn(self)
nextBlockTransition = self._sig("nextBlockTransition")
baseIndex, nextBaseIndex, nextBaseReady = self.baseAddrLogic(
nextBlockTransition)
self.itemUploadLogic(baseIndex, nextBaseIndex, nextBaseReady,
nextBlockTransition)
def _impl(self):
propagateClkRstn(self)
if self.HAS_R:
self.conv.r(self.r)
if self.HAS_W:
self.conv.w(self.w)
self.ram.port[0](self.conv.ram)
def _impl(self):
assert int(self.DRIVER_CNT
) > 1, "It makes no sense to use interconnect in this case"
propagateClkRstn(self)
self.reqHandler(self.wDatapump.req, self.orderInfoFifoW.dataIn)
self.wHandler()
self.ackHandler()
def _impl(self):
req = self.wDatapump.req
w = self.wDatapump.w
ack = self.wDatapump.ack
# multi frame
ackPropageteInfo = HandshakedFifo(Handshaked)
ackPropageteInfo.DATA_WIDTH.set(1)
ackPropageteInfo.DEPTH.set(self.MAX_OVERLAP)
self.ackPropageteInfo = ackPropageteInfo
propagateClkRstn(self)
if self.WRITE_ACK:
_set = self.set
else:
_set = HsBuilder(self, self.set).buff().end
req.id(self.ID)
req.rem(0)
def propagateRequests(frame, indx):
ack = StreamNode(slaves=[req, ackPropageteInfo.dataIn]).ack()
statements = [req.addr(_set.data + frame.startBitAddr // 8),
req.len(frame.getWordCnt() - 1),
StreamNode(slaves=[req, ackPropageteInfo.dataIn],
).sync(_set.vld)
]
if indx != 0:
prop = SKIP
else:
prop = PROPAGATE
statements.append(ackPropageteInfo.dataIn.data(prop))
isLastFrame = indx == len(self._frames) - 1
if isLastFrame:
statements.append(_set.rd(ack))
else:
statements.append(_set.rd(0))
return statements, ack & _set.vld
StaticForEach(self, self._frames, propagateRequests)
# connect write channel
w(self.frameAssember.dataOut)
# propagate ack
StreamNode(masters=[ack, ackPropageteInfo.dataOut],
slaves=[self.writeAck],
skipWhen={
self.writeAck: ackPropageteInfo.dataOut.data._eq(PROPAGATE)
}).sync()
# connect fields to assembler
for _, transTmpl in self._tmpl.walkFlatten():
f = transTmpl.origin
intf = self.frameAssember.dataIn._fieldsToInterfaces[f]
intf(self.dataIn._fieldsToInterfaces[f])
def _impl(self):
START_BIT = 0
STOP_BIT = 1
os = int(self.OVERSAMPLING)
baud = int(self.BAUD)
freq = int(self.FREQ)
assert freq >= baud * os, "Frequency too low for current Baud rate and oversampling"
assert os >= 8 and (os & (os - 1)) == 0, "Invalid oversampling value"
propagateClkRstn(self)
clkBuilder = ClkBuilder(self, self.clk)
en = self._reg("en", defVal=0)
first = self._reg("first", defVal=1)
RxD_data = self._reg("RxD_data", Bits(1 + 8))
startBitWasNotStartbit = self._sig("startBitWasNotStartbit")
# it can happen that there is just glitch on wire and bit was not startbit only begin was resolved wrong
# eval because otherwise vhdl int overflows
sampleTick = clkBuilder.timer(
("sampleTick", self.FREQ // self.BAUD // self.OVERSAMPLING),
enableSig=en,
rstSig=~en)
# synchronize RxD to our clk domain
RxD_sync = self._reg("RxD_sync", defVal=1)
RxD_sync(self.rxd)
rxd, rxd_vld = clkBuilder.oversample(RxD_sync,
self.OVERSAMPLING,
sampleTick,
rstSig=~en)
isLastBit = clkBuilder.timer(("isLastBitTick", 10),
enableSig=rxd_vld,
rstSig=~en)
If(
en,
If(
rxd_vld,
RxD_data(Concat(rxd, RxD_data[9:1])), # shift data from left
If(
startBitWasNotStartbit,
en(0),
first(1),
).Else(
en(~isLastBit),
first(isLastBit),
))).Elif(
RxD_sync._eq(START_BIT),
# potential start bit detected, begin scanning sequence
en(1),
)
startBitWasNotStartbit(first & rxd_vld & (rxd != START_BIT))
self.dataOut.vld(isLastBit & RxD_data[0]._eq(START_BIT)
& rxd._eq(STOP_BIT))
self.dataOut.data(RxD_data[9:1])
def _impl(self):
assert(int(self.USER_WIDTH) == 2) # this is how is protocol specified
In = self.dataIn
Out = self.dataOut
propagateClkRstn(self)
lastSeenLast = self._reg("lastSeenLast", defVal=1)
sof = lastSeenLast
Out.data(In.data)
Out.src_rdy_n(~In.valid)
outRd = ~Out.dst_rdy_n
If(In.valid & outRd,
lastSeenLast(In.last)
)
In.ready(outRd)
Out.eof_n(~In.last)
# AXI_USER(0) -> FL_SOP_N
# Always set FL_SOP_N when FL_SOF_N - added for compatibility with xilinx
# axi components. Otherwise FL_SOP_N would never been set and LocalLink
# protocol would be broken.
sop = In.user[0]
If(sof,
Out.sop_n(0)
).Else(
Out.sop_n( ~sop)
)
# AXI_USER(1) -> FL_EOP_N
# Always set FL_EOP_N when FL_EOF_N - added for compatibility with xilinx
# axi components. Otherwise FL_EOP_N would never been set and LocalLink
# protocol would be broken.
eop = In.user[1]
If(In.last,
Out.eop_n(0)
).Else(
Out.eop_n(~eop)
)
remMap = []
remBits = Out.rem._dtype.bit_length()
strbBits = In.strb._dtype.bit_length()
for strb, rem in strbToRem(strbBits, remBits):
remMap.append((strb, Out.rem(rem)))
end_of_part_or_transaction = In.last | eop
If(end_of_part_or_transaction,
Switch(In.strb)\
.addCases(remMap)
).Else(
Out.rem(mask(remBits))
)
Out.sof_n(~sof)
def _impl(self):
propagateClkRstn(self)
self.u0.c(self.a[0])
self.u1.c(self.a[1])
# u2in = connect(a[2], u2.c)
self.b[0](self.u0.d)
self.b[1](self.u1.d)
def _impl(self):
propagateClkRstn(self)
self.u0.c(self.a[0])
self.u1.c(self.a[1])
# u2in = u2.c(a[2])
self.b[0](self.u0.d)
self.b[1](self.u1.d)
def _impl(self):
w = self.port[0]
ram_w = self.ram.port[0]
# True if each byte of the mask is 0xff or 0x00
we_bytes = list(iterBits(w.we, bitsInOne=8, fillup=True))
# cut off padding
we_for_we_bytes = []
for last, b in iter_with_last(we_bytes):
if last and self.MASK_PADDING_W:
mask_rem_w = self.MASK_W % 8
b = b[mask_rem_w:]
we_for_we_bytes.append(b != 0)
we_for_we_bytes = rename_signal(
self,
Concat(*[
b | ~w.do_accumulate | w.do_overwrite
for b in reversed(we_for_we_bytes)
]), "we_for_we_bytes")
preload = self._reg("preload", def_val=0)
If(w.en.vld, preload(~preload & w.do_accumulate & ~w.do_overwrite))
w.en.rd(~w.do_accumulate | w.do_overwrite | preload)
ram_w.addr(w.addr)
ram_w.en(w.en.vld & (w.do_overwrite | ~w.do_accumulate | preload))
ram_w.we(Concat(w.we, we_for_we_bytes))
w_mask = w.we
if self.MASK_PADDING_W:
w_mask = Concat(Bits(self.MASK_PADDING_W).from_py(0), w_mask)
is_first_read_port = True
for ram_r, r in zip(self.ram.port[1:], self.port[1:]):
if is_first_read_port:
w_mask = preload._ternary(
w_mask | ram_r.dout[self.MASK_PADDING_W + self.MASK_W:],
w_mask)
w_mask = rename_signal(self, w_mask, "w_mask")
ram_w.din(Concat(w.din, w_mask))
will_preload_for_accumulate = rename_signal(
self, w.en.vld & w.do_accumulate & ~w.do_overwrite,
"will_preload_for_accumulate")
ram_r.addr(will_preload_for_accumulate._ternary(
w.addr, r.addr))
ram_r.en(will_preload_for_accumulate | r.en.vld)
# [TODO] check if r.en.rd is according to spec
r.en.rd(~will_preload_for_accumulate | preload)
is_first_read_port = False
else:
ram_r.addr(r.addr)
ram_r.en(r.en.vld)
r.en.rd(1)
r.dout(ram_r.dout[:self.MASK_PADDING_W + self.MASK_W])
r.dout_mask(ram_r.dout[self.MASK_W:])
propagateClkRstn(self)
def _impl(self):
req = self.wDatapump.req
w = self.wDatapump.w
ack = self.wDatapump.ack
# multi frame
if self.MAX_OVERLAP > 1:
ackPropageteInfo = HandshakedFifo(Handshaked)
ackPropageteInfo.DEPTH = self.MAX_OVERLAP
else:
ackPropageteInfo = HandshakedReg(Handshaked)
ackPropageteInfo.DATA_WIDTH = 1
self.ackPropageteInfo = ackPropageteInfo
if self.WRITE_ACK:
_set = self.set
else:
_set = HsBuilder(self, self.set).buff().end
if self.ID_WIDTH:
req.id(self.ID)
def propagateRequest(frame, indx):
inNode = StreamNode(slaves=[req, ackPropageteInfo.dataIn])
ack = inNode.ack()
isLastFrame = indx == len(self._frames) - 1
statements = [
req.addr(_set.data + frame.startBitAddr // 8),
req.len(frame.getWordCnt() - 1),
self.driveReqRem(
req, frame.parts[-1].endOfPart - frame.startBitAddr),
ackPropageteInfo.dataIn.data(SKIP if indx != 0 else PROPAGATE),
inNode.sync(_set.vld),
_set.rd(ack if isLastFrame else 0),
]
return statements, ack & _set.vld
StaticForEach(self, self._frames, propagateRequest)
# connect write channel
w(self.frameAssember.dataOut)
# propagate ack
StreamNode(masters=[ack, ackPropageteInfo.dataOut],
slaves=[self.writeAck],
skipWhen={
self.writeAck:
ackPropageteInfo.dataOut.data._eq(PROPAGATE)
}).sync()
# connect fields to assembler
for _, transTmpl in self._tmpl.walkFlatten():
f = transTmpl.getFieldPath()
intf = self.frameAssember.dataIn._fieldsToInterfaces[f]
intf(self.dataIn._fieldsToInterfaces[f])
propagateClkRstn(self)
def _impl(self):
propagateClkRstn(self)
toMi32 = self.toMi32
toAxi = self.toAxi
m = AxiBuilder(self, self.s).buff().end
toMi32.s(m)
toAxi.s(toMi32.m)
self.m(AxiBuilder(self, toAxi.m).buff().end)
def _impl(self):
propagateClkRstn(self)
self.u0.a(self.a)
self.u1.a(self.u0.c)
self.u2_0.a(self.u1.b[0])
self.u2_1.a(self.u1.b[1])
self.b0(self.u2_0.c)
self.b1(self.u2_1.c)
def _impl(self):
propagateClkRstn(self)
self.u0.a(self.a)
self.u1.a(self.u0.c)
self.u2_0.a(self.u1.b[0])
self.u2_1.a(self.u1.b[1])
self.b0(self.u2_0.c)
self.b1(self.u2_1.c)
def _impl(self):
o = axiS_strFormat(self,
"f0",
self.DATA_WIDTH,
"{0:s}{1:s}xyz{str2:s}",
self.str0,
self.str1,
str2=self.str2)
self.out(o)
propagateClkRstn(self)
def _impl(self):
"""
Read operation:
* Use index to lookup in tag memory
* if tag matches return cacheline else dispatch read request
(the transaction is dispatched with original id, uppon data receive the transaction
is passed to master without any synchronisation with the cache )
Write operation:
* Use index to lookup in tag memory
* If tag matches and the cacheline is not beeing replaced update the data in data array.
* If tag is not found in corresponding set select a victim and read it from data array, flush it
and write back cacheline to array and update tag
"""
# transaction type usind in data array memory access pipeline
data_array_r, data_array_w = self.data_array.port
ar_tagRes, aw_tagRes = self.tag_array.lookupRes
with self._paramsShared():
data_arr_read = self.data_arr_read = Axi4_r()
data_arr_read_req = IndexWayHs()
data_arr_read_req.INDEX_WIDTH = self.INDEX_W
self.data_arr_read_req = data_arr_read_req
self.connect_tag_lookup()
# addd a register with backup register for poential overflow
# we need this as we need to check if we can store data in advance.
# this is because we need a higher priority for flushing
# in order to avoid deadlock.
_data_arr_read = AxiSBuilder(self, data_arr_read)\
.buff(1, latency=(1, 2))\
.end
_data_arr_read_req = HsBuilder(self, data_arr_read_req)\
.buff(1, latency=(1, 2))\
.end
self.read_handler(self.lru_array.incr[0], ar_tagRes, data_arr_read_req,
_data_arr_read)
self.data_array_io(
self.lru_array.incr[1],
aw_tagRes,
self.lru_array.victim_req,
self.lru_array.victim_data,
_data_arr_read_req,
data_arr_read,
data_array_r,
data_array_w,
self.tag_array.update[0],
)
propagateClkRstn(self)
def _impl(self):
START_BIT = 0
STOP_BIT = 1
os = int(self.OVERSAMPLING)
baud = int(self.BAUD)
freq = int(self.FREQ)
assert freq >= baud * os, "Frequency too low for current Baud rate and oversampling"
assert os >= 8 and (os & (os - 1)) == 0, "Invalid oversampling value"
propagateClkRstn(self)
clkBuilder = ClkBuilder(self, self.clk)
en = self._reg("en", defVal=0)
first = self._reg("first", defVal=1)
RxD_data = self._reg("RxD_data", Bits(1 + 8))
startBitWasNotStartbit = self._sig("startBitWasNotStartbit")
# it can happen that there is just glitch on wire and bit was not startbit only begin was resolved wrong
# eval because otherwise vhdl int overflows
sampleTick = clkBuilder.timer(("sampleTick", self.FREQ // self.BAUD // self.OVERSAMPLING),
enableSig=en,
rstSig=~en)
# synchronize RxD to our clk domain
RxD_sync = self._reg("RxD_sync", defVal=1)
RxD_sync(self.rxd)
rxd, rxd_vld = clkBuilder.oversample(RxD_sync,
self.OVERSAMPLING,
sampleTick,
rstSig=~en)
isLastBit = clkBuilder.timer(("isLastBitTick", 10),
enableSig=rxd_vld,
rstSig=~en)
If(en,
If(rxd_vld,
RxD_data(Concat(rxd, RxD_data[9:1])), # shift data from left
If(startBitWasNotStartbit,
en(0),
first(1),
).Else(
en(~isLastBit),
first(isLastBit),
)
)
).Elif(RxD_sync._eq(START_BIT),
# potential start bit detected, begin scanning sequence
en(1),
)
startBitWasNotStartbit(first & rxd_vld & (rxd != START_BIT))
self.dataOut.vld(isLastBit & RxD_data[0]._eq(START_BIT) & rxd._eq(STOP_BIT))
self.dataOut.data(RxD_data[9:1])
def _impl(self):
propagateClkRstn(self)
dp = self.dp
ic = self.ic
self.aw(dp.a)
self.w(dp.w)
dp.b(self.b)
dp.driver(ic.wDatapump)
ic.drivers(self.drivers)
def _impl(self):
propagateClkRstn(self)
dp = self.dp
ic = self.ic
self.aw(dp.a)
self.w(dp.w)
dp.b(self.b)
dp.driver(ic.wDatapump)
ic.drivers(self.drivers)
def _impl(self):
propagateClkRstn(self)
dIn = AxiSBuilder(self, self.dataIn).buff().end
sb = self.sizesBuff
db = self.dataBuff
wordCntr = self._reg("wordCntr",
Bits(log2ceil(self.MAX_LEN) + 1),
def_val=0)
overflow = wordCntr._eq(self.MAX_LEN)
last = dIn.last | overflow
If(
StreamNode(masters=[dIn], slaves=[sb.dataIn, db.dataIn]).ack(),
If(last, wordCntr(0)).Else(wordCntr(wordCntr + 1)))
length = self._sig("length", wordCntr._dtype)
BYTE_CNT = dIn.data._dtype.bit_length() // 8
if dIn.USE_STRB:
# compress strb mask as binary number
rem = self._sig("rem", Bits(log2ceil(BYTE_CNT)))
SwitchLogic(cases=[(dIn.strb[i],
rem(0 if i == BYTE_CNT - 1 else i + 1))
for i in reversed(range(BYTE_CNT))],
default=[
rem(0),
])
if self.EXPORT_ALIGNMENT_ERROR:
errorAlignment = self._reg("errorAlignment_reg", def_val=0)
self.errorAlignment(errorAlignment)
If(dIn.valid & (dIn.strb != mask(BYTE_CNT)) & ~dIn.last,
errorAlignment(1))
If(last & (dIn.strb != mask(BYTE_CNT)),
length(wordCntr)).Else(length(wordCntr + 1))
else:
length(wordCntr + 1)
rem = Bits(log2ceil(BYTE_CNT)).from_py(0)
sb.dataIn.data(Concat(length, rem))
db.dataIn(dIn, exclude=[dIn.valid, dIn.ready, dIn.last])
db.dataIn.last(last)
StreamNode(masters=[dIn],
slaves=[sb.dataIn, db.dataIn],
extraConds={
sb.dataIn: last
}).sync()
self.sizes(sb.dataOut)
self.dataOut(db.dataOut)
def _impl(self) -> None:
ram = self.ram
al = AxiBuilder(self, self.s).to_axi(Axi4Lite).end
with self._paramsShared():
dec = self.decoder = AxiLiteEndpoint(
HStruct((ram.port[0].dout._dtype[2**ram.ADDR_WIDTH], "ram")))
dec.bus(al)
ram.port[0](dec.decoded.ram)
propagateClkRstn(self)
def _impl(self):
propagateClkRstn(self)
segfaultFlag = self.segfaultChecker()
lvl1read = self.connectLvl1PageTable()
self.connectL1Load(lvl1read.addr)
self.connectL2Load(lvl1read.data, segfaultFlag)
self.connectPhyout(segfaultFlag)
self.segfault(segfaultFlag)
def _impl(self):
propagateClkRstn(self)
segfaultFlag = self.segfaultChecker()
lvl1read = self.connectLvl1PageTable()
self.connectL1Load(lvl1read.addr)
self.connectL2Load(lvl1read.data, segfaultFlag)
self.connectPhyout(segfaultFlag)
self.segfault(segfaultFlag)
def _impl(self):
if self.ADD_NAME_MEMORY:
name_memory, name_memory_size, name_content_size =\
self.build_name_memory(self.monitored_data)
else:
name_content_size = 0
const_uint32_t = Bits(32, signed=False, const=True)
addr_space = IntfMap([
(const_uint32_t, "name_memory_size"),
(const_uint32_t, "name_memory_offset"),
(IntfMap(
(Interface_to_HdlType().apply(i, const=True), name)
for i, name, _, _, _ in self.monitored_data), "data_memory"),
])
data_part_t = HTypeFromIntfMap(addr_space)
data_part_width = data_part_t.bit_length()
if self.ADD_NAME_MEMORY:
closest_pow2 = 2**data_part_width.bit_length()
if data_part_width != closest_pow2:
# padding between data_memory and name_memory
addr_space.append((Bits(closest_pow2 - data_part_width), None))
name_memory_offset = closest_pow2 // 8
name_mem_words = name_memory_size // (self.DATA_WIDTH // 8)
addr_space.append(
(Bits(self.DATA_WIDTH,
const=True)[name_mem_words], "name_memory"))
else:
name_memory_offset = 0
ep = self._bus_endpoint_cls.fromInterfaceMap(addr_space)
with self._paramsShared():
self.ep = ep
ep.bus(self.s)
ep.decoded.name_memory_size(name_content_size)
ep.decoded.name_memory_offset(name_memory_offset)
for intf, (_, name, _, _, _) in zip(self.monitor, self.monitored_data):
to_bus_intf = getattr(ep.decoded.data_memory, name)
connect_MonitorIntf(intf, to_bus_intf)
if self.ADD_NAME_MEMORY:
name_memory = rename_signal(self, name_memory, "name_memory")
name_memory_reader = ep.decoded.name_memory
If(
self.clk._onRisingEdge(),
If(
name_memory_reader.en,
name_memory_reader.dout(
name_memory[name_memory_reader.addr])))
propagateClkRstn(self)
def _impl(self):
s = self
propagateClkRstn(s)
AxiSBuilder(self, s.hfe.dout).split_copy_to(s.patternMatch.din,
s.filter.din)
s.hfe.din(s.din)
s.filter.headers(s.hfe.headers)
s.filter.patternMatch(s.patternMatch.match)
s.exporter.din(s.filter.dout)
s.export(s.exporter.dout)
self.filter.cfg(s.cfg)
def _impl(self):
of = self.ooo_fifo
data_ram = self.data_ram
self.data_insert(data_ram.port[0])
wd = self.write_dispatch
self.m(wd.m)
data_ram.port[1](wd.data)
of.read_confirm(wd.read_confirm)
wd.read_execute(of.read_execute)
propagateClkRstn(self)
def _impl(self):
s = self
propagateClkRstn(s)
AxiSBuilder(self, s.hfe.dout).split_copy_to(s.patternMatch.din,
s.filter.din)
s.hfe.din(s.din)
s.filter.headers(s.hfe.headers)
s.filter.patternMatch(s.patternMatch.match)
s.exporter.din(s.filter.dout)
s.export(s.exporter.dout)
self.filter.cfg(s.cfg)
def _impl(self):
"""
* read on 'en' faling edge, write on 'en' rising edge
* 'en' max frequency = LCD_FREQ / 10
* rs has to be set at least 1 clk (LCD_FREQ) before rising edge of 'en'
"""
LCD_DW = self.LCD_DATA_WIDTH
assert LCD_DW in (4, 8), LCD_DW
cmd_timer_rst = self._sig("cmd_timer_rst")
HALF_LCD_PERIOD = ceil(self.FREQ / (self.LCD_FREQ * 2))
LCD_CLK_PER = 2 * HALF_LCD_PERIOD
lcd_clk_en, = ClkBuilder(self, self.clk).timers([
("lcd_clk_en", LCD_CLK_PER),
])
delay_cmd_half_done, delay_cmd_done, delay_cmd_long_done =\
ClkBuilder(self, self.clk)\
.timers([
# used to signalize that the 'en' should be asserted low
("delay_cmd_half_done", Hd44780Intf.DELAY_CMD // 2),
# used to signalize that the processing of command is completed
("delay_cmd_done", Hd44780Intf.DELAY_CMD),
# used to signalize that the long command (return home, etc.) is completed
("delay_cmd_long_done", Hd44780Intf.DELAY_RETURN_HOME)
],
enableSig=lcd_clk_en,
rstSig=cmd_timer_rst
)
data_in_tmp = Hd44780CmdIntf()
data_in_tmp.DATA_WIDTH = self.LCD_DATA_WIDTH
self.data_in_tmp = data_in_tmp
self._io_core(data_in_tmp, cmd_timer_rst,
lcd_clk_en, delay_cmd_half_done,
delay_cmd_done, delay_cmd_long_done)
INIT_SEQUENCE = [
Hd44780Intf.CMD_FUNCTION_SET(
Hd44780Intf.DATA_LEN_8b if LCD_DW == 8 else Hd44780Intf.DATA_LEN_4b,
self.LCD_ROWS - 1,
Hd44780Intf.FONT_5x8),
Hd44780Intf.CMD_DISPLAY_CONTROL(1, 0, 0),
Hd44780Intf.CMD_ENTRY_MODE_SET(1, 1),
]
init_seq = Hd44780CmdIntfBurst()
init_seq.DATA_WIDTH = self.LCD_DATA_WIDTH
init_seq.DATA = tuple(
(Hd44780Intf.RS_CONTROL, Hd44780Intf.RW_WRITE, 0, d)
for d in INIT_SEQUENCE
)
self.init_seq = init_seq
propagateClkRstn(self)
data_in = self._translate_data_in(self.dataIn)
data_in_tmp(HsBuilder.join_prioritized(self, [init_seq.dataOut, data_in]).end)
def _impl(self, clks: Optional[Tuple[Clk, Clk]]=None):
"""
:clks: optional tuple (inClk, outClk)
"""
rd = self.getRd
vld = self.getVld
# connect clock and resets
if clks is None:
propagateClkRstn(self)
inClk, outClk = (None, None)
else:
propagateRstn(self)
inClk, outClk = clks
self.fifo.dataIn_clk(inClk)
self.fifo.dataOut_clk(outClk)
# to fifo
fIn = self.fifo.dataIn
din = self.dataIn
wr_en = ~fIn.wait
rd(din)(wr_en)
fIn.data(packIntf(din, exclude=[vld(din), rd(din)]))
fIn.en(vld(din) & wr_en)
# from fifo
fOut = self.fifo.dataOut
dout = self.dataOut
out_vld = self._reg("out_vld", defVal=0, clk=outClk)
vld(dout)(out_vld)
connectPacked(fOut.data,
dout,
exclude=[vld(dout), rd(dout)])
fOut.en((rd(dout) | ~out_vld) & ~fOut.wait)
If(rd(dout) | ~out_vld,
out_vld(~fOut.wait)
)
if self.EXPORT_SIZE:
sizeTmp = self._sig("sizeTmp", self.size._dtype)
connect(self.fifo.size, sizeTmp, fit=True)
If(out_vld,
self.size(sizeTmp + 1)
).Else(
connect(self.fifo.size, self.size, fit=True)
)
def _impl(self):
propagateClkRstn(self)
req = self.rDatapump.req
req.rem(0)
if self.READ_ACK:
get = self.get
else:
get = HsBuilder(self, self.get).buff().end
def f(frame, indx):
s = [req.addr(get.data + frame.startBitAddr // 8),
req.len(frame.getWordCnt() - 1),
req.vld(get.vld)
]
isLastFrame = indx == len(self._frames) - 1
if isLastFrame:
rd = req.rd
else:
rd = 0
s.append(get.rd(rd))
ack = StreamNode(masters=[get], slaves=[self.rDatapump.req]).ack()
return s, ack
StaticForEach(self, self._frames, f)
r = self.rDatapump.r
data_sig_to_exclude = []
req.id(self.ID)
if hasattr(r, "id"):
data_sig_to_exclude.append(r.id)
if hasattr(r, "strb"):
data_sig_to_exclude.append(r.strb)
connect(r, self.parser.dataIn, exclude=data_sig_to_exclude)
for _, field in self._tmpl.walkFlatten():
myIntf = self.dataOut._fieldsToInterfaces[field.origin]
parserIntf = self.parser.dataOut._fieldsToInterfaces[field.origin]
myIntf(parserIntf)
def _impl(self):
propagateClkRstn(self)
ITEM_WIDTH = int(self.ITEM_WIDTH)
DATA_WIDTH = int(self.DATA_WIDTH)
ITEMS_IN_DATA_WORD = self.ITEMS_IN_DATA_WORD
ITEM_SIZE_IN_WORDS = 1
if ITEM_WIDTH % 8 != 0 or ITEM_SIZE_IN_WORDS * DATA_WIDTH != ITEMS_IN_DATA_WORD * ITEM_WIDTH:
raise NotImplementedError(ITEM_WIDTH)
req = self.rDatapump.req
req.id(self.ID)
req.len(ITEM_SIZE_IN_WORDS - 1)
req.rem(0)
if ITEMS_IN_DATA_WORD == 1:
addr = Concat(self.index.data, vec(0, log2ceil(ITEM_WIDTH // 8)))
req.addr(self.base + fitTo(addr, req.addr))
StreamNode(masters=[self.index], slaves=[req]).sync()
self.item.data(self.rDatapump.r.data)
StreamNode(masters=[self.rDatapump.r], slaves=[self.item]).sync()
else:
r = self.rDatapump.r.data
f = self.itemSubIndexFifo
subIndexBits = f.dataIn.data._dtype.bit_length()
itemAlignBits = log2ceil(ITEM_WIDTH // 8)
addr = Concat(self.index.data[:subIndexBits],
vec(0, itemAlignBits + subIndexBits))
req.addr(self.base + fitTo(addr, req.addr))
f.dataIn.data(self.index.data[subIndexBits:])
StreamNode(masters=[self.index],
slaves=[req, f.dataIn]).sync()
Switch(f.dataOut.data).addCases([
(ITEMS_IN_DATA_WORD - i - 1, self.item.data(r[(ITEM_WIDTH * (i + 1)): (ITEM_WIDTH * i)]))
for i in range(ITEMS_IN_DATA_WORD)
])
StreamNode(masters=[self.rDatapump.r, f.dataOut],
slaves=[self.item]).sync()
def _impl(self):
self.regCntrlOut0(self.regCntrlLoop0.dout)
self.regCntrlOut1(self.regCntrlLoop1.dout)
self.regCntrlOut2(self.regCntrlLoop2.dout)
def configEp(ep):
ep._updateParamsFrom(self)
interfaceMap = IntfMap([
([self.regCntrlLoop0.din,
self.regCntrlLoop1.din,
self.regCntrlLoop2.din,
], "regCntrl"),
])
axiLiteConv = AxiLiteEndpoint.fromInterfaceMap(interfaceMap)
axiLiteConv._updateParamsFrom(self)
self.conv = axiLiteConv
axiLiteConv.connectByInterfaceMap(interfaceMap)
axiLiteConv.bus(self.bus)
propagateClkRstn(self)
def _impl(self):
propagateClkRstn(self)
cntr = self._reg("wordCntr", Bits(log2ceil(self.MAX_LEN)), defVal=0)
en = self._reg("enable", defVal=0)
_len = self._reg("wordCntr", Bits(log2ceil(self.MAX_LEN)), defVal=0)
self.conv.bus(self.cntrl)
cEn = self.conv.decoded.enable
If(cEn.dout.vld,
connect(cEn.dout.data, en, fit=True)
)
connect(en, cEn.din, fit=True)
cLen = self.conv.decoded.len
If(cLen.dout.vld,
connect(cLen.dout.data, _len, fit=True)
)
connect(_len, cLen.din, fit=True)
out = self.axis_out
connect(cntr, out.data, fit=True)
if self.USE_STRB:
out.strb(mask(self.axis_out.strb._dtype.bit_length()))
out.last(cntr._eq(0))
out.valid(en)
If(cLen.dout.vld,
connect(cLen.dout.data, cntr, fit=True)
).Else(
If(out.ready & en,
If(cntr._eq(0),
cntr(_len)
).Else(
cntr(cntr - 1)
)
)
)
def _impl(self):
In = self.dataIn
rd = self.getRd
sel = self.selectOneHot
r = HandshakedReg(Handshaked)
r.DATA_WIDTH.set(sel.data._dtype.bit_length())
self.selReg = r
r.dataIn(sel)
propagateClkRstn(self)
sel = r.dataOut
for index, outIntf in enumerate(self.dataOut):
for ini, outi in zip(In._interfaces, outIntf._interfaces):
if ini == self.getVld(In):
# out.vld
outi(sel.vld & ini & sel.data[index])
elif ini == rd(In):
pass
else: # data
outi(ini)
din = self.dataIn
SwitchLogic(
cases=[(~sel.vld, [sel.rd(0),
rd(In)(0)])
] +
[(sel.data[index],
[rd(In)(rd(out)),
sel.rd(rd(out) & self.getVld(din) & sel.vld & self._select_consume_en())])
for index, out in enumerate(self.dataOut)],
default=[
sel.rd(None),
rd(In)(None)
]
)
def _impl(self):
propagateClkRstn(self)
r = self._reg
START_BIT = hBit(0)
STOP_BIT = hBit(1)
BITS_TO_SEND = 1 + 8 + 1
BIT_RATE = self.FREQ // self.BAUD
assert BIT_RATE >= 1
din = self.dataIn
data = r("data", Bits(BITS_TO_SEND)) # data + start bit + stop bit
en = r("en", defVal=False)
tick, last = ClkBuilder(self, self.clk).timers(
[BIT_RATE, BIT_RATE * BITS_TO_SEND],
en)
If(~en & din.vld,
data(Concat(STOP_BIT, din.data, START_BIT)),
en(1)
).Elif(tick & en,
# srl where 1 is shifted from left
data(hBit(1)._concat(data[:1])),
If(last,
en(0),
)
)
din.rd(~en)
txd = r("reg_txd", defVal=1)
If(tick & en,
txd(data[0])
)
self.txd(txd)
def _impl(self):
propagateClkRstn(self)
connectDp(self, self.rxPacketLoader, self.rxDataPump, self.axi_m)
connectDp(self, self.txPacketUpdater, self.txDataPump, self.axi_m)
self.txPacketUpdater.writeAck.rd(1)
rxR = self.rxPacketLoader.dataOut
txW = self.txPacketUpdater.dataIn
def withFifo(interface):
return HsBuilder(self, interface)\
.buff(items=4)\
.end
txW.eth.dst(withFifo(rxR.eth.src))
txW.eth.src(withFifo(rxR.eth.dst))
txW.ipv4.dst(withFifo(rxR.ipv4.src))
txW.ipv4.src(withFifo(rxR.ipv4.dst))
HsBuilder(self, self.packetAddr).split_copy_to(
self.rxPacketLoader.get,
self.txPacketUpdater.set)
def _impl(self):
propagateClkRstn(self)
r, s = self._reg, self._sig
req = self.rDatapump.req
f = self.dataFifo
dIn = self.rDatapump.r
dBuffIn = f.dataIn
ALIGN_BITS = self.addrAlignBits()
ID = self.ID
BUFFER_CAPACITY = self.BUFFER_CAPACITY
BURST_LEN = BUFFER_CAPACITY // 2
ID_LAST = self.ID_LAST
bufferHasSpace = s("bufferHasSpace")
bufferHasSpace(f.size < (BURST_LEN + 1))
# we are counting base next addr as item as well
inBlock_t = Bits(log2ceil(self.ITEMS_IN_BLOCK + 1))
ringSpace_t = Bits(self.PTR_WIDTH)
downloadPending = r("downloadPending", defVal=0)
baseIndex = r("baseIndex", Bits(self.ADDR_WIDTH - ALIGN_BITS))
inBlockRemain = r("inBlockRemain_reg", inBlock_t, defVal=self.ITEMS_IN_BLOCK)
self.inBlockRemain(inBlockRemain)
# Logic of tail/head
rdPtr = r("rdPtr", ringSpace_t, defVal=0)
wrPtr = r("wrPtr", ringSpace_t, defVal=0)
If(self.wrPtr.dout.vld,
wrPtr(self.wrPtr.dout.data)
)
self.wrPtr.din(wrPtr)
self.rdPtr.din(rdPtr)
# this means items are present in memory
hasSpace = s("hasSpace")
hasSpace(wrPtr != rdPtr)
doReq = s("doReq")
doReq(bufferHasSpace & hasSpace & ~downloadPending & req.rd)
req.rem(0)
self.dataOut(f.dataOut)
# logic of baseAddr and baseIndex
baseAddr = Concat(baseIndex, vec(0, ALIGN_BITS))
req.addr(baseAddr)
self.baseAddr.din(baseAddr)
dataAck = dIn.valid & In(dIn.id, [ID, ID_LAST]) & dBuffIn.rd
If(self.baseAddr.dout.vld,
baseIndex(self.baseAddr.dout.data[:ALIGN_BITS])
).Elif(dataAck & downloadPending,
If(dIn.last & dIn.id._eq(ID_LAST),
baseIndex(dIn.data[self.ADDR_WIDTH:ALIGN_BITS])
).Else(
baseIndex(baseIndex + 1)
)
)
sizeByPtrs = s("sizeByPtrs", ringSpace_t)
sizeByPtrs(wrPtr - rdPtr)
inBlockRemain_asPtrSize = fitTo(inBlockRemain, sizeByPtrs)
constraingSpace = s("constraingSpace", ringSpace_t)
If(inBlockRemain_asPtrSize < sizeByPtrs,
constraingSpace(inBlockRemain_asPtrSize)
).Else(
constraingSpace(sizeByPtrs)
)
constrainedByInBlockRemain = s("constrainedByInBlockRemain")
constrainedByInBlockRemain(fitTo(sizeByPtrs, inBlockRemain) >= inBlockRemain)
If(constraingSpace > BURST_LEN,
# download full burst
req.id(ID),
req.len(BURST_LEN - 1),
If(doReq,
inBlockRemain(inBlockRemain - BURST_LEN)
)
).Elif(constrainedByInBlockRemain & (inBlockRemain < BURST_LEN),
# we know that sizeByPtrs <= inBlockRemain thats why we can resize it
# we will download next* as well
req.id(ID_LAST),
connect(constraingSpace, req.len, fit=True),
If(doReq,
inBlockRemain(self.ITEMS_IN_BLOCK)
)
).Else(
# download data leftover
req.id(ID),
connect(constraingSpace - 1, req.len, fit=True),
If(doReq,
inBlockRemain(inBlockRemain - fitTo(constraingSpace, inBlockRemain))
)
)
# logic of req dispatching
If(downloadPending,
req.vld(0),
If(dataAck & dIn.last,
downloadPending(0)
)
).Else(
req.vld(bufferHasSpace & hasSpace),
If(req.rd & bufferHasSpace & hasSpace,
downloadPending(1)
)
)
# into buffer pushing logic
dBuffIn.data(dIn.data)
isMyData = s("isMyData")
isMyData(dIn.id._eq(ID) | (~dIn.last & dIn.id._eq(ID_LAST)))
If(self.rdPtr.dout.vld,
rdPtr(self.rdPtr.dout.data)
).Else(
If(dIn.valid & downloadPending & dBuffIn.rd & isMyData,
rdPtr(rdPtr + 1)
)
)
# push data into buffer and increment rdPtr
StreamNode(masters=[dIn],
slaves=[dBuffIn],
extraConds={dIn: downloadPending,
dBuffIn: (dIn.id._eq(ID) | (dIn.id._eq(ID_LAST) & ~dIn.last)) & downloadPending
}).sync()
def _impl(self):
propagateClkRstn(self)
ep = self.ep
self.reg.dataIn(self.bus)
ep.bus(self.reg.dataOut)
self.decoded(ep.decoded)
def _impl(self):
propagateClkRstn(self)
self.flipHandler()
self.dataHanldler()
def _impl(self):
propagateClkRstn(self)
dIn = AxiSBuilder(self, self.dataIn).buff().end
sb = self.sizesBuff
db = self.dataBuff
wordCntr = self._reg("wordCntr",
Bits(log2ceil(self.MAX_LEN) + 1),
defVal=0)
overflow = wordCntr._eq(self.MAX_LEN)
last = dIn.last | overflow
If(StreamNode(masters=[dIn], slaves=[sb.dataIn, db.dataIn]).ack(),
If(last,
wordCntr(0)
).Else(
wordCntr(wordCntr + 1)
)
)
length = self._sig("length", wordCntr._dtype)
BYTE_CNT = dIn.data._dtype.bit_length() // 8
if dIn.USE_STRB:
# compress strb mask as binary number
rem = self._sig("rem", Bits(log2ceil(BYTE_CNT)))
SwitchLogic(
cases=[
(dIn.strb[i], rem(0 if i == BYTE_CNT - 1 else i + 1))
for i in reversed(range(BYTE_CNT))],
default=[
rem(0),
]
)
if self.EXPORT_ALIGNMENT_ERROR:
errorAlignment = self._reg("errorAlignment_reg", defVal=0)
self.errorAlignment(errorAlignment)
If(dIn.valid & (dIn.strb != mask(BYTE_CNT)) & ~dIn.last,
errorAlignment(1)
)
If(last & (dIn.strb != mask(BYTE_CNT)),
length(wordCntr)
).Else(
length(wordCntr + 1)
)
else:
length(wordCntr + 1)
rem = vec(0, log2ceil(BYTE_CNT))
sb.dataIn.data(Concat(length, rem))
connect(dIn, db.dataIn, exclude=[dIn.valid, dIn.ready, dIn.last])
db.dataIn.last(last)
StreamNode(masters=[dIn],
slaves=[sb.dataIn, db.dataIn],
extraConds={sb.dataIn: last
}).sync()
self.sizes(sb.dataOut)
connect(db.dataOut, self.dataOut)
def _impl(self):
propagateClkRstn(self)
rErrFlag = self.dataHandler(self.sizeRmFifo.dataOut)
self.addrHandler(self.sizeRmFifo.dataIn, rErrFlag)
def _impl(self):
propagateClkRstn(self)
self.conv.r(self.r)
self.conv.w(self.w)
self.ram.a(self.conv.ram)
def _impl(self):
propagateClkRstn(self)
self.decoded(self.ep.decoded)
self.reg.in_s(self.bus)
self.ep.bus(self.reg.out_m)
def _impl(self):
assert int(self.DRIVER_CNT) > 1, "It makes no sense to use interconnect in this case"
propagateClkRstn(self)
self.reqHandler(self.wDatapump.req, self.orderInfoFifoW.dataIn)
self.wHandler()
self.ackHandler()
def _impl(self):
propagateClkRstn(self)
u = self.subunit0
u.a(self.a0)
self.c0(u.b)
self.b0(u.c)
def _impl(self):
propagateClkRstn(self)
nextBlockTransition = self._sig("nextBlockTransition")
baseIndex, nextBaseIndex, nextBaseReady = self.baseAddrLogic(nextBlockTransition)
self.itemUploadLogic(baseIndex, nextBaseIndex, nextBaseReady, nextBlockTransition)