def runSimWithoutLog(self, until, name=None, config=None):
sim = HdlSimulator()
# dummy config
sim.config = HdlSimConfig()
# run simulation, stimul processes are register after initial
# initialization
sim.simUnit(self.model, until=until, extraProcesses=self.procs)
return sim
def runSimWithoutLog(self, until, name=None, config=None):
sim = HdlSimulator()
# dummy config
sim.config = HdlSimConfig()
# run simulation, stimul processes are register after initial
# initialization
sim.simUnit(self.model, until=until, extraProcesses=self.procs)
return sim
def __serializeTestbenchDump(self, until: float, file):
sim = HdlSimulator()
# configure simulator to log in vcd
sim.config = HdlSimConfigVhdlTestbench(self.u)
# run simulation, stimul processes are register after initial
# initialization
sim.simUnit(self.model, until=until, extraProcesses=self.procs)
sim.config.dump(file)
return sim
def doSim(self, time):
outputFileName = "tmp/" + self.getTestName() + ".vcd"
d = os.path.dirname(outputFileName)
if d:
os.makedirs(d, exist_ok=True)
with open(outputFileName, 'w') as outputFile:
# return _simUnitVcd(simModel, stimulFunctions, outputFile=f, time=time)
sim = HdlSimulator()
# configure simulator to log in vcd
sim.config = VcdHdlSimConfig(outputFile)
# run simulation, stimul processes are register after initial initialization
sim.simUnit(self.model, time=time, extraProcesses=self.procs)
return sim
def _simUnitVcd(simModel, stimulFunctions, outputFile, time):
"""
:param unit: interface level unit to simulate
:param stimulFunctions: iterable of function with single param env (simpy environment)
which are driving the simulation
:param outputFile: file where vcd will be dumped
:param time: endtime of simulation, time units are defined in HdlSimulator
:return: hdl simulator object
"""
sim = HdlSimulator()
# configure simulator to log in vcd
sim.config = VcdHdlSimConfig(outputFile)
# run simulation, stimul processes are register after initial initialization
sim.simUnit(simModel, time=time, extraProcesses=stimulFunctions)
return sim
def dumpHdlTestbench(self, time, file=None):
if file:
outputFileName = file
else:
outputFileName = "tmp/" + self.getTestName() + "_tb.vhd"
d = os.path.dirname(outputFileName)
if d:
os.makedirs(d, exist_ok=True)
with open(outputFileName, 'w') as outputFile:
# return _simUnitVcd(simModel, stimulFunctions, outputFile=f, time=time)
sim = HdlSimulator()
# configure simulator to log in vcd
sim.config = HdlSimConfigVhdlTestbench(self.u)
# run simulation, stimul processes are register after initial initialization
sim.simUnit(self.model, time=time, extraProcesses=self.procs)
sim.config.dump(outputFile)
return sim
def runSim(self, until: float, name=None, config=None):
if name is None:
outputFileName = "tmp/" + self.getTestName() + ".vcd"
else:
outputFileName = name
d = os.path.dirname(outputFileName)
if d:
os.makedirs(d, exist_ok=True)
with open(outputFileName, 'w') as outputFile:
sim = HdlSimulator()
if config is None:
# configure simulator to log in vcd
config = VcdHdlSimConfig(outputFile)
sim.config = config
# run simulation, stimul processes are register after initial
# initialization
sim.simUnit(self.model, until=until, extraProcesses=self.procs)
return sim