def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.dp = Axi_wDatapump(axiCls=Axi4)
self.ic = WStrictOrderInterconnect()
self.ic.ID_WIDTH = 0
self.aw = Axi4_addr()._m()
self.w = Axi4_w()._m()
self.b = Axi4_b()
self.drivers = HObjList(AxiWDatapumpIntf()
for _ in range(int(self.DRIVER_CNT)))
for d in self.drivers:
d.ID_WIDTH = self.ic.ID_WIDTH
def gen_addr_logic(self, addr_ch_in: Axi4_addr, addr_ch_out: Axi4Lite_addr,
req_fifo_inp: HandshakedIdAndLen):
"""
Instanciate logic which splits the transactions to a beats on AxiLite interface
and propagate informations about the transacttions to req_fifo_inp for later use
"""
name_prefix = addr_ch_in._name + "_"
len_rem = self._reg(name_prefix + "len_rem",
addr_ch_in.len._dtype,
def_val=0)
# len_rem_vld is valid only if len > 0 otherwise transaction is processed
# without lem_rem care
len_rem_vld = self._reg(name_prefix + "len_rem_vld", def_val=0)
addr_step = self.DATA_WIDTH // 8
actual_addr = self._reg(name_prefix + "actual_addr",
addr_ch_in.addr._dtype)
If(
len_rem_vld,
addr_ch_out.addr(actual_addr),
addr_ch_in.ready(
0), # because we need to process pending req. first
addr_ch_out.valid(1),
If(
addr_ch_out.ready,
# move on next beat
actual_addr(actual_addr + addr_step),
If(
len_rem._eq(0),
len_rem_vld(0),
),
len_rem(len_rem - 1),
),
).Else(
addr_ch_out.addr(addr_ch_in.addr),
# have to store request to register if it is longer than
# a single beat
actual_addr(addr_ch_out.addr + addr_step),
len_rem(addr_ch_in.len - 1),
len_rem_vld(addr_ch_in.valid & (addr_ch_in.len != 0)
& addr_ch_out.ready & req_fifo_inp.rd),
# directly pass this first beat
StreamNode([addr_ch_in], [addr_ch_out]).sync(req_fifo_inp.rd),
)
addr_ch_out.prot(PROT_DEFAULT)
# push new request to req_fifo only on start of new requirest
req_fifo_inp.vld(~len_rem_vld & addr_ch_in.valid & addr_ch_out.ready)
req_fifo_inp.id(addr_ch_in.id)
req_fifo_inp.len(addr_ch_in.len)
def _declr(self):
Axi4_addr._declr(self)
self.domain = VectSignal(2)
self.region = VectSignal(4)
self.snoop = VectSignal(3)
self.bar = VectSignal(2)
def dispatch_addr(self, id_to_use: RtlSignal, addr: RtlSignal,
a: Axi4_addr):
"""
* if there is a valid item in buffer dispatch read request
"""
a_ld = self._sig("a_ld")
a_tmp = self._reg("ar_tmp",
HStruct(
(a.id._dtype, "id"),
(addr._dtype, "addr"),
(BIT, "vld"),
),
def_val={"vld": 0})
If(a_ld, a_tmp.id(id_to_use), a_tmp.addr(addr),
a_tmp.vld(1)).Else(a_tmp.vld(a_tmp.vld & ~a.ready))
a.id(a_tmp.id)
a.addr(Concat(a_tmp.addr,
Bits(self.CACHE_LINE_OFFSET_BITS).from_py(0)))
a.len(self.BUS_WORDS_IN_CACHE_LINE - 1)
a.burst(BURST_INCR)
a.prot(PROT_DEFAULT)
a.size(BYTES_IN_TRANS(self.DATA_WIDTH // 8))
a.lock(LOCK_DEFAULT)
a.cache(CACHE_DEFAULT)
a.qos(QOS_DEFAULT)
a.valid(a_tmp.vld)
return a_ld
def axiAddrDefaults(self, a: Axi4_addr):
a.burst(BURST_INCR)
a.cache(CACHE_DEFAULT)
a.lock(LOCK_DEFAULT)
a.size(BYTES_IN_TRANS(self.DATA_WIDTH // 8))
a.prot(PROT_DEFAULT)
a.qos(QOS_DEFAULT)
def a_defaults(a: Axi4_addr):
a.id(self.DEFAULT_ID)
a.burst(BURST_INCR)
a.cache(CACHE_DEFAULT)
a.len(0)
a.lock(LOCK_DEFAULT)
a.size(BYTES_IN_TRANS(self.DATA_WIDTH // 8))
if hasattr(a, "qos"):
# axi3/4 difference
a.qos(QOS_DEFAULT)
def _axi_addr_defaults(self, a: Axi4_addr, word_cnt: int):
"""
Set default values for AXI address channel signals
"""
a.len(word_cnt - 1)
a.burst(BURST_INCR)
a.prot(PROT_DEFAULT)
a.size(BYTES_IN_TRANS(self.DATA_WIDTH // 8))
a.lock(LOCK_DEFAULT)
a.cache(CACHE_DEFAULT)
a.qos(QOS_DEFAULT)
def addr_defaults(self, a: Axi4_addr):
axi = self.m
a.id(0)
a.burst(BURST_INCR)
a.cache(CACHE_DEFAULT)
words = ceil(self.S_DATA_WIDTH / axi.DATA_WIDTH)
a.len(words - 1)
a.lock(LOCK_DEFAULT)
a.size(BYTES_IN_TRANS(axi.DATA_WIDTH // 8))
a.prot(PROT_DEFAULT)
if hasattr(a, "qos"):
# axi4
a.qos(QOS_DEFAULT)