def setUpClass(cls):
u = cls.u = Axi_wDatapump(axiCls=Axi3)
u.DATA_WIDTH = u.ALIGNAS = u.CHUNK_WIDTH = cls.DATA_WIDTH
u.MAX_CHUNKS = (cls.DATA_WIDTH // cls.CHUNK_WIDTH) * (cls.LEN_MAX_VAL +
1)
cls.compileSim(u)
def write(
self,
t: HdlType,
id_=0,
tmpl: Optional[TransTmpl] = None,
frames: Optional[List[FrameTmpl]] = None,
):
"""
Rest of the paramters described in :meth:`~.AxiMemRead.read`
"""
axi = self.end
w = StructWriter(t, tmpl=tmpl, frames=frames)
w.ID_WIDTH = 0
w.ADDR_WIDTH = axi.ADDR_WIDTH
w.DATA_WIDTH = axi.DATA_WIDTH
w.USE_STRB = True
setattr(self.parent, self._findSuitableName("wWriter"), w)
self._propagateClkRstn(w)
dp = Axi_wDatapump(axi.__class__)
dp.ADDR_WIDTH = axi.ADDR_WIDTH
dp.ID_WIDTH = axi.ID_WIDTH
dp.DATA_WIDTH = axi.DATA_WIDTH
dp.ID_VAL = id_
dp.MAX_TRANS_OVERLAP = self.max_trans_overlap
dp.ALIGNAS = self.alignas
if isinstance(t, HStream):
raise NotImplementedError()
else:
dp.MAX_CHUNKS = 1
dp.CHUNK_WIDTH = w.wDatapump.MAX_BYTES * 8
setattr(self.parent, self._findSuitableName("wDataPump"), dp)
self._propagateClkRstn(dp)
connectDp(self.parent, w, dp, self.end)
return w.set, w.dataIn, w.writeAck
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.dp = Axi_wDatapump(axiCls=Axi4)
self.ic = WStrictOrderInterconnect()
self.ic.ID_WIDTH = 0
self.aw = Axi4_addr()._m()
self.w = Axi4_w()._m()
self.b = Axi4_b()
self.drivers = HObjList(AxiWDatapumpIntf()
for _ in range(int(self.DRIVER_CNT)))
for d in self.drivers:
d.ID_WIDTH = self.ic.ID_WIDTH
def setUpClass(cls):
cls.u = u = Axi_wDatapump(axiCls=Axi4Lite)
u.MAX_LEN = cls.LEN_MAX_VAL
u.ALIGNAS = 8
cls.compileSim(u)
def setUpClass(cls):
cls.u = u = Axi_wDatapump(axiCls=Axi3Lite)
u.MAX_LEN = cls.LEN_MAX_VAL
cls.compileSim(u)
def setUpClass(cls):
u = Axi_wDatapump(axiCls=Axi3)
u.MAX_LEN = 16
u.ALIGNAS = 8
cls.compileSim(u)
def test_Axi_wDatapump(self):
u = Axi_wDatapump()
convert(u)