def _declr(self) -> None:
self._normalize_config()
addClkRstn(self)
slavePorts = HObjList()
for _ in self.MASTERS:
s = Mi32()
s._updateParamsFrom(self)
slavePorts.append(s)
self.s = slavePorts
masterPorts = HObjList()
for _, size in self.SLAVES:
m = Mi32()._m()
m.ADDR_WIDTH = log2ceil(size - 1)
m.DATA_WIDTH = self.DATA_WIDTH
masterPorts.append(m)
self.m = masterPorts
# fifo which keeps index of slave for master read transaction
# so the interconnect can delivery the read data to master
# which asked for it
f = self.r_data_order = HandshakedFifo(Handshaked)
f.DEPTH = self.MAX_TRANS_OVERLAP
f.DATA_WIDTH = log2ceil(len(self.SLAVES))
def _connect_Mi32AddrHs_to_Mi32(self, mi32ahs: Mi32AddrHs, mi32: Mi32):
return [
mi32(mi32ahs,
exclude={
mi32ahs.vld, mi32ahs.rd, mi32ahs.read, mi32ahs.write,
mi32.ardy, mi32.rd, mi32.wr, mi32.drd, mi32.drdy
}),
mi32.rd(mi32ahs.vld & mi32ahs.read),
mi32.wr(mi32ahs.vld & mi32ahs.write),
mi32ahs.rd(mi32.ardy),
]
def _declr(self):
assert isPow2(self.WINDOW_SIZE), self.WINDOW_SIZE
assert self.M_ADDR_WIDTH > self.ADDR_WIDTH, (self.M_ADDR_WIDTH,
self.ADDR_WIDTH)
assert (2**self.M_ADDR_WIDTH) >= self.WINDOW_SIZE, (
"has to be large enough in order to address whole window",
self.M_ADDR_WIDTH, self.WINDOW_SIZE)
addClkRstn(self)
with self._paramsShared(exclude=({"ADDR_WIDTH"}, {})):
self.m = Mi32()._m()
self.m.ADDR_WIDTH = self.M_ADDR_WIDTH
self.s = Mi32()
self.s.ADDR_WIDTH = self.ADDR_WIDTH
def _Mi32_addr_to_Mi32AddrHs(self, mi32: Mi32, tmp_name):
tmp = Mi32AddrHs()
tmp._updateParamsFrom(mi32)
setattr(self, tmp_name, tmp)
tmp(mi32,
exclude={
tmp.vld, tmp.rd, tmp.read, tmp.write, mi32.ardy, mi32.rd,
mi32.wr, mi32.drd, mi32.drdy
})
tmp.read(mi32.rd)
tmp.write(mi32.wr)
tmp.vld(mi32.rd | mi32.wr)
mi32.ardy(tmp.rd)
return tmp
def __init__(self, mi32: Mi32, parent=None):
super(Mi32SimRam, self).__init__(mi32.DATA_WIDTH // 8, parent=parent)
self.intf = mi32
self.clk = mi32._getAssociatedClk()
self._word_bytes = mi32.DATA_WIDTH // 8
self._word_mask = mask(self._word_bytes)
self._registerOnClock()
def _declr(self):
addClkRstn(self)
with self._paramsShared():
self.s = Mi32()
self.m = Mi32()._m()
def _config(self):
Mi32._config(self)
self.ADDR_BUFF_DEPTH = Param(1)
self.DATA_BUFF_DEPTH = Param(1)
def _config(self):
Mi32._config(self)
def _config(self) -> None:
super(Mi32InterconnectMatrix, self)._config()
Mi32._config(self)
self.MAX_TRANS_OVERLAP = Param(4)
def _declr(self) -> None:
addClkRstn(self)
with self._paramsShared():
self.s = Axi4Lite()
self.m = Mi32()._m()
def _config(self) -> None:
Mi32._config(self)
self.RW_PRIORITY = Param(READ)
def _declr(self):
addClkRstn(self)
self.m = Mi32()._m()
self.s = Mi32()
def _config(self):
Mi32._config(self)
self.M_ADDR_WIDTH = Param(self.ADDR_WIDTH + 1)
self.WINDOW_SIZE = Param(4096)