def test_resources(self):
u = SwitchStmUnit()
expected = {(ResourceMUX, 1, 4): 1}
s = ResourceAnalyzer()
toRtl(u, serializer=s)
r = s.report()
self.assertDictEqual(r, expected)
def test_resources(self):
u = SwitchStmUnit()
expected = {(ResourceMUX, 1, 4): 1}
s = ResourceAnalyzer()
synthesised(u)
s.visit_Unit(u)
r = s.report()
self.assertDictEqual(r, expected)
def test_allCases(self):
self.u = SwitchStmUnit()
self.prepareUnit(self.u)
u = self.u
u.sel._ag.data.extend([0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 0, 1])
u.a._ag.data.extend([0, 1, 0, 0, 0, 0, 0, 0, 1, None, 0])
u.b._ag.data.extend([0, 0, 0, 1, 0, 0, 0, 0, 1, None, 0])
u.c._ag.data.extend([0, 0, 0, 0, 0, 1, 0, 0, 1, None, 0])
self.runSim(110 * Time.ns)
self.assertValSequenceEqual(u.out._ag.data,
[0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0])
def test_systemcSerialization(self):
u = SwitchStmUnit()
s = toRtl(u, serializer=SystemCSerializer)
self.assertEqual(s, switchStm_systemc)
def test_verilogSerialization(self):
u = SwitchStmUnit()
s = toRtl(u, serializer=VerilogSerializer)
self.assertEqual(s, switchStm_verilog)
def test_systemcSerialization(self):
self.assert_serializes_as_file(SwitchStmUnit(), "SwitchStmUnit.cpp")
def test_verilogSerialization(self):
self.assert_serializes_as_file(SwitchStmUnit(), "SwitchStmUnit.v")