def _test_sim_wire(self, DW, test_data):
# build_dir = "tmp"
# if True:
with TemporaryDirectory() as build_dir:
rtl_sim = self.build_sim(build_dir, DW, f"wire{DW:d}")
io = rtl_sim.io
sim = HdlSimulator(rtl_sim)
r_data = []
def data_collect():
for d_ref in test_data:
yield WaitCombRead()
d = io.outp.read()
d = int(d)
r_data.append(d)
self.assertEqual(d, d_ref)
yield Timer(CLK_PERIOD)
def data_feed():
for d in test_data:
yield WaitWriteOnly()
io.inp.write(d)
yield Timer(CLK_PERIOD)
rtl_sim.set_trace_file(join(build_dir, f"wire{DW:d}.vcd"), -1)
sim.run(int(CLK_PERIOD * (len(test_data) + 0.5)),
extraProcesses=[data_collect(),
data_feed()])
self.assertEqual(len(r_data), len(test_data))
def test_sim_cntr(self):
"""
Time synchronized monitors (val) and drivers (clk, rst, en)
"""
# build_dir = "tmp"
# if True:
with TemporaryDirectory() as build_dir:
rtl_sim = self.cntr_build(build_dir)
io = rtl_sim.io
data = []
def data_collector():
yield Timer(CLK_PERIOD // 2)
assert sim.now == CLK_PERIOD // 2
val = io.val
while True:
yield Timer(CLK_PERIOD)
yield WaitCombStable()
data.append((sim.now, int(val.read())))
sim = HdlSimulator(rtl_sim)
# rtl_sim.set_trace_file("cntr.vcd", -1)
procs = [
get_clk_driver(sim, io.clk, CLK_PERIOD),
get_rst_driver(sim, io.rst, CLK_PERIOD),
get_pull_up_driver(sim, io.en, CLK_PERIOD),
data_collector()
]
sim.run(int(CLK_PERIOD * 10.5), extraProcesses=procs)
self.assertSequenceEqual(data, REF_DATA)
def test_sim_cntr_sync_pull_up_reset(self):
"""
Clock dependency on clk
* driver of en
* monitor of val
Simulation step restart due write after reset read
"""
# build_dir = "tmp"
# if True:
with TemporaryDirectory() as build_dir:
rtl_sim = self.cntr_build(build_dir)
io = rtl_sim.io
data = []
sim = HdlSimulator(rtl_sim)
# rtl_sim.set_trace_file(join(build_dir, "cntr.vcd"), -1)
proc = [
get_clk_driver(sim, io.clk, CLK_PERIOD),
get_rst_driver(sim, io.rst, CLK_PERIOD),
get_sync_pull_up_driver_with_reset(sim, io.en, io.clk, io.rst),
get_sync_sig_monitor(sim, io.val, io.clk, io.rst, data)
]
sim.run(int(CLK_PERIOD * 10.5), extraProcesses=proc)
self.assertSequenceEqual(data, REF_DATA)
def test_sim_HandshakedFifo(self):
# build_dir = "tmp"
# if True:
with TemporaryDirectory() as build_dir:
rtl_sim = self.build_handshaked_fifo(build_dir)
io = rtl_sim.io
sim = HdlSimulator(rtl_sim)
def check_if_can_read():
yield WaitCombStable()
assert (len(io.fifo_inst.memory) == 3)
item0 = io.fifo_inst.memory[0]
item0.read()
for i in io.fifo_inst.memory:
i.read()
sim.run(int(CLK_PERIOD * 10.5),
extraProcesses=[check_if_can_read()])
def test_sim_normal_agents(self):
# build_dir = "tmp"
# if True:
with TemporaryDirectory() as build_dir:
rtl_sim = self.cntr_build(build_dir)
io = rtl_sim.io
sim = HdlSimulator(rtl_sim)
data = []
procs = [
*ClockAgent(sim, io.clk).getDrivers(),
*PullDownAgent(sim, io.rst).getDrivers(),
*PullUpAgent(sim, io.en, initDelay=CLK_PERIOD).getDrivers(),
get_sync_sig_monitor(sim, io.val, io.clk, io.rst, data)
]
rtl_sim.set_trace_file(join(build_dir, "cntr.vcd"), -1)
sim.run(int(CLK_PERIOD * 10.5), extraProcesses=procs)
self.assertSequenceEqual(data, REF_DATA)
def build_I2c_wire_with_agents(self, build_dir):
rtl_sim, i, o = self.build_I2c_wire(build_dir)
sim = HdlSimulator(rtl_sim)
i_ag = I2cAgent(sim, i.as_tuple(), (None, False))
o_ag = I2cAgent(sim, o.as_tuple(), (None, False))
procs = [*i_ag.getDrivers(), *o_ag.getMonitors()]
# because the pullup is already on other side of interface
o_ag.sda.pullMode = None
o_ag.scl.pullMode = None
return sim, i_ag, o_ag, procs
def _test_pass_data(self, initFn):
# build_dir = "tmp"
# if True:
with TemporaryDirectory() as build_dir:
rtl_sim = self.hw_build(build_dir)
io = rtl_sim.io
sim = HdlSimulator(rtl_sim)
din_ag, dout_ag = generate_handshaked_agents(
sim, io, io.clk, io.rst_n)
extra_procs = initFn(sim, din_ag, dout_ag)
if extra_procs is None:
extra_procs = []
proc = [
*ClockAgent(sim, io.clk, CLK_PERIOD).getDrivers(),
*PullUpAgent(sim, io.rst_n, CLK_PERIOD).getDrivers(),
*din_ag.getDrivers(),
*dout_ag.getMonitors(),
*extra_procs,
]
sim.run(int(CLK_PERIOD * 20.5), extraProcesses=proc)
return sim, din_ag, dout_ag
def restartSim(self):
"""
Set simulator to initial state and connect it to
:return: tuple (fully loaded unit with connected simulator,
connected simulator,
simulation processes
)
"""
rtl_simulator = self.rtl_simulator_cls()
hdl_simulator = HdlSimulator(rtl_simulator)
unit = self.u
reconnectUnitSignalsToModel(unit, rtl_simulator)
autoAddAgents(unit, hdl_simulator)
self.procs = []
self.u, self.rtl_simulator, self.hdl_simulator = \
unit, rtl_simulator, hdl_simulator
return unit, rtl_simulator, self.procs