def template(): # Create a model container. m = ila.Abstraction('tutorial') # Create/define states in the model. regs = [] for i in xrange(0, 8): regName = 'reg{}'.format(i) regs.append(m.reg(regName, 8)) instr = m.reg('input', 16) out = m.reg('output', 8) # Define next state function. imm = instr[7:0] src1 = ila.choice('src1', regs + [imm]) src2 = ila.choice('src2', regs + [imm]) out_nxt = ila.choice('out', [src1 + src2, src1 * src2]) # Assign the next state function. m.set_next('output', out_nxt) # Define how to decode. m.decode_exprs = [instr[15:8] == i for i in xrange(0, 0x100)] return m
def getSlice(v, lowBits): expr = \ ila.ite( lowBits == 0, ila.choice('lowbits_0',ext(v[7:0]), ext(v[15:0]), ext(v[23:0] ), v[31:0] ), ila.ite( lowBits == 1, ila.choice('lowbits_1' , ext(v[15:8]), ext(v[23:8] ), ext(v[31:8] ) ), ila.ite( lowBits == 2, ila.choice('lowbits_2' , ext(v[23:16]), ext(v[31:16]) ), ila.ite( lowBits == 3, ext(v[31:24]) , v[31:0] )))) return expr
def model(paramsyn): # create the alu. alu = alu_sim() sys = ila.Abstraction("alu") sys.enable_parameterized_synthesis = paramsyn # state elements. rom = sys.mem('rom', alu.ROM_ADDR_WIDTH, alu.OPCODE_WIDTH) pc = sys.reg('pc', alu.ROM_ADDR_WIDTH) opcode = rom[pc] regs = [sys.reg('r%d' % i, alu.REG_SIZE) for i in xrange(alu.NUM_REGS)] # get the two sources. imm = rom[pc + 1] rs = ila.choice('rs', regs) rt = ila.choice('rt', regs + [imm]) results = [rs + rt, rs - rt] # golden model gm_regs_next, pc_next = aluexpr(rom, pc, regs) # set next for PC. sys.set_next('pc', pc_next) # rom never changes. sys.set_next('rom', rom) regs_next = [] for i in xrange(alu.NUM_REGS): ri_next = ila.choice('result%d' % i, results + [regs[i]]) sys.set_next('r%d' % i, ri_next) # set the fetch expressions. sys.fetch_expr = opcode # now set the decode expressions. sys.decode_exprs = [opcode[5:0] == i for i in xrange(alu.NUM_CARE_OPCODES)] # now synthesize. st = time.clock() #sys.synthesize(lambda s: alu.alusim(s)) sys.synthesize(lambda s: alu.alusim(s)) et = time.clock() print '%.3f' % (et - st) for i in xrange(alu.NUM_REGS): rn1 = sys.get_next('r%d' % i) rn2 = gm_regs_next[i] if not sys.areEqual(rn1, rn2): print rn1 print rn2 assert False print rn1 sys.generateVerilog("syn.v")
def dmem_nxt(self): self.st_addr = self.stImm << 0x2 self.store_value = self.sregdest return ila.choice( 'dmem_nxt', [self.dmem, ila.store(self.dmem, self.st_addr, self.store_value)])
def createILA(): m = ila.Abstraction('acc_regs') # input ports cmd = m.inp ('cmd', 2) cmdaddr = m.inp ('cmdaddr', 16) cmddata = m.inp ('cmddata', 8) # arch states state = m.reg ('acc_state', 3) rd_addr = m.reg ('rd_addr', 16) wr_addr = m.reg ('wr_addr', 16) oplen = m.reg ('acc_len', 16) xram = m.mem ('XRAM', 16, 8) # micro-arch states bytes_read = m.reg ('bytes_read', 16) # fetch function and fetch valid function m.fetch_expr = ila.concat ([state, cmd, cmdaddr, cmddata]) m.fetch_valid = (cmd == 1) | (cmd == 2) # state_nxt state_nxt = ila.choice ('state_nxt', [ m.const (0, 3), m.const (1, 3), m.const (2, 3), m.const (3, 3), m.const (4, 3), state]) m.set_next ('acc_state', state_nxt) # NOTE next state functions for rd_addr, wr_addr, oplen and xram is ignore. return m
def synthesize(): rv = riscv() xregs = rv.xregs fregs = rv.fregs pc = rv.pc ram = rv.ram bv = rv.model.const rv.model.fetch_expr = rv.op rv.model.decode_exprs = [rv.op == i for i in xrange(2)] X1_next = ila.choice('x1', [bv(0x1, 64), xregs[0], xregs[2]]) rv.model.set_next('X1', X1_next) rv.model.set_init('X0', bv(0x2, 64)) rv.model.set_next('X0', bv(0x2, 64)) rv.model.set_init('X2', bv(0x0, 64)) rv.model.set_next('X2', bv(0x0, 64)) rv.model.synthesize('X1', sim) synthesized = rv.model.get_next('X1') # expected: (if (or (eq (readmem RAM PC) 0x1) (eq (readmem RAM PC) 0x0)) X2 X1) expected = ila.ite((ram[pc] == 1) | (ram[pc] == 0), xregs[2], xregs[1]) assert rv.model.areEqual(synthesized, expected)
def createmodel(): m = ila.Abstraction('alu') m.enable_parameterized_synthesis = 1 regs = [m.reg('r%d' % i, 8) for i in xrange(4)] opcode = m.inp('opcode', 7) rs_index = opcode[1:0] rt_index = opcode[3:2] rd_index = opcode[5:4] op = opcode[6:6] def sel(regs, idx): return ila.ite( idx == 0, regs[0], ila.ite(idx == 1, regs[1], ila.ite(idx == 2, regs[2], regs[3]))) rs = sel(regs, rs_index) rt = sel(regs, rt_index) res = ila.choice('op', rs + rt, rs - rt) for i in xrange(4): ri_next = ila.ite(rd_index == i, res, regs[i]) m.set_next('r%d' % i, ri_next) m.fetch_expr = opcode m.decode_exprs = [opcode == i for i in xrange(0, 128)] m.synthesize(alusim) for i, di in enumerate(m.decode_exprs): for reg in xrange(4): exp_i = m.get_next('r%d' % reg, i) si = ila.simplify(di, exp_i) if not m.areEqual(di, exp_i, si): print 'decode:', di print 'exp:', exp_i
def get_reg_choices(reg): rs1_val = rm.indexIntoGPR(rm.rs1) rs2_val = rm.indexIntoGPR(rm.rs2) rd_val = rm.indexIntoGPR(rm.rd) rs_val = ila.choice('rs_sel', rs1_val, rs2_val) shamt = ila.choice('shift_amout', rs2_val[4:0], rm.inst[24:20]) rs2_comb = ila.choice('rs2_or_immed', rs2_val, ila.zero_extend(rm.immI, 32), ila.sign_extend(rm.immI, 32)) addr = rs1_val + rm.immI lw_val = ila.load(rm.mem, zext(addr[31:2])) load_val = getSlice(lw_val, addr[1:0]) #load_dw = ila.loadblk(rm.mem, zext(addr[31:2]), 2 ) return ila.choice( "x%d_next" % reg, [ rm.generalRegList[ reg], # Remain the Same regardless of RD (i.e. S/SB instructions) ila.ite( rm.rd == reg, # Is this the destination register? ila.choice( "x%d" % reg, [ rs1_val + rs2_comb, # RS1 + RS2 rs1_val - rs2_comb, # RS1 - RS2 rs1_val & rs2_comb, # AND rs1_val | rs2_comb, # OR rs1_val ^ rs2_comb, # XOR ila.ite( ila.slt(rs1_val, rs2_comb), # SLT bv(1), bv(0)), ila.ite(ila.slt(rs1_val, rs2_comb), bv(0), bv(1)), ila.ite(rs1_val < rs2_comb, bv(1), bv(0)), rs1_val << zext(shamt), # sll rs1_val >> zext(shamt), # srl ila.ashr(rs1_val, zext(shamt)), # sra rm.immU, # LUI rm.immU + rm.pc, # AUIPC rm.pc + bv(4), # JAL/JALR load_val #load_dw ]), rm.generalRegList[reg]) # Remain the same ])
def createIla(): m = ila.Abstraction ('sha') m.enable_parameterized_synthesis = 0 # input ports cmd = m.inp ('cmd', 2) cmdaddr = m.inp ('cmdaddr', 16) cmddata = m.inp ('cmddata', 8) # arch states state = m.reg ('sha_state', 3) rd_addr = m.reg ('sha_rdaddr', 16) wr_addr = m.reg ('sha_wraddr', 16) oplen = m.reg ('sha_len', 16) rd_data = m.reg ('sha_rd_data', 512) hs_data = m.reg ('sha_hs_data', 160) xram = m.mem ('XRAM', 16, 8) sha = m.fun ('sha', 160, [512]) # fetch is just looking at the input command. m.fetch_expr = ila.concat ([state, cmd, cmdaddr, cmddata]) m.fetch_valid = (cmd == 1) | (cmd == 2) # write commands. def mb_reg_wr (name, reg): # multibyte reg write. reg_wr = ila.writechunk ('wr_' + name, reg, cmddata) reg_nxt = ila.choice ('nxt_' + name, [reg_wr, reg]) m.set_next (name, reg_nxt) mb_reg_wr ('sha_rdaddr', rd_addr) mb_reg_wr ('sha_wraddr', wr_addr) mb_reg_wr ('sha_len', oplen) # state (atomic) state_nxt = ila.choice ('state_nxt', [ m.const (0, 3), m.const (1, 3), m.const (2, 3), m.const (3, 3), m.const (4, 3), state]) m.set_next ('sha_state', state_nxt) # xram xram_w_sha_little = ila.storeblk (xram, wr_addr, hs_data) xram_w_sha_big = ila.storeblk_big (xram, wr_addr, hs_data) xram_cho = ila.choice ('xram_nxt', xram, xram_w_sha_little, xram_w_sha_big) xram_nxt = ila.ite ((state == 0) & (cmddata == 1), xram_cho, xram) m.set_next ('XRAM', xram_nxt) return m
def get_mem_choices(): rs1_val = rm.indexIntoGPR(rm.rs1) rs2_val = rm.indexIntoGPR(rm.rs2) mask = ila.choice('store_mask', [bv(0xff), bv(0xffff), bv(0xffffffff)]) addr = rs1_val + rm.immS word_addr = zext(addr[31:2]) store_value = (rs2_val & mask) << (8 * zext(addr[1:0])) | ( (~(mask << (8 * zext(addr[1:0])))) & rm.mem[word_addr]) return ila.choice( "mem_nxt", [ rm.mem, # NC ila.store(rm.mem, word_addr, store_value) ])
def sreg_nxt(self, regNo): return ila.ite( self.dest == regNo, ila.choice( str(regNo) + "_nxt", [ self.sreg1 + self.sreg2, self.sreg1 - self.sreg2, self.sreg1 * self.sreg2, self.sregdest ]), self.scalar_registers[regNo])
def createuBar(self): bar_spec = barSpec() self.bar_state = self.model.reg('bar_state', bar_spec.BAR_STATE_BITS) #self.bar_counter_enter = self.model.reg('bar_counter_enter', bar_spec.BAR_COUNTER_ENTER_BITS) #self.bar_counter_exit = self.model.reg('bar_counter_exit', bar_spec.BAR_COUNTER_EXIT_BITS) #self.bar_state = self.model.getreg('bar_state') #self.bar_counter_enter = self.model.getreg('bar_counter_enter') #self.bar_counter_exit = self.model.getreg('bar_counter_exit') #self.model.set_next('bar_counter_enter', self.bar_counter_enter) #self.model.set_next('bar_counter_exit', self.bar_counter_exit) instruction_map_file = 'instruction_map' instruction_map_obj = open(instruction_map_file, 'r') instruction_map = pickle.load(instruction_map_obj) self.bar_counter_enter = self.model.reg( 'bar_counter_enter', bar_spec.BAR_COUNTER_ENTER_BITS) self.bar_counter_exit = self.model.reg('bar_counter_exit', bar_spec.BAR_COUNTER_EXIT_BITS) #bar_counter_enter = self.model.getreg('bar_counter_enter') #bar_counter_exit = self.model.getreg('bar_counter_exit') self.bar_counter_max = bar_spec.THREAD_NUM # need cleanup #bar_state_next = ila.ite(bar_state == bar_spec.bar_enter, ila.ite(bar_counter_exit != 0, bar_spec.bar_enter, ila.ite(bar_counter_enter == (bar_counter_max - 1), bar_spec.bar_exit, bar_wait)), ila.ite(bar_state == bar_spec.bar_wait, ila.ite(bar_counter_enter == bar_counter_max, bar_spec.bar_exit, bar_spec.bar_wait), ila.ite(bar_state == bar_spec.bar_exit, bar_spec.bar_finish , bar_state))) #bar_counter_enter_next = ila.ite(bar_state == bar_spec.bar_enter, ila.ite(bar_counter_exit != 0, bar_counter_enter, bar_counter_enter + 1), ila.ite((bar_state == bar_spec.bar_exit) & (bar_counter_exit == 1), ila.const(0x0, bar_spec.bar_counter_enter_bits), bar_counter_enter)) #bar_counter_exit_next = ila.ite((bar_state == bar_spec.bar_enter) & (counter_enter == (bar_counter_max - 1)), bar_counter_max, ila.ite(bar_state == bar_spec.bar_exit, bar_counter_exit - 1, bar_counter_exit)) bar_state_next = ila.choice( 'bar_state_next', [ila.const(i, bar_spec.BAR_STATE_BITS) for i in range(0, 5)]) self.bar_counter_enter_next = ila.choice('bar_counter_enter_next', [ self.bar_counter_enter, self.bar_counter_enter + 1, ila.const(0x0, bar_spec.BAR_COUNTER_ENTER_BITS) ]) self.bar_counter_exit_next = ila.choice('bar_counter_exit_next', [ self.bar_counter_exit, self.bar_counter_exit - 1, ila.const(self.bar_counter_max, bar_spec.BAR_COUNTER_EXIT_BITS) ]) self.model.set_next('bar_state', bar_state_next) self.model.set_next('bar_counter_enter', self.bar_counter_enter_next) self.model.set_next('bar_counter_exit', self.bar_counter_exit_next) self.bar_decode_list = [(self.bar_state == bar_spec.BAR_ENTER) & (self.bar_counter_exit != 0),\ (self.bar_state == bar_spec.BAR_ENTER) & (self.bar_counter_exit == 0) & (self.bar_counter_enter == (self.bar_counter_max - 1)),\ (self.bar_state == bar_spec.BAR_ENTER) & (self.bar_counter_exit == 0) & (self.bar_counter_enter != (self.bar_counter_max - 1)),\ (self.bar_state == bar_spec.BAR_WAIT) & (self.bar_counter_enter != self.bar_counter_max),\ (self.bar_state == bar_spec.BAR_WAIT) & (self.bar_counter_enter == self.bar_counter_max),\ (self.bar_state == bar_spec.BAR_EXIT) & (self.bar_counter_exit > 1),\ (self.bar_state == bar_spec.BAR_EXIT) & (self.bar_counter_exit == 1),\ (self.bar_state == bar_spec.BAR_EXIT) & (self.bar_counter_exit == 0)]
def ubar(self): instruction_map_file = 'instruction_map' instruction_map_obj = open(instruction_map_file, 'r') instruction_map = pickle.load(instruction_map_obj) bar_spec = barSpec() self.u_bar_model = self.model.add_microabstraction( 'bar_instruction', ((self.bar_state > bar_spec.BAR_INIT) & (self.bar_state < bar_spec.BAR_FINISH))) self.bar_counter_enter = self.u_bar_model.reg( 'bar_counter_enter', bar_spec.BAR_COUNTER_ENTER_BITS) self.bar_counter_exit = self.u_bar_model.reg( 'bar_counter_exit', bar_spec.BAR_COUNTER_EXIT_BITS) #bar_counter_enter = self.model.getreg('bar_counter_enter') #bar_counter_exit = self.model.getreg('bar_counter_exit') bar_state = self.model.getreg('bar_state') self.bar_counter_max = bar_spec.THREAD_NUM # need cleanup #bar_state_next = ila.ite(bar_state == bar_spec.bar_enter, ila.ite(bar_counter_exit != 0, bar_spec.bar_enter, ila.ite(bar_counter_enter == (bar_counter_max - 1), bar_spec.bar_exit, bar_wait)), ila.ite(bar_state == bar_spec.bar_wait, ila.ite(bar_counter_enter == bar_counter_max, bar_spec.bar_exit, bar_spec.bar_wait), ila.ite(bar_state == bar_spec.bar_exit, bar_spec.bar_finish , bar_state))) #bar_counter_enter_next = ila.ite(bar_state == bar_spec.bar_enter, ila.ite(bar_counter_exit != 0, bar_counter_enter, bar_counter_enter + 1), ila.ite((bar_state == bar_spec.bar_exit) & (bar_counter_exit == 1), ila.const(0x0, bar_spec.bar_counter_enter_bits), bar_counter_enter)) #bar_counter_exit_next = ila.ite((bar_state == bar_spec.bar_enter) & (counter_enter == (bar_counter_max - 1)), bar_counter_max, ila.ite(bar_state == bar_spec.bar_exit, bar_counter_exit - 1, bar_counter_exit)) bar_state_next = ila.choice( 'bar_state_next', [ila.const(i, bar_spec.BAR_STATE_BITS) for i in range(1, 4)]) self.bar_counter_enter_next = ila.choice('bar_counter_enter_next', [ self.bar_counter_enter, self.bar_counter_enter + 1, ila.const(0x0, bar_spec.BAR_COUNTER_ENTER_BITS) ]) self.bar_counter_exit_next = ila.choice('bar_counter_exit_next', [ self.bar_counter_exit, self.bar_counter_exit + 1, ila.const(self.bar_counter_max, bar_spec.BAR_COUNTER_EXIT_BITS) ]) self.u_bar_model.set_next('bar_state', bar_state_next) self.u_bar_model.set_next('bar_counter_enter', self.bar_counter_enter_next) self.u_bar_model.set_next('bar_counter_exit', self.bar_counter_exit_next) bar_decode_list = [(bar_state == bar_spec.BAR_ENTER) & (self.bar_counter_exit != 0),\ (bar_state == bar_spec.BAR_ENTER) & (self.bar_counter_exit == 0) & (self.bar_counter_enter == (self.bar_counter_max - 1)),\ (bar_state == bar_spec.BAR_ENTER) & (self.bar_counter_exit == 0) & (self.bar_counter_enter != (self.bar_counter_max - 1)),\ (bar_state == bar_spec.BAR_WAIT) & (self.bar_counter_enter != self.bar_counter_max),\ (bar_state == bar_spec.BAR_WAIT) & (self.bar_counter_enter == self.bar_counter_max),\ (bar_state == bar_spec.BAR_EXIT) & (self.bar_counter_exit != 1),\ (bar_state == bar_spec.BAR_EXIT) & (self.bar_counter_exit == 1)] self.u_bar_model.decode_exprs = bar_decode_list
def main(): expFile = "tmp/test_ila_export.txt" sys = ila.Abstraction("test") r0 = sys.reg('r0', 8) r1 = sys.reg('r1', 8) a = sys.bit('a') b = sys.bit('b') ex = ila.choice("function", r0 + r1, r0 - r1, r0 + r1 + 1) resfoo = sys.syn_elem("sum", ex, foo) assert sys.areEqual(resfoo, r0 + r1) resbar = sys.syn_elem("diff", ex, bar) assert sys.areEqual(resbar, r0 - r1) a1 = ila.choice("a1", a, ~a, a & b, a | b) b1 = ila.choice("b1", [b, ~b, a & b, a | b, a ^ b]) a2 = ila.choice("a2", a, ~a) b2 = ila.choice("b2", b, ~b) t1 = a1 & b1 t2 = a2 & b2 y = t1 | t2 resbaz = sys.syn_elem("baz", y, baz) assert sys.areEqual(resbaz, a ^ b) resshaz = sys.syn_elem("shaz", y, shaz) assert sys.areEqual(resshaz, ~(a ^ b)) c = ila.inrange("cnst", sys.const(0x00, 8), sys.const(0xff, 8)) z = ila.choice("func_z", r0 + r1 + c, r0 + r1 - c) resdaz = sys.syn_elem("daz", z, daz) assert sys.areEqual(resdaz, r0 + r1 + 0x44) slc0 = ila.readslice("r0slice", r0, 4) slc1 = ila.readslice("r1slice", r1, 4) res = ila.choice('slice', slc0 + slc1, slc0 - slc1) resrmz = sys.syn_elem("razmatazz", res, razmatazz) assert sys.areEqual(resrmz, r0[3:0] + r1[7:4]) sys.exportOne(resrmz, expFile) getback = sys.importOne(expFile) assert sys.areEqual(resrmz, getback) print getback #sys.exportFile(expFile); #sys.importFile(expFile); ila.setloglevel(3, "") ila.enablelog("Export") sys.exportList([resrmz, resdaz], expFile) l = sys.importList(expFile) for ast in l: print ast
def main(): c = ila.Abstraction("test") top = c.bool(True) bot = c.bool(False) x = c.reg('x', 8) y = c.reg('y', 8) g = c.fun('cnst', 8, []) h1 = ila.appfun(g, []) h2 = c.const(40, 8) c.add_assumption((h1 >= 10) & (h1 <= 15)) val = ila.choice('val', h1, h2) res = val + x + y def sim(d): x = d['x'] y = d['y'] d_out = {} d_out['res'] = (x + y + randint(11, 12)) & 0xff return d_out res_s = c.syn_elem('res', res, sim) assert c.areEqual(res_s, h1 + x + y) z = c.reg('z', 16) c0 = c.const(0, 8) c1 = c.const(1, 8) cmax = c.const(255, 8) f = c.fun('foo', 8, [8, 16]) r = ila.appfun(f, x, z) t = ila.appfun(f, y, z) eq = x == y req = r == t assert c.areEqual(ila.implies(eq, req), top) assert c.areEqual(r <= cmax, top) up = c.const(128, 8) down = c.const(120, 16) con = ila.implies((x < up) & (z > down), ila.appfun(f, x, z) > up) test = ila.implies(con & (x == 125) & (z == 125), ila.appfun(f, x, z) > up) assert c.areEqual(test, top) x_next = ila.appfun(f, y, z) c.set_next('x', x_next) exportFile = 'tmp/test_ila_export.txt' c.exportAll(exportFile) c.importAll(exportFile) simFile = 'tmp/test_ila_sim.hpp' c.generateSim(simFile)
def choiceGPRList(self,*arg): # l1[0,1,...,31], l2[0,1,...,31], ... => [0:choice(l1[0],l2[0],...), ... 31:...] # check length for listIter in arg: assert( len(listIter) == 32 ) exprList = [] for idx in range(32): choiceList = [] for listIter in arg: choiceList.append(listIter[idx]) exprList.append( ila.choice('gpr_final_choice_%d'%idx, choiceList) ) return exprList
def sreg_nxt(self, regNo): # self.ssreg1 = ila.ite(self.sreg1_flag, self.sreg1, self.sreg1[(instruction_format.REG_BITS - 1):0]) # self.ssreg2 = ila.ite(self.sreg2_flag, self.sreg2, self.sreg2[(instruction_format.REG_BITS - 1):0]) # self.ssreg3 = ila.ite(self.sreg3_flag, self.sreg3, self.sreg3[(instruction_format.REG_BITS - 1):0]) return ila.ite( self.dest == regNo, ila.choice( str(regNo) + "_nxt", [ self.sreg1 + self.sreg2, self.sreg1 - self.sreg2, self.dmem[self.ldImm << 0x2], self.sreg1, self.sreg1 * self.sreg2, self.scalar_registers[regNo] ]), self.scalar_registers[regNo])
def createILA (): m = ila.Abstraction ('acc_regs') m.enable_parameterized_synthesis = 0 # input ports cmd = m.inp ('cmd', 2) cmdaddr = m.inp ('cmdaddr', 16) cmddata = m.inp ('cmddata', 8) # states state = m.reg ('acc_state', 3) rd_addr = m.reg ('rd_addr', 16) wr_addr = m.reg ('wr_addr', 16) oplen = m.reg ('acc_len', 16) xram = m.mem ('XRAM', 16, 8) # child states bytes_read = m.reg ('bytes_read', 16) # fetch function and fetch valid function m.fetch_expr = state m.fetch_valid = (state == 1) | (state == 2) | (state == 3) | (state == 4) m.add_assumption (oplen > 0) # acc_state RD_nxt = m.const (2, 3) OP1_nxt = m.const (3, 3) OP2_nxt = ila.ite (bytes_read < oplen, m.const (1, 3), m.const (4, 3)) WR_nxt = m.const (0, 3) state_nxt = ila.choice ('state_nxt', [RD_nxt, OP1_nxt, OP2_nxt, WR_nxt]) m.set_next ('acc_state', state_nxt) # bytes_state bytes_read_inc = bytes_read + 1 bytes_read_nxt = ila.choice ('bytes_read_nxt', bytes_read_inc, bytes_read) m.set_next ('bytes_read', bytes_read_nxt) return m
def createuBar(self): bar_spec = barSpec() self.bar_state = self.model.reg('bar_state', bar_spec.BAR_STATE_BITS) #self.bar_counter_enter = self.model.reg('bar_counter_enter', bar_spec.BAR_COUNTER_ENTER_BITS) #self.bar_counter_exit = self.model.reg('bar_counter_exit', bar_spec.BAR_COUNTER_EXIT_BITS) #self.bar_state = self.model.getreg('bar_state') #self.bar_counter_enter = self.model.getreg('bar_counter_enter') #self.bar_counter_exit = self.model.getreg('bar_counter_exit') bar_state_next = ila.choice('bar_state_next', [ ila.const(bar_spec.BAR_INIT, bar_spec.BAR_STATE_BITS), ila.const(bar_spec.BAR_ENTER, bar_spec.BAR_STATE_BITS) ]) self.model.set_next('bar_state', bar_state_next)
def createILA(): m = ila.Abstraction('acc_regs') m.enable_parameterized_synthesis = 0 # input ports cmd = m.inp('cmd', 2) cmdaddr = m.inp('cmdaddr', 16) cmddata = m.inp('cmddata', 8) # arch states state = m.reg('acc_state', 3) rd_addr = m.reg('rd_addr', 16) wr_addr = m.reg('wr_addr', 16) oplen = m.reg('acc_len', 16) xram = m.mem('XRAM', 16, 8) bytes_read = m.reg('bytes_read', 16) # fetch function and fetch valid fuction m.fetch_expr = ila.concat([state, cmd, cmdaddr, cmddata]) m.fetch_valid = (cmd == 1) | (cmd == 2) m.add_assumption(oplen > 0) # acc_state id_nxt = ila.ite(cmddata == 1, m.const(1, 3), m.const(0, 3)) state_nxt = ila.choice('state_nxt', id_nxt, state) m.set_next('acc_state', state_nxt) # bytes_read bytes_read_inc = bytes_read + 1 bytes_read_rst = ila.ite(cmddata == 1, m.const(0, 16), bytes_read) bytes_read_nxt = ila.choice( 'bytes_read_nxt', [m.const(0, 16), bytes_read_inc, bytes_read_rst, bytes_read]) m.set_next('bytes_read', bytes_read_nxt) return m
def lreg_nxt(self, regNo): return ila.ite( self.dest == (regNo + len(self.scalar_registers)), ila.choice( str(regNo) + '_lnxt', [ ila.sign_extend(self.sreg1 + self.sreg2, instruction_format.LONG_REG_BITS), ila.sign_extend(self.sreg1 - self.sreg2, instruction_format.LONG_REG_BITS), ila.sign_extend(self.sreg1 * self.sreg2, instruction_format.LONG_REG_BITS), ila.sign_extend(self.dmem[self.ldImm << 0x2], instruction_format.LONG_REG_BITS), ila.sign_extend(self.sreg1, instruction_format.LONG_REG_BITS), self.long_scalar_registers[regNo] ]), self.long_scalar_registers[regNo])
def main(): sys = ila.Abstraction("test") r0 = sys.reg('r0', 8) r1 = sys.reg('r1', 8) a = sys.bit('a') b = sys.bit('b') ex = ila.choice("function", r0 + r1, r0 - r1, r0 + r1 + 1) resfoo = sys.syn_elem("sum", ex, foo) assert sys.areEqual(resfoo, r0 + r1) resbar = sys.syn_elem("diff", ex, bar) assert sys.areEqual(resbar, r0 - r1) a1 = ila.choice("a1", a, ~a, a & b, a | b) b1 = ila.choice("b1", [b, ~b, a & b, a | b, a ^ b]) a2 = ila.choice("a2", a, ~a) b2 = ila.choice("b2", b, ~b) t1 = a1 & b1 t2 = a2 & b2 y = t1 | t2 resbaz = sys.syn_elem("baz", y, baz) assert sys.areEqual(resbaz, a ^ b) resshaz = sys.syn_elem("shaz", y, shaz) assert sys.areEqual(resshaz, ~(a ^ b)) c = ila.inrange("cnst", sys.const(0x00, 8), sys.const(0xff, 8)) z = ila.choice("func_z", r0 + r1 + c, r0 + r1 - c) resdaz = sys.syn_elem("daz", z, daz) assert sys.areEqual(resdaz, r0 + r1 + 0x44) slc0 = ila.readslice("r0slice", r0, 4) slc1 = ila.readchunk("r1chunk", r1, 4) res = ila.choice('slice', slc0 + slc1, slc0 - slc1) resrmz = sys.syn_elem("razmatazz", res, razmatazz) assert sys.areEqual(resrmz, r0[3:0] + r1[7:4]) nr0 = ila.writeslice("wr0slice", r0, slc0) resjazz = sys.syn_elem("jazz", nr0, jazz) assert sys.areEqual(resjazz, ila.concat(r0[3:0], r0[3:0])) nr1 = ila.writechunk("wr0chunk", r0, slc0) resjazy = sys.syn_elem("jazz", nr1, jazz) assert sys.areEqual(resjazy, ila.concat(r0[3:0], r0[3:0]))
def createPCRILA(synstates): m = ila.Abstraction("sha") inp = m.reg("input", 8) inp1 = m.reg("input1", 8) out = m.reg("output", 8) m.set_next("output", ila.choice("out_choice", [inp, out])) inp_dec = [inp == i for i in range(0, 512)] inp1_dec = [inp1 == i for i in range(0, 512)] out_dec = [out == i for i in range(0, 512)] m.decode_exprs = inp_dec + inp1_dec + out_dec m.synthesize("output", updateFifo) ast = m.get_next("output") m.exportOne(ast, "ast_out")
def get_pc_choices(): rs1_val = rm.indexIntoGPR(rm.rs1) rs2_val = rm.indexIntoGPR(rm.rs2) NC = rm.pc + bv(4) BTarget = rm.pc + rm.immB return ila.choice( "pc_nxt", [ NC, # Next Instruction Address ila.ite(rs1_val == rs2_val, BTarget, NC), ila.ite(rs1_val != rs2_val, BTarget, NC), ila.ite(rs1_val < rs2_val, BTarget, NC), ila.ite(ila.slt(rs1_val, rs2_val), BTarget, NC), ila.ite(rs1_val >= rs2_val, BTarget, NC), ila.ite(ila.sge(rs1_val, rs2_val), BTarget, NC), rm.pc + rm.immJ, # JAL (rs1_val + rm.immI) & bv(0xFFFFFFFE) #JALR ])
def synthesize(): rv = riscv() xregs = rv.xregs fregs = rv.fregs pc = rv.pc ram = rv.ram bv = rv.model.const rv.model.fetch_expr = rv.op rv.model.decode_exprs = [rv.op == i for i in xrange(2)] X1_next = ila.choice('x1', [bv(0x1, 64), xregs[2]]) rv.model.set_next('X1', X1_next) rv.model.add_assumption(xregs[2] == 1) rv.model.synthesize('X1', sim) print rv.model.get_next('X1')
def main(): ila.setloglevel(3, "") ila.enablelog("Z3ExprAdapter") c = ila.Abstraction("test") x = c.bit('x') y = c.bit('y') e1 = (x == y) e2 = ((x & y) | (~x & ~y)) assert c.areEqual(e1, e2) e1p = ~e1 e2p = ~e2 assert c.areEqual(e1p, e2p) assert not c.areEqual(e1p, e2) assert not c.areEqual(e1, e2p) e1 = (x & y) e2 = ~(~x | ~y) assert c.areEqual(e1, e2) assert not c.areEqual(e1, e1p) a = c.reg('a', 8) e1 = -a e2 = ~a + 1 e3 = ~a + 2 e4 = ila.choice("dummy", e2, e1) assert c.areEqual(e1, e2) assert c.areEqual(e1, e4) assert c.areEqual(e2, e4) assert not c.areEqual(e1, e3) assert not c.areEqual(e4, e3) bv1 = c.reg('bv1', 8) bv2 = c.reg('bv2', 8) bv_add1 = bv1 + bv2 bv_add2 = bv2 + bv1 assert c.areEqual(bv_add1, bv_add2)
def bit_reg_wr(name, reg, sz): # bitwise register write assert reg.type.bitwidth == sz reg_wr = cmddata[sz - 1:0] reg_nxt = ila.choice('nxt_' + name, [reg_wr, reg]) m.set_next(name, reg_nxt)
def createAESILA(enable_ps): m = ila.Abstraction("aes") m.enable_parameterized_synthesis = enable_ps # I/O interface: this is where the commands come from. cmd = m.inp('cmd', 2) cmdaddr = m.inp('cmdaddr', 16) cmddata = m.inp('cmddata', 8) # response. dataout = m.reg('dataout', 8) # internal arch state. state = m.reg('aes_state', 2) opaddr = m.reg('aes_addr', 16) oplen = m.reg('aes_len', 16) keysel = m.reg('aes_keysel', 1) ctr = m.reg('aes_ctr', 128) key0 = m.reg('aes_key0', 128) key1 = m.reg('aes_key1', 128) # for the uinst. xram = m.mem('XRAM', 16, 8) aes = m.fun('aes', 128, [128, 128, 128]) # fetch is just looking at the input command. m.fetch_expr = ila.concat([state, cmd, cmdaddr, cmddata]) m.fetch_valid = (cmd == 1) | (cmd == 2) # decode rdcmds = [(state == i) & (cmd == 1) & (cmdaddr == addr) for addr in xrange(0xff00, 0xff40) for i in [0, 1, 2, 3]] wrcmds = [(state == 0) & (cmd == 2) & (cmdaddr == addr) for addr in xrange(0xff00, 0xff40)] nopcmds = [ ((state != 0) & (cmd != 1)) | ((state == 0) & (cmd != 1) & (cmd != 2)) ] m.decode_exprs = rdcmds + wrcmds + nopcmds # read commands statebyte = ila.zero_extend(state, 8) opaddrbyte = ila.readchunk('rd_addr', opaddr, 8) oplenbyte = ila.readchunk('rd_len', oplen, 8) keyselbyte = ila.zero_extend(keysel, 8) ctrbyte = ila.readchunk('rd_ctr', ctr, 8) key0byte = ila.readchunk('rd_key0', key0, 8) key1byte = ila.readchunk('rd_key1', key1, 8) dataoutnext = ila.choice('dataout', [ statebyte, opaddrbyte, oplenbyte, keyselbyte, ctrbyte, key0byte, key1byte, m.const(0, 8) ]) m.set_next('dataout', dataoutnext) # write commands. def mb_reg_wr(name, reg): # multibyte register write. reg_wr = ila.writechunk('wr_' + name, reg, cmddata) reg_nxt = ila.choice('nxt_' + name, [reg_wr, reg]) m.set_next(name, reg_nxt) mb_reg_wr('aes_addr', opaddr) mb_reg_wr('aes_len', oplen) mb_reg_wr('aes_ctr', ctr) mb_reg_wr('aes_key0', key0) mb_reg_wr('aes_key1', key1) # bit-level registers def bit_reg_wr(name, reg, sz): # bitwise register write assert reg.type.bitwidth == sz reg_wr = cmddata[sz - 1:0] reg_nxt = ila.choice('nxt_' + name, [reg_wr, reg]) m.set_next(name, reg_nxt) bit_reg_wr('aes_keysel', keysel, 1) # these are for the uinst um = m.add_microabstraction('aes_compute', state != 0) # read data rd_data = um.reg('rd_data', 128) enc_data = um.reg('enc_data', 128) byte_cnt = um.reg('byte_cnt', 4) oped_byte_cnt = um.reg('oped_byte_cnt', 16) blk_cnt = um.reg('blk_cnt', 16) um.set_init('byte_cnt', um.const(0, 4)) um.set_init('blk_cnt', um.const(0, 16)) um.set_init('oped_byte_cnt', um.const(0, 16)) uxram = m.getmem('XRAM') byte_cnt_16b = ila.zero_extend(byte_cnt, 16) um.fetch_expr = state um.decode_exprs = [(state == i) & (byte_cnt == j) for j in xrange(16) for i in [1, 2, 3]] usim = lambda s: AESmicro().simMicro(s) # byte_cnt byte_cnt_inc = byte_cnt + 1 byte_cnt_buf = ila.choice('byte_cnt_buf', [byte_cnt_inc, byte_cnt]) byte_cnt_nxt = ila.choice( 'byte_cnt_nxt', [byte_cnt_inc, m.const(0, 4), byte_cnt]) um.set_next('byte_cnt', byte_cnt_nxt) # oped_byte_cnt oped_byte_cnt_inc = oped_byte_cnt + 16 oped_byte_cnt_nxt = ila.choice( 'oped_byte_cnt_nxt', [m.const(0, 16), oped_byte_cnt, oped_byte_cnt_inc]) um.set_next('oped_byte_cnt', oped_byte_cnt_nxt) # blk_cnt blk_cnt_inc = blk_cnt + 16 more_blocks = (oped_byte_cnt_inc < oplen) blk_cnt_nxt = ila.choice('blk_cnt_nxt', [ m.const(0, 16), blk_cnt, blk_cnt_inc, ila.ite(more_blocks, blk_cnt_inc, blk_cnt) ]) um.set_next('blk_cnt', blk_cnt_nxt) # ustate ustate = um.getreg('aes_state') ustate_nxt = ila.choice('ustate_next', [ m.const(0, 2), m.const(1, 2), m.const(2, 2), m.const(3, 2), ustate, ila.ite(more_blocks, m.const(1, 2), m.const(0, 2)) ]) um.set_next('aes_state', ustate_nxt) # rd_data rdblock = ila.writechunk("rd_data_chunk", rd_data, ila.load(uxram, opaddr + blk_cnt + byte_cnt_16b)) rd_data_nxt = ila.choice('rd_data_nxt', rdblock, rd_data) um.set_next('rd_data', rd_data_nxt) # enc_data aes_key = ila.ite(keysel == 0, key0, key1) aes_enc_data = ila.appfun(aes, [ctr, aes_key, rd_data]) enc_data_nxt = ila.ite(state == 2, aes_enc_data, enc_data) um.set_next('enc_data', enc_data_nxt) #print um.get_next('enc_data') # xram write xram_w_data = ila.readchunk('enc_data_chunk', enc_data, 8) xram_w_addr = opaddr + blk_cnt + byte_cnt_16b xram_w_aes = ila.store(uxram, xram_w_addr, xram_w_data) xram_nxt = ila.choice('xram_nxt', uxram, xram_w_aes) um.set_next('XRAM', xram_nxt) suffix = 'en' if enable_ps else 'dis' timefile = open('aes-times-%s.txt' % suffix, 'wt') t_elapsed = 0 # micro-synthesis for s in [ 'XRAM', 'aes_state', 'byte_cnt', 'blk_cnt', 'oped_byte_cnt', 'rd_data' ]: t_elapsed = 0 st = time.clock() um.synthesize(s, usim) dt = time.clock() - st t_elapsed += dt print >> timefile, '%s %.2f' % ('u_' + s, dt) print '%s: %s' % (s, str(um.get_next(s))) ast = um.get_next(s) m.exportOne(ast, 'asts/u_%s_%s' % (s, suffix)) sim = lambda s: AESmacro().simMacro(s) # state state_next = ila.choice( 'state_next', [state, ila.ite(cmddata == 1, m.const(1, 2), state)]) m.set_next('aes_state', state_next) # xram m.set_next('XRAM', xram) # synthesize. for s in [ 'aes_state', 'aes_addr', 'aes_len', 'aes_keysel', 'aes_ctr', 'aes_key0', 'aes_key1', 'dataout' ]: st = time.clock() m.synthesize(s, sim) dt = time.clock() - st t_elapsed += dt print >> timefile, '%s %.2f' % (s, dt) ast = m.get_next(s) print '%s: %s' % (s, str(ast)) m.exportOne(ast, 'asts/%s_%s' % (s, suffix)) # connect to the uinst m.connect_microabstraction('aes_state', um) m.connect_microabstraction('XRAM', um) print 'total time: %.2f' % t_elapsed #print 'aes_state: %s' % str(m.get_next('aes_state')) #print 'XRAM: %s' % str(m.get_next('XRAM')) #m.generateSim('gen/aes_sim.hpp') m.generateSimToDir('sim')
def mb_reg_wr(name, reg): # multibyte register write. reg_wr = ila.writechunk('wr_' + name, reg, cmddata) reg_nxt = ila.choice('nxt_' + name, [reg_wr, reg]) m.set_next(name, reg_nxt)
print 'ROM:', rom print 'pc:%08x r0:%08x r1:%08x' % (pc, r0, r1) if opcode == 0: state_out['r0'] = (r0 + r1) elif opcode == 1: state_out['r0'] = (r0 - r1) elif opcode == 2: state_out['r0'] = (r0 + 1) else: state_out['r0'] = (r0 - 1) print 'r0_out:%08x' % state_out['r0'] return state_out ila.setloglevel(0, "") #ila.enablelog("Synthesizer") m = ila.Abstraction('test') regs = [m.reg('r%d' % i, 32) for i in xrange(4)] pc = m.reg('pc', 32) rom = m.mem('rom', 32, 32) m.fetch_expr = rom[pc] m.decode_exprs = [rom[pc] == 0, rom[pc] == 1, rom[pc] == 2, rom[pc] == 3] r0_next = ila.choice( 't1', [regs[0] + regs[1], regs[0] - regs[1], regs[0] + 1, regs[0] - 1]) m.set_next('r0', r0_next) m.synthesize('r0', sim) print m.get_next('r0')