def createCheck(self):
g_st_set_file = 'g_st_set'
g_st_set_obj = open(TMP_DIR + g_st_set_file, 'r')
g_st_set = pickle.load(g_st_set_obj)
g_st_set_obj.close()
s_st_set_file = 's_st_set'
s_st_set_obj = open(TMP_DIR + s_st_set_file, 'r')
s_st_set = pickle.load(s_st_set_obj)
s_st_set_obj.close()
l_st_set_file = 'l_st_set'
l_st_set_obj = open(TMP_DIR + l_st_set_file, 'r')
l_st_set = pickle.load(l_st_set_obj)
l_st_set_obj.close()
g_atom_set_file = 'g_atom_set'
g_atom_set_obj = open(TMP_DIR + g_atom_set_file, 'r')
g_atom_set = pickle.load(g_atom_set_obj)
s_atom_set_file = 's_atom_set'
s_atom_set_obj = open(TMP_DIR + s_atom_set_file, 'r')
s_atom_set = pickle.load(s_atom_set_obj)
self.create_data_race_element(g_st_set, False, ila.const(0x2, 2), 0)
self.create_data_race_element(s_st_set, False, ila.const(0x1, 2), 0)
self.create_data_race_element(l_st_set, False, ila.const(0x0, 2), 0)
self.create_data_race_element(g_atom_set, False, ila.const(0x2, 2), 1)
self.create_data_race_element(s_atom_set, False, ila.const(0x1, 2), 1)
def create_data_race_element(self, access_set, pred_map, log):
if log == True:
suffix = 'log'
index = 0
else:
suffix = 'check'
index = 1
self.log_clean = ila.bool(False)
self.check_clean = ila.bool(False)
for pc in self.bar_list:
bar_pred_list = self.pred_map[pc]
conj_bar_pred = self.pred_gen(index, bar_pred_list)
self.log_clean = self.log_clean | ((self.pc_list[0] == pc) & (conj_bar_pred))
self.check_clean = self.check_clean | ((self.pc_list[0] == pc) & (conj_bar_pred))
for pc in access_set.keys():
reg_name = access_set[pc]
operands = re.split('\+', reg_name)
reg_len = 64
for i in range(len(operands)):
operand = operands[i]
if operand in ptx_declaration.keys():
op_reg_type = ptx_declaration[operand]
op_reg_len = int(op_reg_type[2:])
if op_reg_len < reg_len:
operands[i] = ila.sign_extend(self.model.getreg(operand + '_%d' % (index)), reg_len)
else:
operands[i] = self.model.getreg(operand + '_%d' % (index))
else:
operands[i] = ila.const(int(operand), reg_len)
access_reg_next = operands[0]
for i in range(1, len(operands)):
access_reg_next = access_reg_next + operands[i]
en_access_reg_next = ila.const(0x1, 1)
en_access_reg_clear = ila.const(0x0, 1)
pred_list = self.pred_map[pc]
conj_pred = self.pred_gen(index, pred_list)
#if log:
# self.model.set_next(reg_name + '_en_%s_%d' % (suffix, pc), ila.ite(self.pc_list[index] == pc, en_access_reg_next, ila.ite(self.log_clean, ila.const(0x0, 1), en_access_reg)))
#else:
# self.model.set_next(reg_name + '_en_%s_%d' % (suffix, pc), ila.ite(self.pc_list[index] == pc, en_access_reg_next, ila.ite(self.check_clean, ila.const(0x0, 1), en_access_reg)))
if log:
self.log_register_next = ila.ite((self.pc_list[0] == pc) & (self.arb_list[index] == 1), access_reg_next, self.log_register_next)
self.en_log_register_next = ila.ite((self.pc_list[0] == pc) & (self.arb_list[index] == 1) & (conj_pred), en_access_reg_next, self.en_log_register_next)
#self.log_register_next = ila.ite(self.pc_list[index] == pc, ila.ite(self.arb_list[index] == 1, access_reg_next, self.log_register_next), self.log_register_next)
#self.en_log_register_next = ila.ite(self.pc_list[index] == pc, ila.ite((self.arb_list[index] == 1) & (conj_pred), en_access_reg_next, self.en_log_register_next), self.en_log_register_next)
else:
self.check_register_next = ila.ite((self.pc_list[0] == pc) & (self.arb_list[index] == 1), access_reg_next, self.check_register_next)
self.en_check_register_next = ila.ite((self.pc_list[0] == pc) & (self.arb_list[index] == 1) & (conj_pred), en_access_reg_next, self.en_check_register_next)
#self.check_register_next = ila.ite(self.pc_list[index] == pc, ila.ite(self.arb_list[index] == 1, access_reg_next, self.check_register_next), self.check_register_next)
#self.en_check_register_next = ila.ite(self.pc_list[index] == pc, ila.ite((self.arb_list[index] == 1) & (conj_pred), en_access_reg_next, self.en_check_register_next), self.en_check_register_next)
if log:
self.en_log_register_next = ila.ite(self.log_clean, ila.const(0x0, 1), self.en_log_register_next)
else:
self.en_check_register_next = ila.ite(self.check_clean, ila.const(0x0, 1), self.en_check_register_next)
def assumptions(self): #assumption for st instruction
self.model.add_assumption(self.stImm >= ila.const(
0x0, instruction_format.IMM_BIT_TOP -
instruction_format.IMM_BIT_BOT))
self.model.add_assumption(self.stImm < ila.const(
max_addr_size / 4, instruction_format.IMM_BIT_TOP -
instruction_format.IMM_BIT_BOT))
def createLog(self):
ld_set_file = 'ld_set'
ld_set_obj = open(ld_set_file)
ld_set = pickle.load(ld_set_obj)
ld_set_obj.close()
st_set_file = 'st_set'
st_set_obj = open(st_set_file)
st_set = pickle.load(st_set_obj)
st_set_obj.close()
for pc in ld_set.keys():
reg_name = ld_set[pc]
operands = re.split('\+', reg_name)
reg_len = 64
for i in range(len(operands)):
operand = operands[i]
if operand in ptx_declaration.keys():
op_reg_type = ptx_declaration[operand]
op_reg_len = int(op_reg_type[2:])
if op_reg_len < reg_len:
operands[i] = ila.sign_extend(
self.model.getreg(operand + '_%d' % (0)), reg_len)
else:
operands[i] = self.model.getreg(operand + '_%d' % (0))
else:
operands[i] = ila.const(int(operand), reg_len)
log_reg = self.model.reg(reg_name + '_log_%d' % (pc),
instruction_format.LONG_REG_BITS)
self.log_registers.append(log_reg)
log_reg_next = operands[0]
for i in range(len(operands)):
log_reg_next = log_reg_next + operands[i]
self.model.set_next(
reg_name + '_log_%d' % (pc),
ila.ite(self.pc_list[0] == (pc), log_reg_next, log_reg))
for pc in st_set.keys():
reg_name = st_set[pc]
operands = re.split('\+', reg_name)
reg_len = 64
for i in range(len(operands)):
operand = operands[i]
if operand in ptx_declaration.keys():
op_reg_type = ptx_declaration[operand]
op_reg_len = int(op_reg_type[2:])
if op_reg_len < reg_len:
operands[i] = ila.sign_extend(
self.model.getreg(operand + '_%d' % (0)), reg_len)
else:
operands[i] = self.model.getreg(operand + '_%d' % (0))
else:
operands[i] = ila.const(int(operand), reg_len)
log_reg = self.model.reg(reg_name + '_log_%d' % (pc),
instruction_format.LONG_REG_BITS)
self.log_registers.append(log_reg)
log_reg_next = operands[0]
for i in range(len(operands)):
log_reg_next = log_reg_next + operands[i]
self.model.set_next(
reg_name + '_log_%d' % (pc),
ila.ite(self.pc_list[0] == (pc), log_reg_next, log_reg))
def fulltable(tab):
expr = tab
for i in range(1024):
idx = ila.const(i, 10)
val = ila.const(innerTable[i], 8)
expr = ila.store(expr, idx, val)
return expr
def table_lookup(b,tab, byte0): # modify p
retList = [0,0,0,0]
retList[0] = [ tab[ ila.concat([b[0], ila.const(0,2) ]) ] , tab[ ila.concat([b[0], ila.const(1,2) ]) ], tab[ ila.concat([b[0], ila.const(2,2) ]) ], tab[ ila.concat([b[0], ila.const(3,2) ]) ] ]
retList[1] = [ tab[ ila.concat([b[1], ila.const(0,2) ]) ] , tab[ ila.concat([b[1], ila.const(1,2) ]) ], tab[ ila.concat([b[1], ila.const(2,2) ]) ], tab[ ila.concat([b[1], ila.const(3,2) ]) ] ]
retList[2] = [ tab[ ila.concat([b[2], ila.const(0,2) ]) ] , tab[ ila.concat([b[2], ila.const(1,2) ]) ], tab[ ila.concat([b[2], ila.const(2,2) ]) ], tab[ ila.concat([b[2], ila.const(3,2) ]) ] ]
retList[3] = [ tab[ ila.concat([b[3], ila.const(0,2) ]) ] , tab[ ila.concat([b[3], ila.const(1,2) ]) ], tab[ ila.concat([b[3], ila.const(2,2) ]) ], tab[ ila.concat([b[3], ila.const(3,2) ]) ] ]
return retList
def create_data_race_element(self, access_set, pred_map, log):
if log == True:
suffix = 'log'
index = 0
else:
suffix = 'check'
index = 1
for pc in access_set.keys():
reg_name = access_set[pc]
operands = re.split('\+', reg_name)
reg_len = 64
for i in range(len(operands)):
operand = operands[i]
if operand in ptx_declaration.keys():
op_reg_type = ptx_declaration[operand]
op_reg_len = int(op_reg_type[2:])
if op_reg_len < reg_len:
operands[i] = ila.sign_extend(
self.model.getreg(operand + '_%d' % (index)),
reg_len)
else:
operands[i] = self.model.getreg(operand + '_%d' %
(index))
else:
operands[i] = ila.const(int(operand), reg_len)
access_reg = self.model.reg(reg_name + '_%s_%d' % (suffix, pc),
instruction_format.LONG_REG_BITS)
if log:
self.log_registers.append(access_reg)
else:
self.check_registers.append(access_reg)
access_reg_next = operands[0]
for i in range(1, len(operands)):
access_reg_next = access_reg_next + operands[i]
self.model.set_next(
reg_name + '_%s_%d' % (suffix, pc),
ila.ite(self.pc_list[index] == (pc), access_reg_next,
access_reg))
en_access_reg = self.model.reg(
reg_name + '_en_%s_%d' % (suffix, pc), 1)
if log:
self.en_log_registers.append(en_access_reg)
else:
self.en_check_registers.append(en_access_reg)
en_access_reg_next = ila.const(0x1, 1)
pred_list = pred_map[pc]
for pred in pred_list:
pred_reg = self.model.getreg(pred + '_%d' % (index))
en_access_reg_next = ila.ite(pred_reg == ila.const(0x0, 1),
en_access_reg_next, en_access_reg)
self.model.set_next(
reg_name + '_en_%s_%d' % (suffix, pc),
ila.ite(self.pc_list[index] == pc, en_access_reg_next,
en_access_reg))
def createuBar(self):
bar_spec = barSpec()
self.bar_state = self.model.reg('bar_state', bar_spec.BAR_STATE_BITS)
#self.bar_counter_enter = self.model.reg('bar_counter_enter', bar_spec.BAR_COUNTER_ENTER_BITS)
#self.bar_counter_exit = self.model.reg('bar_counter_exit', bar_spec.BAR_COUNTER_EXIT_BITS)
#self.bar_state = self.model.getreg('bar_state')
#self.bar_counter_enter = self.model.getreg('bar_counter_enter')
#self.bar_counter_exit = self.model.getreg('bar_counter_exit')
bar_state_next = ila.choice('bar_state_next', [
ila.const(bar_spec.BAR_INIT, bar_spec.BAR_STATE_BITS),
ila.const(bar_spec.BAR_ENTER, bar_spec.BAR_STATE_BITS)
])
self.model.set_next('bar_state', bar_state_next)
def perform_instruction(self, index, program_line):
if len(program_line) < 2:
return
opcode = program_line[0]
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
if (opcode_name != '@') and (opcode_name != 'bra'):
self.next_state_finished.append(program_line[1])
if opcode_name == 'bar':
op_len = 0
else:
op_len = int(opcode_split[-1][1:])
src_list = self.aux_generate_src_list(program_line, index, op_len)
dest = self.aux_dest(program_line[0], src_list, index)
if not dest:
self.current_pc += 4
return
dest_str = program_line[1]
dest = self.adjust_dest(index, dest, dest_str, op_len)
self.next_state_dict[dest_str + '_%d' % (index)] = ila.ite(
self.pc_list[index] == self.current_pc, dest,
self.next_state_dict[dest_str + '_%d' % (index)])
self.current_pc += 4
return
else:
if opcode_name == '@':
opcode_pred_name = program_line[1]
opcode_pred = self.model.getreg(opcode_pred_name + '_%d' %
(index))
opcode_jmp_dest = program_line[3]
opcode_jmp_target = self.pc_target[opcode_jmp_dest]
pc_jmp = ila.ite(
opcode_pred == 1,
ila.const(opcode_jmp_target, instruction_format.PC_BITS),
self.pc_list[index] + 4)
self.pc_next_list[index] = ila.ite(
self.pc_list[index] == self.current_pc, pc_jmp,
self.pc_next_list[index])
self.current_pc += 4
else:
opcode_jmp_dest = program_line[1]
opcode_jmp_target = self.pc_target[opcode_jmp_dest]
pc_jmp = ila.const(opcode_jmp_target,
instruction_format.PC_BITS)
self.pc_next_list[index] = ila.ite(
self.pc_list[index] == self.current_pc, pc_jmp,
self.pc_next_list[index])
self.current_pc += 4
def assumptions(self): #assumption for st instruction
instruction_map_file = 'instruction_map'
instruction_map_obj = open(instruction_map_file, 'r')
instruction_map = pickle.load(instruction_map_obj)
self.model.add_assumption(self.stImm >= ila.const(
0x0, instruction_format.IMM_BIT_TOP -
instruction_format.IMM_BIT_BOT))
self.model.add_assumption(self.stImm < ila.const(
max_addr_size / 4, instruction_format.IMM_BIT_TOP -
instruction_format.IMM_BIT_BOT))
#self.model.add_assumption((self.opcode == instruction_map['mul.lo']) | ((self.sreg1_flag == self.scalar_register_flag) & (self.sreg2_flag == self.scalar_register_flag) & (self.sregdest_flag == self.scalar_register_flag)))
self.model.add_assumption(
(self.opcode == instruction_map['mul.wide'])
| ((self.sreg1_flag == self.scalar_register_flag)
& (self.sreg2_flag == self.scalar_register_flag)
& (self.sregdest_flag == self.long_scalar_register_flag)))
def add_assumptions(self):
ptx_declaration_diff_obj = open('diff_read_only_regs', 'r')
ptx_declaration_diff = pickle.load(ptx_declaration_diff_obj)
ptx_declaration_shared_obj = open('shared_read_only_regs', 'r')
ptx_declaration_shared = pickle.load(ptx_declaration_shared_obj)
self.init = ila.bool(True)
for index in range(self.thread_num):
pc = self.model.getreg('pc_%d' % (index))
self.init = self.init & (pc == self.model.const(
0x0, instruction_format.PC_BITS))
i = 1
for reg_name in ptx_declaration_shared:
reg0 = self.model.getreg(reg_name + '_%d' % (0))
reg1 = self.model.getreg(reg_name + '_%d' % (1))
self.init = self.init & (reg0 == reg1)
self.init_max = self.model.const(
i, instruction_format.LONG_REG_BITS) << 59
self.init_range = self.model.const(
1, instruction_format.LONG_REG_BITS) << 58
self.init = self.init & (reg0 < self.init_max) & (
reg0 > (self.init_max - self.init_range))
i += 1
for reg in ptx_declaration_diff:
reg0 = self.model.getreg(reg + '_%d' % (0))
reg1 = self.model.getreg(reg + '_%d' % (1))
self.init = self.init & (reg0 != reg1) & (reg0 <= 128) & (
reg0 >= 0) & (reg1 <= 128) & (reg1 >= 0)
self.init = self.init & (self.en_log_register
== 0) & (self.en_check_register == 0)
bar_pred_map_obj = open('bar_pred_map', 'r')
bar_pred_map = pickle.load(bar_pred_map_obj)
bar_pred_map_obj.close()
self.check_point = ila.bool(False)
for pc in self.bar_list:
bar_pred_list = bar_pred_map[pc]
bar_pred = ila.bool(True)
for bar_pred_name in bar_pred_list:
bar_pred_reg = self.model.getreg(bar_pred_name + '_%d' % (0))
bar_pred = bar_pred & (bar_pred_reg == ila.const(0x0, 1))
#self.condition = []
#for index in range(self.thread_num):
# self.condition.append(self.pc_list[index] >= (self.pc_max))
#self.constrain = self.condition[0]
#for index in range(1, len(self.condition)):
# self.constrain = self.constrain & self.condition[index]
self.imply = (self.check_register == self.log_register) & (
self.en_log_register == 1) & (self.en_check_register == 1)
# self.implied = self.implied & (self.mem_list[0] == self.mem_list[1])
self.predicate_bit = self.model.bit('predicate_bit')
#self.model.set_init('predicate_bit', self.model.bool(True))
self.init = self.init & (self.predicate_bit == self.model.bool(True))
self.model.set_next(
'predicate_bit',
ila.ite(self.imply, self.model.bool(False), self.predicate_bit))
def createCheck(self):
st_set_file = 'st_set'
st_set_obj = open(st_set_file, 'r')
st_set = pickle.load(st_set_obj)
st_set_obj.close()
pred_map_file = 'pred_map'
pred_map_obj = open(pred_map_file, 'r')
pred_map = pickle.load(pred_map_obj)
pred_map_obj.close()
for pc in st_set.keys():
reg_name = st_set[pc]
operands = re.split('\+', reg_name)
reg_len = 64
for i in range(len(operands)):
operand = operands[i]
if operand in ptx_declaration.keys():
op_reg_type = ptx_declaration[operand]
op_reg_len = int(op_reg_type[2:])
if op_reg_len < reg_len:
operands[i] = ila.sign_extend(
self.model.getreg(operand + '_%d' % (1)), reg_len)
else:
operands[i] = self.model.getreg(operand + '_%d' % (1))
else:
operands[i] = ila.const(int(operand), reg_len)
check_reg = self.model.reg(reg_name + '_check_%d' % (pc),
instruction_format.LONG_REG_BITS)
self.check_registers.append(check_reg)
check_reg_next = operands[0]
for i in range(1, len(operands)):
check_reg_next = check_reg_next + operands[i]
self.model.set_next(
reg_name + '_check_%d' % (pc),
ila.ite(self.pc_list[1] == (pc), check_reg_next, check_reg))
en_check_reg = self.model.reg(reg_name + '_en_check_%d' % (pc), 1)
self.en_check_registers.append(en_check_reg)
en_check_reg_next = ila.const(0x1, 1)
pred_list = pred_map[pc]
for pred in pred_list:
pred_reg = self.model.getreg(pred + '_%d' % (1))
en_check_reg_next = ila.ite(pred_reg == ila.const(0x0, 1),
en_check_reg_next, en_check_reg)
self.model.set_next(
reg_name + '_en_check_%d' % (pc),
ila.ite(self.pc_list[1] == (pc), en_check_reg_next,
en_check_reg))
def createuBar(self):
bar_spec = barSpec()
self.bar_state = self.model.reg('bar_state', bar_spec.BAR_STATE_BITS)
#self.bar_counter_enter = self.model.reg('bar_counter_enter', bar_spec.BAR_COUNTER_ENTER_BITS)
#self.bar_counter_exit = self.model.reg('bar_counter_exit', bar_spec.BAR_COUNTER_EXIT_BITS)
#self.bar_state = self.model.getreg('bar_state')
#self.bar_counter_enter = self.model.getreg('bar_counter_enter')
#self.bar_counter_exit = self.model.getreg('bar_counter_exit')
#self.model.set_next('bar_counter_enter', self.bar_counter_enter)
#self.model.set_next('bar_counter_exit', self.bar_counter_exit)
instruction_map_file = 'instruction_map'
instruction_map_obj = open(instruction_map_file, 'r')
instruction_map = pickle.load(instruction_map_obj)
self.bar_counter_enter = self.model.reg(
'bar_counter_enter', bar_spec.BAR_COUNTER_ENTER_BITS)
self.bar_counter_exit = self.model.reg('bar_counter_exit',
bar_spec.BAR_COUNTER_EXIT_BITS)
#bar_counter_enter = self.model.getreg('bar_counter_enter')
#bar_counter_exit = self.model.getreg('bar_counter_exit')
self.bar_counter_max = bar_spec.THREAD_NUM # need cleanup
#bar_state_next = ila.ite(bar_state == bar_spec.bar_enter, ila.ite(bar_counter_exit != 0, bar_spec.bar_enter, ila.ite(bar_counter_enter == (bar_counter_max - 1), bar_spec.bar_exit, bar_wait)), ila.ite(bar_state == bar_spec.bar_wait, ila.ite(bar_counter_enter == bar_counter_max, bar_spec.bar_exit, bar_spec.bar_wait), ila.ite(bar_state == bar_spec.bar_exit, bar_spec.bar_finish , bar_state)))
#bar_counter_enter_next = ila.ite(bar_state == bar_spec.bar_enter, ila.ite(bar_counter_exit != 0, bar_counter_enter, bar_counter_enter + 1), ila.ite((bar_state == bar_spec.bar_exit) & (bar_counter_exit == 1), ila.const(0x0, bar_spec.bar_counter_enter_bits), bar_counter_enter))
#bar_counter_exit_next = ila.ite((bar_state == bar_spec.bar_enter) & (counter_enter == (bar_counter_max - 1)), bar_counter_max, ila.ite(bar_state == bar_spec.bar_exit, bar_counter_exit - 1, bar_counter_exit))
bar_state_next = ila.choice(
'bar_state_next',
[ila.const(i, bar_spec.BAR_STATE_BITS) for i in range(0, 5)])
self.bar_counter_enter_next = ila.choice('bar_counter_enter_next', [
self.bar_counter_enter, self.bar_counter_enter + 1,
ila.const(0x0, bar_spec.BAR_COUNTER_ENTER_BITS)
])
self.bar_counter_exit_next = ila.choice('bar_counter_exit_next', [
self.bar_counter_exit, self.bar_counter_exit - 1,
ila.const(self.bar_counter_max, bar_spec.BAR_COUNTER_EXIT_BITS)
])
self.model.set_next('bar_state', bar_state_next)
self.model.set_next('bar_counter_enter', self.bar_counter_enter_next)
self.model.set_next('bar_counter_exit', self.bar_counter_exit_next)
self.bar_decode_list = [(self.bar_state == bar_spec.BAR_ENTER) & (self.bar_counter_exit != 0),\
(self.bar_state == bar_spec.BAR_ENTER) & (self.bar_counter_exit == 0) & (self.bar_counter_enter == (self.bar_counter_max - 1)),\
(self.bar_state == bar_spec.BAR_ENTER) & (self.bar_counter_exit == 0) & (self.bar_counter_enter != (self.bar_counter_max - 1)),\
(self.bar_state == bar_spec.BAR_WAIT) & (self.bar_counter_enter != self.bar_counter_max),\
(self.bar_state == bar_spec.BAR_WAIT) & (self.bar_counter_enter == self.bar_counter_max),\
(self.bar_state == bar_spec.BAR_EXIT) & (self.bar_counter_exit > 1),\
(self.bar_state == bar_spec.BAR_EXIT) & (self.bar_counter_exit == 1),\
(self.bar_state == bar_spec.BAR_EXIT) & (self.bar_counter_exit == 0)]
def createLog(self):
s_ld_set_file = 's_ld_set'
s_ld_set_obj = open(TMP_DIR + s_ld_set_file, 'r')
s_ld_set = pickle.load(s_ld_set_obj)
s_ld_set_obj.close()
g_ld_set_file = 'g_ld_set'
g_ld_set_obj = open(TMP_DIR + g_ld_set_file, 'r')
g_ld_set = pickle.load(g_ld_set_obj)
g_ld_set_obj.close()
l_ld_set_file = 'l_ld_set'
l_ld_set_obj = open(TMP_DIR + l_ld_set_file, 'r')
l_ld_set = pickle.load(l_ld_set_obj)
l_ld_set_obj.close()
g_atom_set_file = 'g_atom_set'
g_atom_set_obj = open(TMP_DIR + g_atom_set_file, 'r')
g_atom_set = pickle.load(g_atom_set_obj)
s_atom_set_file = 's_atom_set'
s_atom_set_obj = open(TMP_DIR + s_atom_set_file, 'r')
s_atom_set = pickle.load(s_atom_set_obj)
g_st_set_file = 'g_st_set'
g_st_set_obj = open(TMP_DIR + g_st_set_file, 'r')
g_st_set = pickle.load(g_st_set_obj)
g_st_set_obj.close()
s_st_set_file = 's_st_set'
s_st_set_obj = open(TMP_DIR + s_st_set_file, 'r')
s_st_set = pickle.load(s_st_set_obj)
s_st_set_obj.close()
l_st_set_file = 'l_st_set'
l_st_set_obj = open(TMP_DIR + l_st_set_file, 'r')
l_st_set = pickle.load(l_st_set_obj)
l_st_set_obj.close()
for pc in g_st_set.keys():
g_ld_set[pc] = g_st_set[pc]
for pc in s_st_set.keys():
s_ld_set[pc] = s_st_set[pc]
for pc in l_st_set.keys():
l_ld_set[pc] = l_st_set[pc]
self.create_data_race_element(g_ld_set, True, ila.const(0x2, 2), 0)
self.create_data_race_element(s_ld_set, True, ila.const(0x1, 2), 0)
self.create_data_race_element(l_ld_set, True, ila.const(0x0, 2), 0)
self.create_data_race_element(g_atom_set, True, ila.const(0x2, 2), 1)
self.create_data_race_element(s_atom_set, True, ila.const(0x1, 2), 1)
def perform_instruction(self, index, program_line, pc_target):
if len(program_line) < 2:
return
opcode = program_line[0]
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
if opcode_name != '@':
self.next_state_finished.append(program_line[1])
conj_pred = self.pred_gen(index, self.pred_map[self.current_pc])
if opcode_name == 'bar':
op_len = 0
else:
op_len = int(opcode_split[-1][1:])
src_list = []
for i in range(2, len(program_line)):
src_str = program_line[i]
src_components = re.split('\+', src_str)
for i in range(len(src_components)):
src_component = src_components[i]
src_components[i] = self.aux_imm(src_component, index,
op_len)
src_sum = src_components[0]
for i in range(1, len(src_components)):
src_sum = src_sum + src_components[0]
src_list.append(src_sum)
dest = self.aux_dest(program_line[0], src_list, index)
if not dest:
self.current_pc += 4
return
dest_str = program_line[1]
dest = self.adjust_dest(index, dest, dest_str, op_len)
current_next_state = self.next_state_dict[dest_str + '_%d' %
(index)]
self.next_state_dict[dest_str + '_%d' % (index)] = ila.ite(
self.pc_list[index] == self.current_pc,
ila.ite(conj_pred, dest, current_next_state),
current_next_state)
self.current_pc += 4
return
else:
conj_pred0 = self.pred_gen(0, self.pred_map[self.current_pc])
conj_pred1 = self.pred_gen(1, self.pred_map[self.current_pc])
opcode_jmp_dest = program_line[3]
opcode_jmp_target = pc_target[opcode_jmp_dest]
if (opcode_jmp_target > self.current_pc):
opcode_pred = conj_pred0 & conj_pred1
else:
opcode_pred = conj_pred0 | conj_pred1
pc_jmp = ila.ite(
opcode_pred,
ila.const(opcode_jmp_target, instruction_format.PC_BITS),
self.pc_list[index] + 4)
self.pc_next_list[index] = ila.ite(
self.pc_list[index] == self.current_pc, pc_jmp,
self.pc_next_list[index])
self.current_pc += 4
def ubar(self):
instruction_map_file = 'instruction_map'
instruction_map_obj = open(instruction_map_file, 'r')
instruction_map = pickle.load(instruction_map_obj)
bar_spec = barSpec()
self.u_bar_model = self.model.add_microabstraction(
'bar_instruction', ((self.bar_state > bar_spec.BAR_INIT) &
(self.bar_state < bar_spec.BAR_FINISH)))
self.bar_counter_enter = self.u_bar_model.reg(
'bar_counter_enter', bar_spec.BAR_COUNTER_ENTER_BITS)
self.bar_counter_exit = self.u_bar_model.reg(
'bar_counter_exit', bar_spec.BAR_COUNTER_EXIT_BITS)
#bar_counter_enter = self.model.getreg('bar_counter_enter')
#bar_counter_exit = self.model.getreg('bar_counter_exit')
bar_state = self.model.getreg('bar_state')
self.bar_counter_max = bar_spec.THREAD_NUM # need cleanup
#bar_state_next = ila.ite(bar_state == bar_spec.bar_enter, ila.ite(bar_counter_exit != 0, bar_spec.bar_enter, ila.ite(bar_counter_enter == (bar_counter_max - 1), bar_spec.bar_exit, bar_wait)), ila.ite(bar_state == bar_spec.bar_wait, ila.ite(bar_counter_enter == bar_counter_max, bar_spec.bar_exit, bar_spec.bar_wait), ila.ite(bar_state == bar_spec.bar_exit, bar_spec.bar_finish , bar_state)))
#bar_counter_enter_next = ila.ite(bar_state == bar_spec.bar_enter, ila.ite(bar_counter_exit != 0, bar_counter_enter, bar_counter_enter + 1), ila.ite((bar_state == bar_spec.bar_exit) & (bar_counter_exit == 1), ila.const(0x0, bar_spec.bar_counter_enter_bits), bar_counter_enter))
#bar_counter_exit_next = ila.ite((bar_state == bar_spec.bar_enter) & (counter_enter == (bar_counter_max - 1)), bar_counter_max, ila.ite(bar_state == bar_spec.bar_exit, bar_counter_exit - 1, bar_counter_exit))
bar_state_next = ila.choice(
'bar_state_next',
[ila.const(i, bar_spec.BAR_STATE_BITS) for i in range(1, 4)])
self.bar_counter_enter_next = ila.choice('bar_counter_enter_next', [
self.bar_counter_enter, self.bar_counter_enter + 1,
ila.const(0x0, bar_spec.BAR_COUNTER_ENTER_BITS)
])
self.bar_counter_exit_next = ila.choice('bar_counter_exit_next', [
self.bar_counter_exit, self.bar_counter_exit + 1,
ila.const(self.bar_counter_max, bar_spec.BAR_COUNTER_EXIT_BITS)
])
self.u_bar_model.set_next('bar_state', bar_state_next)
self.u_bar_model.set_next('bar_counter_enter',
self.bar_counter_enter_next)
self.u_bar_model.set_next('bar_counter_exit',
self.bar_counter_exit_next)
bar_decode_list = [(bar_state == bar_spec.BAR_ENTER) & (self.bar_counter_exit != 0),\
(bar_state == bar_spec.BAR_ENTER) & (self.bar_counter_exit == 0) & (self.bar_counter_enter == (self.bar_counter_max - 1)),\
(bar_state == bar_spec.BAR_ENTER) & (self.bar_counter_exit == 0) & (self.bar_counter_enter != (self.bar_counter_max - 1)),\
(bar_state == bar_spec.BAR_WAIT) & (self.bar_counter_enter != self.bar_counter_max),\
(bar_state == bar_spec.BAR_WAIT) & (self.bar_counter_enter == self.bar_counter_max),\
(bar_state == bar_spec.BAR_EXIT) & (self.bar_counter_exit != 1),\
(bar_state == bar_spec.BAR_EXIT) & (self.bar_counter_exit == 1)]
self.u_bar_model.decode_exprs = bar_decode_list
def buildTemplateVR1(aes):
#
key0 = aes.getreg('in_key0')
key1 = aes.getreg('in_key1')
key2 = aes.getreg('in_key2')
key3 = aes.getreg('in_key3')
state0 = aes.getreg('state0')
state1 = aes.getreg('state1')
state2 = aes.getreg('state2')
state3 = aes.getreg('state3')
debug = aes.reg('vdb', 32)
def _print(n):
aes.set_next('vdb', n)
i = aes.getreg('i')
rsT = aes.reg('encr1', 128)
rsK = aes.reg('keyr1', 128)
#vtable = aes.mem('vtable', 8, 8)
#tab = fulltable(vtable)
tab = None
# assuming the above are given in little-endian
[state0, state1, state2,
state3] = [state0 ^ key0, state1 ^ key1, state2 ^ key2,
state3 ^ key3] # pre-round
k0t = Lto128([key0, key1, key2, key3])
# inside one round
[k0, k1, k2, k3] = expand_key_128(k0t, ila.const(1, 8), tab)
[p00, p01, p02, p03] = table_lookup(state0, tab)
[p10, p11, p12, p13] = table_lookup(state1, tab)
[p20, p21, p22, p23] = table_lookup(state2, tab)
tab = _print
[p30, p31, p32, p33] = table_lookup(state3, tab)
tab = None
z0 = p00 ^ p11 ^ p22 ^ p33 ^ k0
z1 = p03 ^ p10 ^ p21 ^ p32 ^ k1
z2 = p02 ^ p13 ^ p20 ^ p31 ^ k2
z3 = p01 ^ p12 ^ p23 ^ p30 ^ k3
_print(z3)
state_out = cat([z0, z1, z2, z3])
aes.set_next('encr1', state_out)
aes.set_next('keyr1', cat([k0, k1, k2, k3]))
return aes
def createRegs(self):
self.scalar_registers_a = []
self.scalar_registers_b = []
reg_book_obj = open(ptxILA.reg_book_file)
reg_book = pickle.load(reg_book_obj)
reg_book.remove('bar_state')
reg_book.remove('bar_counter_enter')
reg_book.remove('bar_counter_exit')
'''
for reg_name in reg_book:
self.scalar_registers_a.append(self.model.reg(reg_name + '_a', instruction_format.REG_BITS))
self.scalar_registers_b.append(self.model.reg(reg_name + '_b', instruction_format.REG_BITS))
'''
self.arb_fun = self.model.fun('arb_fun', 1, [])
self.arb = self.model.reg('arb', 1)
self.model.set_next('arb', ila.appfun(self.arb_fun,
[])) #Non-determined value
self.arbA = ila.const(0x0, 1)
self.arbB = ila.const(0x1, 1)
self.model.set_init('arb', self.model.const(0x0, 1))
def get_next_pc(self, index):
current_pc = self.pc_list[index]
seq_next = current_pc + 4
bar_stopped = ~((ila.is_bar_list[0]) & (ila.is_bar_list[1]))
bar_next = ila.ite(bar_stopped, current_pc, current_pc + 4)
bra_next = ila.sign_extend(self.imm_list[index],
instruction_format.PC_BITS)
pred_reg = self.get_pred_registers(self.pred_reg_list[index], index)
pc_next = ila.ite(
self.is_bra_list[index],
ila.ite(
self.pred_enable_list[index] == 0, bra_next,
ila.ite(
self.pred_enable_list[index] == 1,
ila.ite(pred_reg == ila.const(0x1, 1), bra_next, seq_next),
ila.ite(
self.pred_enable_list[index] == 2,
ila.ite(pred_reg == ila.const(0x1, 1), seq_next,
bra_next)))),
ila.ite(self.is_bar_list[index], bar_next,
ila.ite(current_pc >= max_pc, current_pc, seq_next)))
self.model.set_next('pc_%d' % (index), pc_next)
def createBar(self):
self.bar_state_next_list = []
self.bar_counter_enter_next_list = []
self.bar_counter_exit_next_list = []
self.bar_counter_max = self.thread_num
for i in range(self.thread_num):
self.bar_state_next_list.append(ila.ite(self.bar_arb == i, ila.ite(self.bar_inst[i] == ila.bool(True), ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_FINISH, ila.const(self.bar_spec.BAR_INIT, self.bar_spec.BAR_STATE_BITS),\
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_INIT, ila.const(self.bar_spec.BAR_ENTER, self.bar_spec.BAR_STATE_BITS),\
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_ENTER, ila.ite(self.bar_counter_exit != 0, self.bar_state_list[i],\
ila.ite(self.bar_counter_enter == (self.bar_counter_max - 1), ila.const(self.bar_spec.BAR_EXIT, self.bar_spec.BAR_STATE_BITS), ila.const(self.bar_spec.BAR_WAIT, self.bar_spec.BAR_STATE_BITS))),\
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_WAIT, ila.ite(self.bar_counter_enter == self.bar_counter_max, ila.const(self.bar_spec.BAR_EXIT, self.bar_spec.BAR_STATE_BITS), self.bar_state_list[i]),\
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_EXIT, ila.const(self.bar_spec.BAR_FINISH, self.bar_spec.BAR_STATE_BITS), self.bar_state_list[i]))))), self.bar_state_list[i]), self.bar_state_list[i]))
self.bar_counter_enter_next_list.append(ila.ite(self.bar_inst[i] == ila.bool(True), \
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_INIT, self.bar_counter_enter, \
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_FINISH, self.bar_counter_enter,\
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_ENTER, ila.ite(self.bar_counter_exit == 0, self.bar_counter_enter + 1, self.bar_counter_enter),\
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_WAIT, self.bar_counter_enter, \
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_EXIT, ila.ite(self.bar_counter_exit == 1, ila.const(0x0, self.bar_spec.BAR_COUNTER_ENTER_BITS), self.bar_counter_enter), self.bar_counter_enter))))), \
self.bar_counter_enter))
self.bar_counter_exit_next_list.append(ila.ite(self.bar_inst[i] == ila.bool(True),\
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_INIT, self.bar_counter_exit,\
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_FINISH, self.bar_counter_exit,\
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_ENTER, ila.ite(self.bar_counter_exit == 0, ila.ite(self.bar_counter_enter == (self.bar_counter_max - 1), ila.const(self.bar_counter_max, self.bar_spec.BAR_COUNTER_EXIT_BITS), self.bar_counter_exit), self.bar_counter_exit),\
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_WAIT, self.bar_counter_exit,\
ila.ite(self.bar_state_list[i] == self.bar_spec.BAR_EXIT, ila.ite(self.bar_counter_exit != 0, self.bar_counter_exit - 1, self.bar_counter_exit - 1), self.bar_counter_exit))))),\
self.bar_counter_exit))
self.bar_counter_enter_next = self.bar_counter_enter
self.bar_counter_exit_next = self.bar_counter_exit
for i in range(self.thread_num):
self.bar_counter_enter_next = ila.ite(
self.bar_arb == i, self.bar_counter_enter_next_list[i],
self.bar_counter_enter_next)
self.bar_counter_exit_next = ila.ite(
self.bar_arb == i, self.bar_counter_exit_next_list[i],
self.bar_counter_exit_next)
def perform_instruction(self, index, program_line, pc_target):
if len(program_line) < 2:
return
opcode = program_line[0]
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
if opcode_name != '@':
self.next_state_finished.append(program_line[1])
op_len = int(opcode_split[-1][1:])
src_list = []
for i in range(2, len(program_line)):
src_str = program_line[i]
src_components = re.split('\+', src_str)
for i in range(len(src_components)):
src_component = src_components[i]
src_components[i] = self.aux_imm(src_component, index,
op_len)
src_sum = src_components[0]
for i in range(1, len(src_components)):
src_sum = src_sum + src_components[0]
src_list.append(src_sum)
dest = self.aux_dest(program_line[0], src_list)
if not dest:
self.current_pc += 4
return
dest_str = program_line[1]
dest = self.adjust_dest(index, dest, dest_str, op_len)
self.next_state_dict[dest_str + '_%d' % (index)] = ila.ite(
self.pc_list[index] == self.current_pc, dest,
self.next_state_dict[dest_str + '_%d' % (index)])
self.current_pc += 4
return
else:
opcode_pred_name = program_line[1]
opcode_pred = self.model.getreg(opcode_pred_name + '_%d' % (index))
opcode_jmp_dest = program_line[3]
opcode_jmp_target = pc_target[opcode_jmp_dest]
pc_jmp = ila.ite(
opcode_pred == 1,
ila.const(opcode_jmp_target, instruction_format.PC_BITS),
self.pc_list[index] + 4)
self.pc_next_list[index] = ila.ite(
self.pc_list[index] == self.current_pc, pc_jmp,
self.pc_next_list[index])
self.current_pc += 4
def property_test2(self):
bar_spec = ptxILA.barSpec()
self.a_is_second_bar = (self.pc_a == 12 * instruction_format.MEM_BITS /
8)
self.a_previous_is_second_bar = self.model.bit(
'a_previous_is_second_bar')
self.model.set_next('a_previous_is_second_bar', self.a_is_second_bar)
self.a_cross_second_bar_flag = self.model.bit(
'a_cross_second_bar_flag')
self.model.set_next(
'a_cross_second_bar_flag',
ila.ite((self.a_is_second_bar == ila.bool(False)) &
(self.a_previous_is_second_bar == ila.bool(True)),
ila.bool(True), self.a_cross_second_bar_flag))
self.b_is_second_bar = (self.pc_b == ila.const(
12 * instruction_format.MEM_BITS / 8, instruction_format.PC_BITS))
self.b_come_to_second_bar_flag = self.model.bit(
'b_come_to_second_bar_flag')
self.model.set_next(
'b_come_to_second_bar_flag',
ila.ite(self.b_is_second_bar, ila.bool(True),
self.b_come_to_second_bar_flag))
self.predicate_two = self.model.bit('predicate_two')
self.model.set_next('predicate_two', (~self.a_cross_second_bar_flag) |
(self.b_come_to_second_bar_flag))
self.model.set_init('a_previous_is_second_bar', self.model.bool(False))
self.model.set_init('a_cross_second_bar_flag', self.model.bool(False))
self.model.set_init('b_come_to_second_bar_flag',
self.model.bool(False))
self.model.set_init('predicate_two', self.model.bool(True))
golden = ila.Abstraction('golden')
g_prop = golden.bit('prop')
golden.set_next('prop', golden.bool(True))
golden.set_init('prop', golden.bool(True))
ila.bmc(10, self.model, self.predicate_two, 1, golden, g_prop)
def ptxSample(self):
bar_spec = barSpec()
return ila.ite(
self.bar_state == bar_spec.BAR_ENTER,
ila.ite(
self.bar_counter_exit != 0,
ila.const(bar_spec.BAR_ENTER, bar_spec.BAR_STATE_BITS),
ila.ite(self.bar_counter_enter == (self.bar_counter_max - 1),
ila.const(bar_spec.BAR_EXIT, bar_spec.BAR_STATE_BITS),
ila.const(bar_spec.BAR_WAIT,
bar_spec.BAR_STATE_BITS))),
ila.ite(
self.bar_state == bar_spec.BAR_WAIT,
ila.ite(self.bar_counter_enter == self.bar_counter_max,
ila.const(bar_spec.BAR_EXIT, bar_spec.BAR_STATE_BITS),
ila.const(bar_spec.BAR_WAIT, bar_spec.BAR_STATE_BITS)),
ila.ite(
self.bar_state == bar_spec.BAR_EXIT,
ila.const(bar_spec.BAR_FINISH, bar_spec.BAR_STATE_BITS),
self.bar_state)))
def createConst(self):
self.pred_one = ila.const(0x1, instruction_format.PRED_REG_BITS)
self.pred_zero = ila.const(0x0, instruction_format.PRED_REG_BITS)
pred_map_obj = open('pred_map', 'r')
self.pred_map = pickle.load(pred_map_obj)
pred_map_obj.close()
def fulltable(inp):
expr = ila.const(0,8)
for i in range(256):
val = ila.const(innerTable[i],8)
expr = ila.ite(inp == i, val, expr )
return expr
def createConst(self):
self.pred_one = ila.const(0x1, instruction_format.PRED_REG_BITS)
self.pred_zero = ila.const(0x0, instruction_format.PRED_REG_BITS)
def ssa_next_state(self):
self.model.set_next('pc', self.pc + 4)
instruction_book_obj = open('instruction_book', 'r')
instruction_book = instruction_book_obj.readlines()
current_pc = 0
next_state_finished = []
for program_line in program:
if len(program_line) < 2:
continue
opcode = program_line[0]
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
opcode_length = int(opcode_split[-1][1:])
current_pc_in = current_pc
if opcode_name == 'ld':
dest_type = ssa_declaration[program_line[1]]
addr_type = ssa_declaration[program_line[2]]
dest_length = int(dest_type[2:])
addr_length = int(addr_type[2:])
dest_reg = self.model.getreg(program_line[1])
addr_reg = self.model.getreg(program_line[2])
if dest_length > instruction_format.DMEM_BITS:
dest = ila.sign_extend(self.mem[addr_reg[(instruction_format.MEM_ADDRESS_BITS - 1) : 0]], dest_length)
elif dest_length == instruction_format.DMEM_BITS:
dest = self.mem[addr_reg[(instruction_format.MEM_ADDRESS_BITS - 1) : 0]]
else:
dest_interim = self.mem[addr_reg[(instruction_format.MEM_ADDRESS_BITS - 1) : 0]]
dest = dest_interim[(dest_length - 1) : 0]
self.model.set_next(program_line[1], ila.ite(self.pc == current_pc, dest, dest_reg))
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'cvta':
dest_type = ssa_declaration[program_line[1]]
src_type = ssa_declaration[program_line[2]]
dest_length = int(dest_type[2:])
src_length = int(src_type[2:])
dest = self.model.getreg(program_line[1])
src = self.model.getreg(program_line[2])
if dest_length > src_length:
src = ila.sign_extend(src, dest_length)
if dest_length < src_length:
src = src[(dest_length - 1) : 0]
self.model.set_next(program_line[1], ila.ite(self.pc == current_pc, src, dest))
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'mov':
dest_type = ssa_declaration[program_line[1]]
src_type = ssa_declaration[program_line[2]]
dest_length = int(dest_type[2:])
src_length = int(src_type[2:])
dest = self.model.getreg(program_line[1])
src = self.model.getreg(program_line[2])
if dest_length > src_length:
src = ila.sign_extend(src, dest_length)
if dest_length < src_length:
src = src[(dest_length - 1) : 0]
self.model.set_next(program_line[1], ila.ite(self.pc == current_pc, src, dest))
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'add':
dest = self.model.getreg(program_line[1])
src0 = self.model.getreg(program_line[2])
src1 = self.model.getreg(program_line[3])
dest_type = ssa_declaration[program_line[1]]
src0_type = ssa_declaration[program_line[2]]
src1_type = ssa_declaration[program_line[3]]
dest_length = int(dest_type[2:])
src0_length = int(src0_type[2:])
src1_length = int(src1_type[2:])
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
if dest_length < src0_length:
src0 = src0[(dest_length - 1) : 0]
if dest_length > src1_length:
src1 = ila.sign_extend(src1, dest_length)
if dest_length < src1_length:
src1 = src1[(dest_length - 1) : 0]
self.model.set_next(program_line[1], ila.ite(self.pc == current_pc, src0 + src1, dest))
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'mul':
dest_type = ssa_declaration[program_line[1]]
src0_type = ssa_declaration[program_line[2]]
dest_length = int(dest_type[2:])
src0_length = int(src0_type[2:])
dest = self.model.getreg(program_line[1])
src0 = self.model.getreg(program_line[2])
src1 = ila.const(int(program_line[3]), dest_length)
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
if dest_length < src0_length:
src0 = src0[(dest_length - 1) : 0]
self.model.set_next(program_line[1], ila.ite(self.pc == current_pc, src0 * src1, dest))
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'st':
addr = self.model.getreg(program_line[1])
src = self.model.getreg(program_line[2])
self.model.set_next('mem', ila.ite(self.pc == current_pc,ila.store(self.mem, addr[(instruction_format.MEM_ADDRESS_BITS - 1):0], src[(instruction_format.DMEM_BITS - 1):0]), self.mem))
current_pc += 4
if current_pc == current_pc_in:
print program_line
a = self.model.reg('support', 32)
self.model.set_next('support', self.model.getreg('s3') + self.model.getreg('s1'))
for reg_name in ssa_declaration.keys():
if reg_name not in next_state_finished:
reg = self.model.getreg(reg_name)
self.model.set_next(reg_name, reg)
src0_type = ssa_declaration[program_line[2]]
dest_length = int(dest_type[2:])
src0_length = int(src0_type[2:])
dest = self.model.getreg(program_line[1])
src0 = self.model.getreg(program_line[2])
src1 = ila.const(int(program_line[3]), dest_length)
if dest_length > src0_length:
src0 = ila.sign_extend(src0, dest_length)
if dest_length < src0_length:
src0 = src0[(dest_length - 1) : 0]
self.model.set_next(program_line[1], ila.ite(self.pc == current_pc, src0 * src1, dest))
next_state_finished.append(program_line[1])
current_pc += 4
if opcode_name == 'st':
addr = self.model.getreg(program_line[1])
src = self.model.getreg(program_line[2])
self.model.set_next('mem', ila.ite(self.pc == current_pc,ila.store(self.mem, addr[(instruction_format.MEM_ADDRESS_BITS - 1):0], src[(instruction_format.DMEM_BITS - 1):0]), self.mem))
current_pc += 4
if current_pc == current_pc_in:
print program_line
a = self.model.reg('support', 32)
self.model.set_next('support', self.model.getreg('s3') + self.model.getreg('s1'))
for reg_name in ssa_declaration.keys():
if reg_name not in next_state_finished:
reg = self.model.getreg(reg_name)
self.model.set_next(reg_name, reg)
ptx = ptxGPUModel()
ptx.model.set_init('pc', ila.const(0x0, 32))
print ila.bmc(2, ptx.model, ptx.model.getreg('s4'), 2, ptx.model, ptx.model.getreg('support'))
def pc_nxt(self):
self.pcPlus4 = self.pc + ila.const(0b100, instruction_format.PC_BITS)
self.branchPC = self.pcPlus4 + self.branchImm
return ila.choice("pc_nxt", [self.pc, self.pcPlus4, self.branchPC])
def perform_instruction(self, index, program_line, pc_target):
if len(program_line) < 2:
return
opcode = program_line[0]
opcode_split = re.split('\.', opcode)
opcode_name = opcode_split[0]
if opcode_name != '@':
op_preds = []
if self.current_pc in self.pred_map.keys():
op_preds = self.pred_map[self.current_pc]
conj_pred = ila.bool(True)
for op_pred in op_preds:
if op_pred[0] == '-':
op_pred_name = op_pred[1:]
pred_cmp = self.pred_zero
else:
op_pred_name = op_pred
pred_cmp = self.pred_one
op_pred_reg = self.model.getreg(op_pred_name + '_%d' % (index))
conj_pred = conj_pred & (op_pred_reg == pred_cmp)
self.next_state_finished.append(program_line[1])
if opcode_name == 'bar':
op_len = 0
else:
op_len = int(opcode_split[-1][1:])
src_list = []
for i in range(2, len(program_line)):
src_str = program_line[i]
src_components = re.split('\+', src_str)
for i in range(len(src_components)):
src_component = src_components[i]
src_components[i] = self.aux_imm(src_component, index,
op_len)
src_sum = src_components[0]
for i in range(1, len(src_components)):
src_sum = src_sum + src_components[0]
src_list.append(src_sum)
dest = self.aux_dest(program_line[0], src_list, index)
if not dest:
self.current_pc += 4
return
dest_str = program_line[1]
dest = self.adjust_dest(index, dest, dest_str, op_len)
ns = self.next_state_dict[dest_str + '_%d' % (index)]
self.next_state_dict[dest_str + '_%d' % (index)] = ila.ite(
self.pc_list[index] == self.current_pc,
ila.ite(conj_pred, dest, ns), ns)
self.current_pc += 4
return
else:
op_preds = []
if self.current_pc in self.pred_map.keys():
op_preds = self.pred_map[self.current_pc]
conj_pred0 = ila.bool(True)
conj_pred1 = ila.bool(True)
for op_pred in op_preds:
if op_pred[0] == '-':
op_pred_name = op_pred[1:]
pred_cmp = self.pred_zero
else:
op_pred_name = op_pred
pred_cmp = self.pred_one
opcode_pred = self.model.getreg(op_pred_name + '_%d' % (0))
conj_pred0 = conj_pred0 & (opcode_pred == pred_cmp)
opcode_pred = self.model.getreg(op_pred_name + '_%d' % (1))
conj_pred1 = conj_pred1 & (opcode_pred == pred_cmp)
target = pc_target[program_line[3]]
if self.current_pc < target:
pc_jmp = ila.ite(conj_pred0 & conj_pred1,
ila.const(target, instruction_format.PC_BITS),
self.pc_list[index] + 4)
self.pc_next_list[index] = ila.ite(
self.pc_list[index] == self.current_pc, pc_jmp,
self.pc_next_list[index])
else:
pc_jmp = ila.ite(conj_pred0 | conj_pred1,
ila.const(target, instruction_format.PC_BITS),
self.pc_list[index] + 4)
self.pc_next_list[index] = ila.ite(
self.pc_list[index] == self.current_pc, pc_jmp,
self.pc_next_list[index])
self.current_pc += 4