def _make_v_eq_j(j: int, v_bits: SignalsTuple) -> Expr: j_bits = '0' * (len(v_bits) - len(bin(j)[2:])) + bin(j)[2:] v_eq_j = _conjunction([ BinOp('=', v_bits[idx], Number(1)) if j_bit == '1' else ~BinOp('=', v_bits[idx], Number(1)) for idx, j_bit in enumerate(j_bits) ]) return v_eq_j
def visit_binary_op(self, binary_op: BinOp): if binary_op.name == 'W': bin_op_expr = BinOp('+', BinOp('U', binary_op.arg1, binary_op.arg2), UnaryOp('G', binary_op.arg1)) return self.dispatch(bin_op_expr) else: return super().visit_binary_op(binary_op)
def visit_binary_op(self, binary_op:BinOp): if binary_op.name == '=': return BinOp('=', self.dispatch(binary_op.arg1), self.dispatch(binary_op.arg2)) dual_op_name = '*+'[binary_op.name == '*'] return BinOp(dual_op_name, self.dispatch(binary_op.arg1), self.dispatch(binary_op.arg2))
def visit_unary_op(self, unary_op: UnaryOp): if unary_op.name != '!': return UnaryOp(unary_op.name, self.dispatch(unary_op.arg)) # Check if the negation is in front of the proposition... arg = unary_op.arg if arg.name == '=': return unary_op # ... and if not, then propagate the negation downwards: if arg.name in 'UR*+': return BinOp(self._get_dual_op_name(arg.name), self.dispatch(~arg.arg1), self.dispatch(~arg.arg2)) if arg.name in 'AEGFX': return UnaryOp(self._get_dual_op_name(arg.name), self.dispatch(~arg.arg)) assert 0, str(unary_op)
def visit_binary_op(self, binary_op: BinOp): return BinOp(binary_op.name, self.dispatch(binary_op.arg1), self.dispatch(binary_op.arg2))
def sig_prop(name:str) -> Tuple[Signal, BinOp]: return Signal(name),\ BinOp('=', Signal(name), Number(1))
def R(a1, a2) -> BinOp: return BinOp('R', a1, a2) def prop(name:str) -> BinOp: return BinOp('=', Signal(name), Number(1))
def W(a1, a2) -> BinOp: return BinOp('W', a1, a2) def R(a1, a2) -> BinOp: return BinOp('R', a1, a2)
def U(a1, a2) -> BinOp: return BinOp('U', a1, a2) def W(a1, a2) -> BinOp: return BinOp('W', a1, a2)