def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# lcd
self.submodules.lcd = SPIMaster(platform.request("lcd_spi"))
self.submodules.rs = Led(platform.request("rs_lcd"))
self.submodules.rst = Led(platform.request("rst_lcd"))
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
interrupt_map = {
"botones": 4,
}
SoCCore.interrupt_map.update(interrupt_map)
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
#botones con interrupcion
bot = Cat(*[platform.request("boton", i) for i in range(8)])
self.submodules.botones = btnintrupt(bot)
# lcd
self.submodules.lcd = SPIMaster(platform.request("lcd_spi"))
self.submodules.rs = Led(platform.request("rs_lcd"))
self.submodules.rst = Led(platform.request("rst_lcd"))
#Memoria SD
self.submodules.SD = SPIMaster(platform.request("sd_spi"))
def __init__(self, revision):
platform = colorlight_5a_75e.Platform(revision)
sys_clk_freq = int(25e6)
platform.add_extension(_serial)
platform.add_extension(_leds)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="vexriscv",
clk_freq=25e6,
ident="LiteX CPU Test SoC 5A-75E",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x4000)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk25"),
~platform.request("user_btn_n"))
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(2)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
def __init__(self, platform):
sys_clk_freq = int(32e6)
# SoC with CPU
SC.SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=32e6,
csr_data_width=32,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk32"),
~platform.request("cpu_reset"))
self.submodules.led = Led(platform.request("led01", 0))
self.submodules.button = Button(platform.request("button01", 0))
# interrupts declaration
interrupt_map = {
"button": 4,
}
SC.SoCCore.interrupt_map.update(interrupt_map)
print(SC.SoCCore.interrupt_map)
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
interrupt_map = {
"buttoniner": 4,
}
SoCCore.interrupt_map.update(interrupt_map)
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(8)])
self.submodules.leds = Led(user_leds)
# Buttons interrupcion
bten = Cat(*[platform.request("user_btn", i) for i in range(8)])
self.submodules.buttoniner = btnintrupt(bten)
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SC.SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
csr_data_width=32,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk32"),
~platform.request("cpu_reset"))
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(9)])
self.submodules.leds = Led(user_leds)
# Spi
self.submodules.spi = SPIMaster(platform.request("spi_master"))
# control_lcd
control_lcd = Cat(
*[platform.request("control_lcd", i) for i in range(3)])
self.submodules.ctrllcd = gpio.GPIOOut(control_lcd)
self.submodules.i2s = I2S(platform.request("i2s_"))
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
csr_data_width=32,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# lcd
self.submodules.spi_sd = SPIMaster(platform.request("SD"))
self.comb += platform.request("uCD").eq(0x1)
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
csr_data_width=32,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# lcd
self.submodules.SD = SPIMaster(platform.request("sd_spi"))
#sdcard
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="vexriscv",
clk_freq=100e6,
ident="LiteX CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x4000)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
self.add_csr("switches")
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
self.add_csr("buttons")
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
self.add_csr("rgbled")
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"),
data_width=32,
sys_clk_freq=sys_clk_freq,
spi_clk_freq=1e6)
self.add_csr("adxl362")
# SevenSegmentDisplay
self.submodules.display = SevenSegmentDisplay(sys_clk_freq)
self.add_csr("display")
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform, **kwargs):
sys_clk_freq = int(32e6)
# SoC init (No CPU, we controlling the SoC with UART)
sc.SoCCore.__init__(
self,
platform,
sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False,
ident="My first System On Chip",
ident_version=True,
# shadow_base=0x00000000,
)
print(sc.SoCCore.csr_map)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk32"),
~platform.request("cpu_reset"))
# No CPU, use Serial to control Wishbone bus
self.add_cpu(
UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu.wishbone)
# FPGA identification
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(9)])
self.submodules.leds = Led(user_leds)
print(sc.SoCCore.csr_map)
def __init__(self, revision):
platform = colorlight_5a_75b.Platform(revision)
sys_clk_freq = int(25e6)
# custom serial using j1 pins instead of led & button
platform.add_extension(_serialx)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="vexriscv",
clk_freq=25e6,
ident="LiteX CPU Test SoC 5A-75B",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x4000,
uart_name="serialJx")
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk25"), 0)
# Led
user_leds = Cat(*[platform.request("user_led_n", i) for i in range(1)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
interrupt_map = {
"buttons": 4,
}
SoCCore.interrupt_map.update(interrupt_map)
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=32 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(8)])
self.submodules.buttons = btnintrupt(user_buttons)
#LedAzul
user_led = Cat(*[platform.request("led_GB", i) for i in range(1)])
self.submodules.led_GB = Led(user_led)
#spiLCD
user_control = Cat(
*[platform.request("pantalla_control", i) for i in range(3)])
self.submodules.pantalla_spi = SPIMaster(
platform.request("pantalla_spi"))
self.submodules.pantalla_control = Led(user_control)
#spiSd
user_control_sd = Cat(
*[platform.request("sdcard_v", i) for i in range(1)])
self.submodules.sdcard_spi = SPIMaster(platform.request("sdcard_spi"))
self.submodules.sdcard_v = Led(user_control_sd)
print(SoCCore.interrupt_map)
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
# SoC init (No CPU, we controlling the SoC with UART)
SoCCore.__init__(
self,
platform,
sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False,
ident="My first System On Chip",
ident_version=True,
)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# No CPU, use Serial to control Wishbone bus
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"))
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform):
sys_clk_freq = int(100e6)
SoCCore.__init__(
self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024,
)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"))
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
# SD
self.submodules.SD = SD(platform.request("SD"),
platform.request("butt"), "csr")
# LCD
self.submodules.LCD = SPIMaster(platform.request("LCD"))
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
# SoCMini (No CPU, we are controlling the SoC over UART)
SoCMini.__init__(self, platform, sys_clk_freq, csr_data_width=32,
ident="My first LiteX System On Chip", ident_version=True)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset"))
# No CPU, use Serial to control Wishbone bus
self.submodules.serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq)
self.add_wb_master(self.serial_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
# Switches
user_switches = Cat(*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
self.add_csr("switches")
# Buttons
user_buttons = Cat(*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
self.add_csr("buttons")
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
self.add_csr("rgbled")
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"),
data_width = 32,
sys_clk_freq = sys_clk_freq,
spi_clk_freq = 1e6)
self.add_csr("adxl362")
# SevenSegmentDisplay
self.submodules.display = SevenSegmentDisplay(sys_clk_freq)
self.add_csr("display")
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self, platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC", ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16*1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Switches
user_switches = Cat(*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
# Buttons
user_buttons = Cat(*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# lcd
self.submodules.lcd = SPIMaster(platform.request("lcd_spi"))
self.submodules.rs = Led(platform.request("rs_lcd"))
self.submodules.rst = Led(platform.request("rst_lcd"))
#sdcard
#self.submodules.sdcard = SDCore(platform.request("sd_spi"))
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform, **kwargs):
sys_clk_freq = int(1 / platform.default_clk_period * 1000000000)
SoCCore.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv",
# cpu_variant="debug",
# cpu_type="picorv32",
# cpu_type="lm32",
csr_data_width=32,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024,
ident="Wir trampeln durchs Getreide ...",
ident_version=True)
for c in [
"dna",
"xadc",
"rgbled",
"leds",
# "switches",
"buttons"
# "adxl362",
# "display"
]:
self.add_csr(c)
# self.submodules.bridge = uart.UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
# self.add_wb_master(self.bridge.wishbone)
# self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu_or_bridge.debug_bus, 0x10)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk12"),
platform.request("user_btn"))
# FPGA identification
self.submodules.dna = dna.DNA()
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
# Led
user_leds = Cat(*[platform.request("user_led") for i in range(2)])
self.submodules.leds = Led(user_leds)
# Buttons
user_buttons = Cat(*[platform.request("user_btn") for i in range(1)])
self.submodules.buttons = Button(user_buttons)
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("rgb_leds"))
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
csr_data_width=32,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=35 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
#RS y RST LCD
rs = platform.request("lcd_rs")
self.submodules.rs = Led(rs)
rst = platform.request("lcd_rst")
rst = 1
# Buttons
bttn = Cat(*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = button_intr(bttn)
#GPO
self.submodules.GPO = Led(platform.request("GPO", 0))
#SD
self.submodules.SD = SPIMaster(platform.request("SD_spi"))
# LCD
self.submodules.lcd = SPIMaster(platform.request("lcd_spi"))
def __init__(self, platform):
sys_clk_freq = int(32e6)
# SoC with CPU
SC.SoCCore.__init__(self, platform,
cpu_type="lm32",
clk_freq=32e6,
ident="CPU Test SoC", ident_version=True,
integrated_rom_size=0x8000,
csr_data_width=32,
integrated_main_ram_size=16*1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk32"), ~platform.request("cpu_reset"))
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(9)])
self.submodules.leds = Led(user_leds)
def __init__(self, sys_clk_freq=int(83333333), **kwargs):
platform = Platform()
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="Alchitry Au SoC",
ident_version=True,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
if not self.integrated_main_ram_size:
self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
platform.request("ddram"),
memtype="DDR3",
nphases=4,
sys_clk_freq=sys_clk_freq)
self.add_csr("ddrphy")
self.add_sdram("sdram",
phy=self.ddrphy,
module=AS4C128M16(sys_clk_freq, "1:4"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x10000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get(
"min_l2_data_width", 128),
l2_cache_reverse=True)
# No CPU, use Serial to control Wishbone bus
#self.submodules.serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq)
#self.add_wb_master(self.serial_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(8)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SC.SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
csr_data_width=32,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk32"),
~platform.request("cpu_reset"))
# Spi
self.submodules.i2c = I2C_MAster(platform.request("i2c_master"))
self.submodules.leds = Led(user_leds)
def __init__(self, sys_clk_freq=int(66666666), **kwargs):
platform = Platform()
SoCCore.__init__(self,
platform,
sys_clk_freq,
ident="Mojo V3 SoC",
ident_version=True,
**kwargs)
self.submodules.crg = _CRG(platform, sys_clk_freq)
# SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size:
#self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.submodules.sdrphy = HalfRateGENSDRPHY(
platform.request("sdram"))
self.add_sdram(
"sdram",
phy=self.sdrphy,
#module = MT48LC32M8(sys_clk_freq, "1:1"),
module=MT48LC32M8(sys_clk_freq, "1:2"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x2000000),
l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_min_data_width=kwargs.get("min_l2_data_width", 128),
l2_cache_reverse=True)
# No CPU, use Serial to control Wishbone bus
#self.submodules.serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq)
#self.add_wb_master(self.serial_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(8)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(8)])
self.submodules.leds = Led(user_leds)
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(8)])
self.submodules.switches = Switch(user_switches)
def __init__(self,
board,
revision,
with_ethernet=False,
with_etherbone=False,
sys_clk_freq=60e6,
**kwargs):
SoCCore.mem_map = {
"rom": 0x00000000,
"sram": 0x10000000,
"spiflash": 0x20000000,
"main_ram": 0x40000000,
"csr": 0x82000000,
}
board = board.lower()
assert board in ["5a-75e"]
if board == "5a-75e":
platform = colorlight_5a_75e.Platform(revision=revision)
# platform.add_extension(_serial)
if with_etherbone:
sys_clk_freq = int(125e6)
# SoCCore -----------------------------------------------------------
SoCCore.__init__(
self,
platform,
cpu_type="vexriscv",
# cpu_variant="lite+debug",
# cpu_variant="lite",
cpu_variant="linux",
csr_data_width=8,
# csr_data_width=32,
ident="LiTex Johnny RiscV",
# max_sdram_size=0x400000,
ident_version=True,
# cpu_reset_address=0x0,
# integrated_rom_size=0x8000,
# integrated_main_ram_size=0x4000)
# integrated_main_ram_size=0x0,
clk_freq=sys_clk_freq,
**kwargs)
# CRG ---------------------------------------------------------------
with_rst = kwargs["uart_name"] not in ["serial", "bridge"]
with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
self.submodules.crg = _CRG(platform,
sys_clk_freq,
with_usb_pll=with_usb_pll,
with_rst=with_rst)
# SDR SDRAM ---------------------------------------------------------
if not self.integrated_main_ram_size:
self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"))
self.add_sdram(
"sdram",
phy=self.sdrphy,
module=M12L16161A(sys_clk_freq, "1:1"),
origin=self.mem_map["main_ram"],
size=kwargs.get("max_sdram_size", 0x40000000),
# l2_cache_size=kwargs.get("l2_size", 8192),
l2_cache_size=kwargs.get("l2_size", 0x8000),
# 0x8000 = 32kiB, 32KiB * 128 = 4096KiB
l2_cache_min_data_width=kwargs.get("min_l2_data_width", 128),
l2_cache_reverse=True)
# Ethernet / Etherbone ----------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
clock_pads=self.platform.request("eth_clocks"),
pads=self.platform.request("eth"))
self.add_csr("ethphy")
if with_ethernet:
self.add_ethernet(phy=self.ethphy)
if with_etherbone:
self.add_etherbone(phy=self.ethphy)
# Wishbone-UART bridge ----------------------------------------------
# self.submodules.serial_bridge = UARTWishboneBridge(
# platform.request("serial", 1),
# sys_clk_freq)
# self.add_wb_master(self.serial_bridge.wishbone)
# CPU DBG ----------------------------------------------------------
# self.register_mem(
# "vexriscv_lite_debug",
# 0xf00f0000,
# self.cpu.debug_bus,
# 0x10)
# LEDs -------------------------------------------------------------
user_leds = Cat(*[platform.request("user_led", i) for i in range(2)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")