def __init__(self, platform):
sys_clk_freq = int(100e6)
# SoC with CPU
SoCCore.__init__(self,
platform,
cpu_type="vexriscv",
clk_freq=100e6,
ident="LiteX CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=0x4000)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
self.add_csr("switches")
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
self.add_csr("buttons")
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
self.add_csr("rgbled")
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"),
data_width=32,
sys_clk_freq=sys_clk_freq,
spi_clk_freq=1e6)
self.add_csr("adxl362")
# SevenSegmentDisplay
self.submodules.display = SevenSegmentDisplay(sys_clk_freq)
self.add_csr("display")
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
# SoC init (No CPU, we controlling the SoC with UART)
SoCCore.__init__(
self,
platform,
sys_clk_freq,
cpu_type=None,
csr_data_width=32,
with_uart=False,
with_timer=False,
ident="My first System On Chip",
ident_version=True,
)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# No CPU, use Serial to control Wishbone bus
self.add_cpu_or_bridge(
UARTWishboneBridge(platform.request("serial"),
sys_clk_freq,
baudrate=115200))
self.add_wb_master(self.cpu_or_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"))
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform):
sys_clk_freq = int(100e6)
SoCCore.__init__(
self,
platform,
cpu_type="lm32",
clk_freq=100e6,
ident="CPU Test SoC",
ident_version=True,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024,
)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"),
~platform.request("cpu_reset"))
# FPGA identification
self.submodules.dna = dna.DNA()
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
# Switches
user_switches = Cat(
*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
# Buttons
user_buttons = Cat(
*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"))
# Display
self.submodules.display = Display(sys_clk_freq)
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
# SD
self.submodules.SD = SD(platform.request("SD"),
platform.request("butt"), "csr")
# LCD
self.submodules.LCD = SPIMaster(platform.request("LCD"))
def __init__(self, platform, **kwargs):
sys_clk_freq = int(100e6)
# SoCMini (No CPU, we are controlling the SoC over UART)
SoCMini.__init__(self, platform, sys_clk_freq, csr_data_width=32,
ident="My first LiteX System On Chip", ident_version=True)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk100"), ~platform.request("cpu_reset"))
# No CPU, use Serial to control Wishbone bus
self.submodules.serial_bridge = UARTWishboneBridge(platform.request("serial"), sys_clk_freq)
self.add_wb_master(self.serial_bridge.wishbone)
# FPGA identification
self.submodules.dna = dna.DNA()
self.add_csr("dna")
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
self.add_csr("xadc")
# Led
user_leds = Cat(*[platform.request("user_led", i) for i in range(16)])
self.submodules.leds = Led(user_leds)
self.add_csr("leds")
# Switches
user_switches = Cat(*[platform.request("user_sw", i) for i in range(16)])
self.submodules.switches = Switch(user_switches)
self.add_csr("switches")
# Buttons
user_buttons = Cat(*[platform.request("user_btn", i) for i in range(5)])
self.submodules.buttons = Button(user_buttons)
self.add_csr("buttons")
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("user_rgb_led", 0))
self.add_csr("rgbled")
# Accelerometer
self.submodules.adxl362 = SPIMaster(platform.request("adxl362_spi"),
data_width = 32,
sys_clk_freq = sys_clk_freq,
spi_clk_freq = 1e6)
self.add_csr("adxl362")
# SevenSegmentDisplay
self.submodules.display = SevenSegmentDisplay(sys_clk_freq)
self.add_csr("display")
self.comb += [
platform.request("display_cs_n").eq(~self.display.cs),
platform.request("display_abcdefg").eq(~self.display.abcdefg)
]
def __init__(self, platform, **kwargs):
sys_clk_freq = int(1 / platform.default_clk_period * 1000000000)
SoCCore.__init__(
self,
platform,
sys_clk_freq,
cpu_type="vexriscv",
# cpu_variant="debug",
# cpu_type="picorv32",
# cpu_type="lm32",
csr_data_width=32,
integrated_rom_size=0x8000,
integrated_main_ram_size=16 * 1024,
ident="Wir trampeln durchs Getreide ...",
ident_version=True)
for c in [
"dna",
"xadc",
"rgbled",
"leds",
# "switches",
"buttons"
# "adxl362",
# "display"
]:
self.add_csr(c)
# self.submodules.bridge = uart.UARTWishboneBridge(platform.request("serial"), sys_clk_freq, baudrate=115200)
# self.add_wb_master(self.bridge.wishbone)
# self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu_or_bridge.debug_bus, 0x10)
# Clock Reset Generation
self.submodules.crg = CRG(platform.request("clk12"),
platform.request("user_btn"))
# FPGA identification
self.submodules.dna = dna.DNA()
# FPGA Temperature/Voltage
self.submodules.xadc = xadc.XADC()
# Led
user_leds = Cat(*[platform.request("user_led") for i in range(2)])
self.submodules.leds = Led(user_leds)
# Buttons
user_buttons = Cat(*[platform.request("user_btn") for i in range(1)])
self.submodules.buttons = Button(user_buttons)
# RGB Led
self.submodules.rgbled = RGBLed(platform.request("rgb_leds"))