def __init__(self, *, reset_addr, clk_freq, rom_addr, rom_size, ram_addr,
ram_size, uart_addr, uart_divisor, uart_pins, timer_addr,
timer_width):
self._arbiter = wishbone.Arbiter(addr_width=30,
data_width=32,
granularity=8,
features={"cti", "bte"})
self._decoder = wishbone.Decoder(addr_width=30,
data_width=32,
granularity=8,
features={"cti", "bte"})
self.cpu = MinervaCPU(reset_address=reset_addr)
self._arbiter.add(self.cpu.ibus)
self._arbiter.add(self.cpu.dbus)
self.rom = SRAMPeripheral(size=rom_size, writable=False)
self._decoder.add(self.rom.bus, addr=rom_addr)
self.ram = SRAMPeripheral(size=ram_size)
self._decoder.add(self.ram.bus, addr=ram_addr)
self.uart = AsyncSerialPeripheral(divisor=uart_divisor, pins=uart_pins)
self._decoder.add(self.uart.bus, addr=uart_addr)
self.timer = TimerPeripheral(width=timer_width)
self._decoder.add(self.timer.bus, addr=timer_addr)
self.intc = GenericInterruptController(width=len(self.cpu.ip))
self.intc.add_irq(self.timer.irq, 0)
self.intc.add_irq(self.uart.irq, 1)
self.memory_map = self._decoder.bus.memory_map
self.clk_freq = clk_freq
def __init__(self, *,
uart_pins, ddr_pins,
ddrphy_addr, dramcore_addr,
ddr_addr):
self._arbiter = wishbone.Arbiter(addr_width=30, data_width=32, granularity=8,
features={"cti", "bte"})
self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
features={"cti", "bte"})
freq = 100e6
self.crg = ECPIX5CRG()
self.cpu = MinervaCPU(reset_address=0)
self._arbiter.add(self.cpu.ibus)
self._arbiter.add(self.cpu.dbus)
self.intc = GenericInterruptController(width=len(self.cpu.ip))
self.rom = SRAMPeripheral(size=4096, writable=False)
with open("firmware/main.bin", "rb") as f:
words = iter(lambda: f.read(self.cpu.data_width // 8), b'')
bios = [int.from_bytes(w, self.cpu.byteorder) for w in words]
self.rom.init = bios
self._decoder.add(self.rom.bus, addr=0)
self.ram = SRAMPeripheral(size=4096)
self._decoder.add(self.ram.bus, addr=0x1000)
self.uart = AsyncSerialPeripheral(divisor=int(freq//115200), pins=uart_pins)
self._decoder.add(self.uart.bus, addr=0x2000)
self.ddrphy = DomainRenamer("dramsync")(ECP5DDRPHY(ddr_pins))
self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
ddrmodule = MT41K256M16(freq, "1:2")
self.dramcore = DomainRenamer("dramsync")(gramCore(
phy=self.ddrphy,
geom_settings=ddrmodule.geom_settings,
timing_settings=ddrmodule.timing_settings,
clk_freq=freq))
self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
self.drambone = DomainRenamer("dramsync")(gramWishbone(self.dramcore))
self._decoder.add(self.drambone.bus, addr=ddr_addr)
self.memory_map = self._decoder.bus.memory_map
self.clk_freq = freq
def add_bios_and_peripherals(self,
uart_pins,
uart_baud_rate=115200,
fixed_addresses=False):
""" Adds a simple BIOS that allows loading firmware, and the requisite peripherals.
Automatically adds the following peripherals:
self.uart -- An AsyncSerialPeripheral used for serial I/O.
self.timer -- A TimerPeripheral used for BIOS timing.
self.rom -- A ROM memory used for the BIOS.
self.ram -- The RAM used by the BIOS; not typically the program RAM.
Parameters:
uart_pins -- The UARTResource to be used for UART communications; or an equivalent record.
uart_baud_rate -- The baud rate to be used by the BIOS' uart.
"""
self._build_bios = True
self._uart_baud = uart_baud_rate
# Add our RAM and ROM.
# Note that these names are from CPUSoC, and thus must not be changed.
#
# Here, we're using SRAMPeripherals instead of our more flexible ones,
# as that's what the lambdasoc BIOS expects. These are effectively internal.
#
addr = 0x0000_0000 if fixed_addresses else None
self.rom = SRAMPeripheral(size=0x4000, writable=False)
self.add_peripheral(self.rom, addr=addr)
addr = 0x0001_0000 if fixed_addresses else None
self.ram = SRAMPeripheral(size=0x1000)
self.add_peripheral(self.ram, addr=addr)
# Add our UART and Timer.
# Again, names are fixed.
addr = 0x0002_0000 if fixed_addresses else None
self.timer = TimerPeripheral(width=32)
self.add_peripheral(self.timer, addr=addr)
addr = 0x0003_0000 if fixed_addresses else None
self.uart = AsyncSerialPeripheral(divisor=int(self.clk_freq //
uart_baud_rate),
pins=uart_pins)
self.add_peripheral(self.uart, addr=addr)
def __init__(self, *, ram_addr, ram_size, uart_addr, uart_divisor,
uart_pins):
self._arbiter = wishbone.Arbiter(addr_width=30,
data_width=32,
granularity=8)
self._decoder = wishbone.Decoder(addr_width=30,
data_width=32,
granularity=8,
features={"cti", "bte"})
self.ram = SRAMPeripheral(size=ram_size)
self._decoder.add(self.ram.bus, addr=ram_addr)
self.bridge = UARTBridge(divisor=uart_divisor, pins=uart_pins)