def add_synthetic_edges(conn, graph, node_mapping, grid, synth_tiles):
cur = conn.cursor()
delayless_switch = graph.get_switch_id('__vpr_delayless_switch__')
for tile_name, synth_tile in synth_tiles['tiles'].items():
assert len(synth_tile['pins']) == 1
for pin in synth_tile['pins']:
if pin['port_type'] in ['input', 'output']:
wire_pkey = get_wire_pkey(conn, tile_name, pin['wire'])
cur.execute(
"""
SELECT
track_pkey
FROM
node
WHERE
pkey = (
SELECT
node_pkey
FROM
wire
WHERE
pkey = ?
);""", (wire_pkey, ))
(track_pkey, ) = cur.fetchone()
assert track_pkey is not None, (tile_name, pin['wire'],
wire_pkey)
elif pin['port_type'] == 'VCC':
cur.execute('SELECT vcc_track_pkey FROM constant_sources')
(track_pkey, ) = cur.fetchone()
elif pin['port_type'] == 'GND':
cur.execute('SELECT gnd_track_pkey FROM constant_sources')
(track_pkey, ) = cur.fetchone()
else:
assert False, pin['port_type']
tracks_model, track_nodes = get_track_model(conn, track_pkey)
option = list(
tracks_model.get_tracks_for_wire_at_coord(
tuple(synth_tile['loc'])).values())
assert len(option) > 0, (pin, len(option))
if pin['port_type'] == 'input':
tile_type = 'SYN-OUTPAD'
wire = 'outpad'
elif pin['port_type'] == 'output':
tile_type = 'SYN-INPAD'
wire = 'inpad'
elif pin['port_type'] == 'VCC':
tile_type = 'SYN-VCC'
wire = 'VCC'
elif pin['port_type'] == 'GND':
tile_type = 'SYN-GND'
wire = 'GND'
else:
assert False, pin
track_node = track_nodes[option[0]]
assert track_node in node_mapping, (track_node, track_pkey)
pin_name = graph.create_pin_name_from_tile_type_and_pin(
tile_type, wire)
pin_node = graph.get_nodes_for_pin(tuple(synth_tile['loc']),
pin_name)
if pin['port_type'] == 'input':
graph.add_edge(
src_node=node_mapping[track_node],
sink_node=pin_node[0][0],
switch_id=delayless_switch,
name='synth_{}_{}'.format(tile_name, pin['wire']),
)
elif pin['port_type'] in ['VCC', 'GND', 'output']:
graph.add_edge(
src_node=pin_node[0][0],
sink_node=node_mapping[track_node],
switch_id=delayless_switch,
name='synth_{}_{}'.format(tile_name, pin['wire']),
)
else:
assert False, pin
def add_synthetic_edges(conn, graph, node_mapping, grid, synth_tiles):
c = conn.cursor()
routing_switch = graph.get_switch_id('routing')
for loc in grid.tile_locations():
tile_name = grid.tilename_at_loc(loc)
if tile_name in synth_tiles['tiles']:
assert len(synth_tiles['tiles'][tile_name]['pins']) == 1
for pin in synth_tiles['tiles'][tile_name]['pins']:
wire_pkey = get_wire_pkey(conn, tile_name, pin['wire'])
c.execute(
"""
SELECT
track_pkey
FROM
node
WHERE
pkey = (
SELECT
node_pkey
FROM
wire
WHERE
pkey = ?
);""", (wire_pkey, ))
(track_pkey, ) = c.fetchone()
assert track_pkey is not None, (tile_name, pin['wire'],
wire_pkey)
tracks_model, track_nodes = get_track_model(conn, track_pkey)
option = list(tracks_model.get_tracks_for_wire_at_coord(loc))
assert len(option) > 0
if pin['port_type'] == 'input':
tile_type = 'BLK_SY-OUTPAD'
wire = 'outpad'
elif pin['port_type'] == 'output':
tile_type = 'BLK_SY-INPAD'
wire = 'inpad'
else:
assert False, pin
track_node = track_nodes[option[0][0]]
assert track_node in node_mapping, (track_node, track_pkey)
pin_name = graph.create_pin_name_from_tile_type_and_pin(
tile_type, wire)
pin_node = graph.get_nodes_for_pin(loc, pin_name)
if pin['port_type'] == 'input':
graph.add_edge(
src_node=node_mapping[track_node],
sink_node=pin_node[0][0],
switch_id=routing_switch,
name='synth_{}_{}'.format(tile_name, pin['wire']),
)
elif pin['port_type'] == 'output':
graph.add_edge(
src_node=pin_node[0][0],
sink_node=node_mapping[track_node],
switch_id=routing_switch,
name='synth_{}_{}'.format(tile_name, pin['wire']),
)
else:
assert False, pin
