def set_sessionid_by_token(self, token_str):
token_str = tornado.escape.native_str(token_str)
val = Mem.get(token_str)
if val is not None and val != 'token':
self._session_id = val
self._request.set_secure_cookie("SESSIONID", self._session_id, self._expires_days)
Mem.delete(token_str)
def get(self, key):
val = Mem.get(self._session_id)
if val is not None:
Mem.set(self._session_id, val, self._time_out)
if val.has_key(key):
return val[key]
return None
def set(self, key, value):
ret = False
val = Mem.get(self._session_id)
if val is None or isinstance(val, dict) == False:
val = dict()
val[key] = value
ret = Mem.set(self._session_id, val, self._time_out)
return ret
def generate_token(self):
token_str = self._session.generate_uuid()
if Mem.set(token_str, 'token',
config.setting['session']['token_time_out']) == False:
return None
else:
return token_str
def nt_gen_replay_top_test(dut):
"""Test bench main function."""
# start the clock
cocotb.fork(clk_gen(dut.clk, CLK_FREQ_MHZ))
# no software reset
dut.rst_sw <= 0
# reset dut
yield rstn(dut.clk, dut.rstn)
# open trace file
trace = File("files/random.file")
# get trace file size
trace_size = trace.size()
# trace file must be a multiple of the AXI data width
if trace.size() % (AXI_MEM_BIT_WIDTH / 8) != 0:
raise cocotb.result.TestFailure("invalid trace size")
# calculate ring buffer sizes
ring_buff_sizes = []
for ring_buff_size in RING_BUFF_SIZES:
# size of ring buffer is determined by multiplying the size factor by
# the size of the trace
ring_buff_size = int(ring_buff_size * trace_size)
# make sure that the ring buffer size is multiple of AXI data width
if ring_buff_size % (AXI_MEM_BIT_WIDTH / 8) != 0:
ring_buff_size += AXI_MEM_BIT_WIDTH/8 - \
ring_buff_size % (AXI_MEM_BIT_WIDTH/8)
ring_buff_sizes.append(ring_buff_size)
# create a ring buffer memory (initially of size 0) and connect it to the
# DUT
ring_buff = Mem(0)
ring_buff.connect(dut, "ddr3")
# create axi lite writer, connect and reset
axi_lite_writer = AXI_Lite_Writer()
axi_lite_writer.connect(dut, dut.clk, AXI_LITE_BIT_WIDTH, "ctrl")
yield axi_lite_writer.rst()
# create axi lite reader, connect and reset
axi_lite_reader = AXI_Lite_Reader()
axi_lite_reader.connect(dut, dut.clk, AXI_LITE_BIT_WIDTH, "ctrl")
yield axi_lite_reader.rst()
# create axi stream reader, connect and reset
axis_reader = AXIS_Reader()
axis_reader.connect(dut, dut.clk, AXIS_BIT_WIDTH)
yield axis_reader.rst()
# start the ring buffer memory main routine
cocotb.fork(ring_buff.main())
# toggle m_axis_tready
cocotb.fork(toggle_signal(dut.clk, dut.m_axis_tready))
# iterate over all ring buffer sizes
for i, ring_buff_size in enumerate(ring_buff_sizes):
# set ring buffer size
ring_buff.set_size(ring_buff_size)
# iterate over all addresses where ring buffer shall be located in
# memory
for j, ring_buff_addr in enumerate(RING_BUFF_ADDRS):
# print status
print("Test %d/%d" % (i * len(RING_BUFF_ADDRS) + j + 1,
len(RING_BUFF_ADDRS) * len(RING_BUFF_SIZES)))
print("Ring Buff Addr: 0x%x, Size: %d" %
(ring_buff_addr, ring_buff_size))
# we have a total of 8 GByte of memory. Make sure the ring buffer
# fits at the desired address
if ring_buff_addr + ring_buff_size > 0x1FFFFFFFF:
raise cocotb.result.TestFailure("ring buffer is too large")
# to reduce the simulation memory footprint, provide the memory
# module the first memory address that we acutally care about
ring_buff.set_offset(ring_buff_addr)
# configure ring buffer memory location
yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_MEM_ADDR_HI,
ring_buff_addr >> 32)
yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_MEM_ADDR_LO,
ring_buff_addr & 0xFFFFFFFF)
# configure ring buffer address range
yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_MEM_RANGE,
ring_buff_size - 1)
# configure trace size
yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_TRACE_SIZE_HI,
trace_size >> 32)
yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_TRACE_SIZE_LO,
trace_size & 0xFFFFFFFF)
# reset write address pointer
yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_ADDR_WR, 0x0)
# make sure module initially is inactive
status = yield axi_lite_reader.read(CPUREG_OFFSET_STATUS)
if status & 0x3 != 0:
raise cocotb.reset.TestFailure("module is active")
# start the module
yield axi_lite_writer.write(CPUREG_OFFSET_CTRL_START, 0x1)
# wait a few cycles
yield wait_n_cycles(dut.clk, 10)
# start writing the ring buffer
cocotb.fork(
ring_buff_write(dut, ring_buff, trace, ring_buff_addr,
axi_lite_reader, axi_lite_writer))
# start coroutine that checks dut output
coroutine_chk_out = cocotb.fork(
check_output(dut, trace, axis_reader))
# wait a few cycles and make sure module is active
yield wait_n_cycles(dut.clk, 10)
status = yield axi_lite_reader.read(CPUREG_OFFSET_STATUS)
if status & 0x1 == 0x0:
raise cocotb.result.TestFailure("mem read not active")
if status & 0x2 == 0x0:
raise cocotb.result.TestFailure("packet assembly not active")
# wait for output check to complete
yield coroutine_chk_out.join()
# wait a few cycles
yield wait_n_cycles(dut.clk, 10)
# make sure module is now inactive
status = yield axi_lite_reader.read(CPUREG_OFFSET_STATUS)
if status & 0x3 != 0x0:
raise cocotb.result.TestFailure("module does not become " +
"inactive")
# clear the ring buffer contents
ring_buff.clear()
# close the trace file
trace.close()
def destroy(self):
Mem.delete(self._session_id)
def nt_recv_capture_top_test(dut):
"""Test bench main function."""
# start the clock
cocotb.fork(clk_gen(dut.clk, CLK_FREQ_MHZ))
# no software reset
dut.rst_sw <= 0
# reset DuT
yield rstn(dut.clk, dut.rstn)
# create AXI4-Lite writer, connect and reset it
axilite_writer = AXI_Lite_Writer()
axilite_writer.connect(dut, dut.clk, AXI_CTRL_BIT_WIDTH, "ctrl")
yield axilite_writer.rst()
# create AXI4-Lite reader, connect and reset it
axilite_reader = AXI_Lite_Reader()
axilite_reader.connect(dut, dut.clk, AXI_CTRL_BIT_WIDTH, "ctrl")
yield axilite_reader.rst()
# create AXI4-Stream writer, connect and reset it
axis_writer = AXIS_Writer()
axis_writer.connect(dut, dut.clk, AXIS_BIT_WIDTH)
yield axis_writer.rst()
# create a ring buffer memory (initially of size 0) and connect it to the
# DuT
ring_buff = Mem(0)
ring_buff.connect(dut, "ddr3")
# generate a couple of random Ethernet packets. For each packet, generate
# a 16 bit latency value and a 26 bit inter-packet time value
pkts = []
latencies = []
inter_packet_times = []
for _ in range(N_PACKETS):
pkts.append(gen_packet())
latencies.append(random.randint(0, 2**24 - 1))
inter_packet_times.append(random.randint(0, 2**28 - 1))
# start the ring buffer memory main routine
cocotb.fork(ring_buff.main())
# wait some more clock cycles
yield wait_n_cycles(dut.clk, 5)
# iterate over all ring buffer sizes
for i, ring_buff_size in enumerate(RING_BUFF_SIZES):
# set ring buffer size
ring_buff.set_size(ring_buff_size)
# iterate over all adderesses where ring buffer shall be located in
# memory
for j, ring_buff_addr in enumerate(RING_BUFF_ADDRS):
# print status
print("Test %d/%d (this will take a while)" %
(i * len(RING_BUFF_ADDRS) + j + 1,
len(RING_BUFF_ADDRS) * len(RING_BUFF_SIZES)))
# we have a total of 8 GByte of memory. Make sure the ring buffer
# fits at the desired address
if ring_buff_addr + ring_buff_size > 0x1FFFFFFFF:
raise cocotb.result.TestFailure("ring buffer is too large")
# to reduce the simulation memory footprint, provide the memory
# module the first memory address that we actually care about
ring_buff.set_offset(ring_buff_addr)
# write ring buffer memory location and address range
yield axilite_writer.write(CPUREG_OFFSET_CTRL_MEM_ADDR_HI,
ring_buff_addr >> 32)
yield axilite_writer.write(CPUREG_OFFSET_CTRL_MEM_ADDR_LO,
ring_buff_addr & 0xFFFFFFFF)
yield axilite_writer.write(CPUREG_OFFSET_CTRL_MEM_RANGE,
ring_buff_size - 1)
# itererate over all capture lengths
for max_len_capture in MAX_CAPTURE_LENS:
# reset read address pointer
yield axilite_writer.write(CPUREG_OFFSET_CTRL_ADDR_RD, 0x0)
# set max capture length
yield axilite_writer.write(CPUREG_OFFSET_CTRL_MAX_LEN_CAPTURE,
max_len_capture)
# start couroutine that applies packets at input
cocotb.fork(
packets_write(dut, axis_writer, axilite_writer,
axilite_reader, pkts, latencies,
inter_packet_times))
# wait a bit
yield wait_n_cycles(dut.clk, 50)
# start the ring buffer read coroutine and wait until it
# completes
yield ring_buff_read(dut, axilite_writer, axilite_reader,
ring_buff, ring_buff_addr,
max_len_capture, pkts, latencies,
inter_packet_times)
# make sure no error occured
errs = yield axilite_reader.read(CPUREG_OFFSET_STATUS_ERRS)
assert errs == 0x0
# make sure packet count is correct
pkt_cnt = \
yield axilite_reader.read(CPUREG_OFFSET_STATUS_PKT_CNT)
assert pkt_cnt == len(pkts)
# make sure module is deactivated now
active = yield axilite_reader.read(CPUREG_OFFSET_STATUS_ACTIVE)
assert active == 0
# clear the ring buffer contents
ring_buff.clear()
(r"/entity/unselect", view.entity.EntityUnSelectHandler),
(r"/entity/top", view.entity.EntityTopHandler),
(r"/entity/untop", view.entity.EntityUnTopHandler),
(r"/entity/released", view.entity.EntityReleasedHandler),
(r"/package", view.package.PackageHandler),
(r".*", view.index.ErrorHandler)]
application = Application(
urls,
cookie_secret="qg6iZZuQSSmfKlYKyjB19dr+q9MfcEN7re2VNDEP5Sw=",
login_url="/login",
template_path=config.setting['template'],
static_path=config.setting['static'],
debug=True,
xsrf_cookies=False, #True
autoescape=None)
# http://127.0.0.1:8888/
if __name__ == "__main__":
reload(sys)
sys.setdefaultencoding("utf-8")
Log.start(config.setting['log_path'], Log.DEBUG)
Mem.start(config.setting['mem']['host'], config.setting['mem']['port'])
http_server = HTTPServer(application, xheaders=True)
if len(sys.argv) >= 2:
http_server.listen(int(sys.argv[1]))
else:
http_server.listen(config.setting['listen_port'])
tornado.autoreload.start(IOLoop.instance(), 500)
IOLoop.instance().start()
def clear_cache(self, key):
Mem.delete(key)
def get_cache(self, key):
return Mem.get(key)
def set_cache(self, key, val, time_out):
return Mem.set(key, val, time_out)
def nt_gen_replay_mem_read_test(dut):
"""Test bench main function."""
# open trace file
trace = File("files/random.file")
# get trace file size
trace_size = trace.size()
# trace file size must be a multiple of AXI data width
if trace.size() % (AXI_BIT_WIDTH / 8) != 0:
raise cocotb.result.TestFailure("invalid trace size")
# calculate ring buffer sizes
ring_buff_sizes = []
for ring_buff_size in RING_BUFF_SIZES:
# size of ring buffer is determined by multiplying the size factor by
# the size of the trace
ring_buff_size = int(ring_buff_size * trace_size)
# make sure that the ring buffer size is multiple of AXI data width
if ring_buff_size % (AXI_BIT_WIDTH / 8) != 0:
ring_buff_size += AXI_BIT_WIDTH/8 - ring_buff_size % \
(AXI_BIT_WIDTH/8)
ring_buff_sizes.append(ring_buff_size)
# create a ring buffer memory (initially of size 0) and connect it to the
# DUT
ring_buff = Mem(0)
ring_buff.connect(dut)
# start the clock
cocotb.fork(clk_gen(dut.clk, CLK_FREQ_MHZ))
# deassert sw reset
dut.rst_sw <= 0
# initially module start is not triggered
dut.ctrl_start_i <= 0
# reset dut
yield rstn(dut.clk, dut.rstn)
# start the ring buffer memory main routine
cocotb.fork(ring_buff.main())
# wait some more clock cycles
yield wait_n_cycles(dut.clk, 5)
# randomly toggle fifo_prog_full input signal
dut.fifo_prog_full_i <= 0
cocotb.fork(toggle_signal(dut.clk, dut.fifo_prog_full_i))
# iterate over all ring buffer sizes
for i, ring_buff_size in enumerate(ring_buff_sizes):
# set ring buffer size
ring_buff.set_size(ring_buff_size)
# iterate over all adderesses where ring buffer shall be located in
# memory
for j, ring_buff_addr in enumerate(RING_BUFF_ADDRS):
# print status
print("Test %d/%d" % (i * len(RING_BUFF_ADDRS) + j + 1,
len(RING_BUFF_ADDRS) * len(RING_BUFF_SIZES)))
# we have a total of 8 GByte of memory. Make sure the ring buffer
# fits at the desired address
if ring_buff_addr + ring_buff_size > 0x1FFFFFFFF:
raise cocotb.result.TestFailure("ring buffer is too large")
# to reduce the simulation memory footprint, provide the memory
# module the first memory address that we actually care about
ring_buff.set_offset(ring_buff_addr)
# apply ring buffer memory location to dut
dut.ctrl_mem_addr_hi_i <= ring_buff_addr >> 32
dut.ctrl_mem_addr_lo_i <= ring_buff_addr & 0xFFFFFFFF
# apply ring buffer address range to dut
dut.ctrl_mem_range_i <= ring_buff_size - 1
# apply trace size to dut
dut.ctrl_trace_size_hi_i <= trace_size >> 32
dut.ctrl_trace_size_lo_i <= trace_size & 0xFFFFFFFF
# reset write address pointer
dut.ctrl_addr_wr_i <= 0
# start reading from the ring buffer
dut.ctrl_start_i <= 1
yield RisingEdge(dut.clk)
dut.ctrl_start_i <= 0
yield RisingEdge(dut.clk)
# start writing the ring buffer
cocotb.fork(ring_buff_write(dut, ring_buff, trace))
# start checking dut output and wait until it completes
yield cocotb.fork(check_output(dut, trace)).join()
# clear the ring buffer contents
ring_buff.clear()
# close trace file
trace.close()
def nt_recv_capture_mem_write_test(dut):
"""Test bench main function."""
# open file with random content
try:
f = File("files/random.file")
except IOError:
raise cocotb.result.TestFailure("Generate input data by calling " +
"'./create_random.py' in 'files' " +
"folder!")
# file size must be a multiple of AXI data width
if f.size() % (BIT_WIDTH_MEM_WRITE / 8) != 0:
raise cocotb.result.TestFailure("invalid input data size")
# create a ring buffer memory (initially of size 0) and connect it to the
# DuT
ring_buff = Mem(0)
ring_buff.connect(dut)
# start the clock
cocotb.fork(clk_gen(dut.clk, CLK_FREQ_MHZ))
# deassert sw reset
dut.rst_sw <= 0
# initially module is disabled
dut.active_i <= 0
# initially no FIFO flush
dut.flush_i <= 0
# reset DuT
yield rstn(dut.clk, dut.rstn)
# start the ring buffer memory main routine
cocotb.fork(ring_buff.main())
# wait some more clock cycles
yield wait_n_cycles(dut.clk, 5)
# iterate over all ring buffer sizes
for i, ring_buff_size in enumerate(RING_BUFF_SIZES):
# set ring buffer size
ring_buff.set_size(ring_buff_size)
# iterate over all adderesses where ring buffer shall be located in
# memory
for j, ring_buff_addr in enumerate(RING_BUFF_ADDRS):
# print status
print("Test %d/%d" % (i * len(RING_BUFF_ADDRS) + j + 1,
len(RING_BUFF_ADDRS) * len(RING_BUFF_SIZES)))
# we have a total of 8 GByte of memory. Make sure the ring buffer
# fits at the desired address
if ring_buff_addr + ring_buff_size > 0x1FFFFFFFF:
raise cocotb.result.TestFailure("ring buffer is too large")
# to reduce the simulation memory footprint, provide the memory
# module the first memory address that we actually care about
ring_buff.set_offset(ring_buff_addr)
# apply ring buffer memory location to dut
dut.mem_addr_hi_i <= ring_buff_addr >> 32
dut.mem_addr_lo_i <= ring_buff_addr & 0xFFFFFFFF
# apply ring buffer address range to dut
dut.mem_range_i <= ring_buff_size - 1
# reset read address pointer
dut.addr_rd_i <= 0
# start a couroutine that applies input data
cocotb.fork(apply_input(dut, f))
# wait a few clock cycles
yield wait_n_cycles(dut.clk, 10)
# start the ring buffer read coroutine and wait until it completes
yield ring_buff_read(dut, ring_buff, f)
# clear the ring buffer contents
ring_buff.clear()
# close file
f.close()