def __init__(self, dut, num_samples, input_width):
self.clk = Clock(dut.clk, 40)
self.clk_en = ClockEnable(dut.clk, dut.clk_en, dut.rst_n, 20)
self.dut = dut
self.inputs = random_samples(input_width, num_samples)
self.coeffs = np.kaiser(num_samples, 6)
self.outputs = np.multiply(self.inputs, self.coeffs)
def __init__(self, dut, num_samples, input_width):
clk = Clock(dut.clk_i, 40)
clk_3x = Clock(dut.clk_3x_i, 120)
self.multiclock = MultiClock([clk, clk_3x])
self.dut = dut
self.re_inputs = random_samples(input_width, num_samples)
self.im_inputs = random_samples(input_width, num_samples)
self.outputs = np.fft.fft(self.re_inputs + 1j * self.im_inputs)
def __init__(self, dut, num_samples, input_width, tap_width):
self.clk = Clock(dut.clk, 40)
self.clk_en = ClockEnable(dut.clk, dut.clk_2mhz_pos_en, dut.rst_n, 20)
self.dut = dut
self.inputs = random_samples(input_width, num_samples)
self.downsample_factor = 20
self.fir = FIR(
numtaps=120,
bands=[0, 0.95e6, 1e6, 20e6],
band_gain=[1, 0],
fs=40e6,
pass_db=0.5,
stop_db=-40,
)
self.taps = self.fir.taps
self.outputs = self.gen_outputs()
class WindowTB:
"""
Window testbench class.
"""
def __init__(self, dut, num_samples, input_width):
self.clk = Clock(dut.clk, 40)
self.clk_en = ClockEnable(dut.clk, dut.clk_en, dut.rst_n, 20)
self.dut = dut
self.inputs = random_samples(input_width, num_samples)
self.coeffs = np.kaiser(num_samples, 6)
self.outputs = np.multiply(self.inputs, self.coeffs)
@cocotb.coroutine
async def setup(self):
"""
Initialize window.
"""
cocotb.fork(self.clk.start())
cocotb.fork(self.clk_en.start())
await self.reset()
@cocotb.coroutine
async def reset(self):
"""
Start window in a known state.
"""
await RisingEdge(self.dut.clk)
self.dut.rst_n <= 0
await RisingEdge(self.dut.clk)
self.dut.rst_n <= 1
@cocotb.coroutine
async def write_continuous(self):
"""
Continously write inputs. When inputs have been exhausted, write
zeros.
"""
sample_ctr = 0
num_samples = len(self.inputs)
while True:
if sample_ctr < num_samples:
self.dut.di <= self.inputs[sample_ctr].item()
self.dut.en <= 1
else:
self.dut.di <= 0
self.dut.en <= 0
sample_ctr += 1
await FallingEdge(self.dut.clk_en)
class ShiftRegTB:
def __init__(self, dut):
self.clk = Clock(dut.clk, 40)
self.dut = dut
@cocotb.coroutine
async def setup(self):
cocotb.fork(self.clk.start())
await self.reset()
self.dut.ce <= 1
@cocotb.coroutine
async def reset(self):
await RisingEdge(self.dut.clk)
self.dut.rst_n <= 0
await RisingEdge(self.dut.clk)
self.dut.rst_n <= 1
def __init__(self, dut):
fst_clk = Clock(dut.fst_clk, 80)
slw_clk = Clock(dut.slw_clk, 10)
self.multiclock = MultiClock([fst_clk, slw_clk])
self.dut = dut
def __init__(self, dut):
self.clk = Clock(dut.clk, 40)
self.dut = dut
def test_normalize_periods_for_simulation():
clocks = MultiClock([Clock(None, 60, 0), Clock(None, 40, 0)])
for clk in clocks.clocks:
print("period: {}, phase: {}".format(clk.period, clk.phase))
assert True
def __init__(self, dut):
rdclk = Clock(dut.rdclk, 60)
wrclk = Clock(dut.wrclk, 40)
self.multiclock = MultiClock([rdclk, wrclk])
self.dut = dut
class FIRTB:
"""
FIR testbench class.
"""
def __init__(self, dut, num_samples, input_width, tap_width):
self.clk = Clock(dut.clk, 40)
self.clk_en = ClockEnable(dut.clk, dut.clk_2mhz_pos_en, dut.rst_n, 20)
self.dut = dut
self.inputs = random_samples(input_width, num_samples)
self.downsample_factor = 20
self.fir = FIR(
numtaps=120,
bands=[0, 0.95e6, 1e6, 20e6],
band_gain=[1, 0],
fs=40e6,
pass_db=0.5,
stop_db=-40,
)
self.taps = self.fir.taps
self.outputs = self.gen_outputs()
@cocotb.coroutine
async def setup(self):
"""
Initialize FIR filter in a defined state.
"""
cocotb.fork(self.clk.start())
cocotb.fork(self.clk_en.start())
await self.reset()
@cocotb.coroutine
async def reset(self):
"""
Assert a reset and ensure it's registered by the clock.
"""
await RisingEdge(self.dut.clk)
self.dut.rst_n <= 0
await RisingEdge(self.dut.clk)
self.dut.rst_n <= 1
@cocotb.coroutine
async def write_continuous(self):
"""
Continously write inputs. When inputs have been exhausted, write
zeros.
"""
sample_ctr = 0
num_samples = len(self.inputs)
while True:
if sample_ctr < num_samples:
self.dut.din <= self.inputs[sample_ctr].item()
else:
self.dut.din <= 0
sample_ctr += 1
await RisingEdge(self.dut.clk)
def gen_outputs(self):
"""
Generate expected outputs.
"""
out_pre_dec = np.convolve(self.inputs, self.taps)
# use convergent rounding
outputs = [
out_pre_dec[i]
# int(np.around(out_pre_dec[i]))
for i in range(len(out_pre_dec)) if i % self.downsample_factor == 0
]
# Drop the first value. This ensures that the first output
# gets the full 2MHz cycle of inputs.
return outputs[1:]
def __init__(self, dut):
clk = Clock(dut.clk, 40)
ft_clk = Clock(dut.ft_clk, 60)
slow_ft_clk = Clock(dut.slow_ft_clk, 7.5)
self.multiclock = MultiClock([clk, ft_clk, slow_ft_clk])
self.dut = dut