def checkBlock(self, strAddr): #global misses #global hits # checkBlock checks for the given address in the cache. # Returns true if it finds the block, false if it does not tag = self.pullTag(strAddr) setNum = self.pullSet(strAddr) #print setNum set = self._lines[setNum] #print "new set:" for i in set: iTag = i.tag #print "iTag =", iTag, "tag =", tag, "i.valid =", i.valid if iTag == tag and i.valid == 1: #print iTag, tag #update LRU order self.adjustLRU(setNum, i) return True newLine = Line() newLine.address = strAddr newLine.valid = 1 newLine.dirty = 0 newLine.tag = tag self._lines[setNum].appendleft(newLine) # Add it to our cache. return False
def checkBlockWrite(self, strAddr): # checkBlockWrite handles the case where we need to write to tag = self.pullTag(strAddr) setNum = self.pullSet(strAddr) set = self._lines[setNum] for i in set: iTag = i.tag if iTag == tag and i.valid == 1: #update LRU order i.dirty = 1 self.adjustLRU(setNum, i) return True newLine = Line() newLine.address = strAddr newLine.valid = 1 newLine.dirty = 1 newLine.tag = tag self._lines[setNum].appendleft(newLine) return False
total = 0 i = 0 blockSize = 0 misses = 0 hits = 0 hmFlag = 0 for line in f: sepLine = line.split() if len(sepLine) != 3: continue sepLine[0] = sepLine[0][:-1] sepLine[2] = sepLine[2].strip("\n") if assoc != 0 and assoc < (cacheSize // cache_line_size): cache.setTag(sepLine[2]) newLine = Line() newLine.address = sepLine[2] total += 1 if sepLine[1] == "R": if assoc == 0 or assoc > (cacheSize // cache_line_size): # Full associative hmFlag = 0 for l in cacheList: #print newLine.address,l.address,l.valid if newLine.address == l.address: #print "match" cacheList.remove(l) newLine.valid == 1 cacheList.appendleft(newLine) hmFlag = 1 break if (hmFlag == 1):