def __init__(self):
self.write_user_port = LiteDRAMWritePort(aw=32, dw=32)
self.write_crossbar_port = LiteDRAMWritePort(aw=32, dw=128)
self.submodules.write_converter = LiteDRAMPortConverter(self.write_user_port,
self.write_crossbar_port)
self.read_user_port = LiteDRAMReadPort(aw=32, dw=32)
self.read_crossbar_port = LiteDRAMReadPort(aw=32, dw=128)
self.submodules.read_converter = LiteDRAMPortConverter(self.read_user_port,
self.read_crossbar_port)
self.memory = DRAMMemory(128, 128)
def get_port(self, mode="both", dw=None, cd="sys", reverse=False):
if self.finalized:
raise FinalizeError
if dw is None:
dw = self.dw
# crossbar port
port = LiteDRAMPort(mode, self.rca_bits + self.bank_bits, self.dw,
"sys")
self.masters.append(port)
# clock domain crossing
if cd != "sys":
new_port = LiteDRAMPort(mode, port.aw, port.dw, cd)
self.submodules += LiteDRAMPortCDC(new_port, port)
port = new_port
# data width convertion
if dw != self.dw:
if dw > self.dw:
adr_shift = -log2_int(dw // self.dw)
else:
adr_shift = log2_int(self.dw // dw)
new_port = LiteDRAMPort(mode, port.aw + adr_shift, dw, cd=cd)
self.submodules += ClockDomainsRenamer(cd)(LiteDRAMPortConverter(
new_port, port, reverse))
port = new_port
return port
def __init__(self):
# write port and converter
self.write_user_port = LiteDRAMWritePort(aw=32, dw=32)
self.write_crossbar_port = LiteDRAMWritePort(aw=32, dw=128)
write_converter = LiteDRAMPortConverter(self.write_user_port,
self.write_crossbar_port)
self.submodules += write_converter
# read port and converter
self.read_user_port = LiteDRAMReadPort(aw=32, dw=32)
self.read_crossbar_port = LiteDRAMReadPort(aw=32, dw=128)
read_converter = LiteDRAMPortConverter(self.read_user_port,
self.read_crossbar_port)
self.submodules += read_converter
# memory
self.memory = DRAMMemory(128, 128)